From 45ff58cfd1555a6ee0586a5f8810fc2eafdd3153 Mon Sep 17 00:00:00 2001
From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun, 30 Oct 2022 16:31:04 +0100
Subject: [PATCH] radv: Handle GSVS ring intrinsic correctly with LLVM.

If we don't set progress to false we get a mess as a replacement is
still attempted.

Fixes: 382831c9865 ("radv,nir: add intrinsics for streamout and GS copy shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>
---
 src/amd/vulkan/radv_nir_lower_abi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c
index 6f097a8003b..e2895e03ab0 100644
--- a/src/amd/vulkan/radv_nir_lower_abi.c
+++ b/src/amd/vulkan/radv_nir_lower_abi.c
@@ -125,8 +125,10 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
       replacement = load_ring(b, stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS : RING_ESGS_VS, s);
       break;
    case nir_intrinsic_load_ring_gsvs_amd:
-      if (s->use_llvm)
+      if (s->use_llvm) {
+         progress = false;
          break;
+      }
 
       replacement = load_ring(b, RING_GSVS_VS, s);
       break;