brw: Change destination of memory fences to UD type

For some reason, we were using UW type for the destination of memory
fences at the generator level, while in the IR we selected UD.

There are some comments in the documentation for the message about it
writing the notification register to the destination, which is 32-bit.
Prior to Xe2, bits 31:16 were Reserved/MBZ.  But on Xe2, all 32 bits
are populated with actual data.

I don't know whether this will fix anything in practice, but it seems
like a better plan to use UD.  Often we used UW types to avoid having
the destination region of sends span too many registers, but we're in
SIMD1 here, so it shouldn't matter.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>

src/intel/compiler/brw_eu_emit.c

@@ -1785,7 +1785,7 @@ brw_memory_fence(struct brw_codegen *p,
 {
    const struct intel_device_info *devinfo = p->devinfo;
 
-   dst = retype(vec1(dst), BRW_TYPE_UW);
+   dst = retype(vec1(dst), BRW_TYPE_UD);
    src = retype(vec1(src), BRW_TYPE_UD);
 
    /* Set dst as destination for dependency tracking, the MEMORY_FENCE