From 43d0ac9eb478c9af50ecb9f39b3106ea3b3c7b63 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 17 Jan 2025 23:07:24 -0800 Subject: [PATCH] brw: Change destination of memory fences to UD type For some reason, we were using UW type for the destination of memory fences at the generator level, while in the IR we selected UD. There are some comments in the documentation for the message about it writing the notification register to the destination, which is 32-bit. Prior to Xe2, bits 31:16 were Reserved/MBZ. But on Xe2, all 32 bits are populated with actual data. I don't know whether this will fix anything in practice, but it seems like a better plan to use UD. Often we used UW types to avoid having the destination region of sends span too many registers, but we're in SIMD1 here, so it shouldn't matter. Acked-by: Caio Oliveira Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_eu_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 0d2c354cfcc..ed79303ea12 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -1785,7 +1785,7 @@ brw_memory_fence(struct brw_codegen *p, { const struct intel_device_info *devinfo = p->devinfo; - dst = retype(vec1(dst), BRW_TYPE_UW); + dst = retype(vec1(dst), BRW_TYPE_UD); src = retype(vec1(src), BRW_TYPE_UD); /* Set dst as destination for dependency tracking, the MEMORY_FENCE