pan/midg: Fix swizzle packing on 64bit instructions with src-expansion + dst-shrinking

In that case, the mask is specified on 32bit lanes, so we need to shift
it if it's > 0x3. The expand modifier will take care of selecting the
right side of the 32bit vector.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>

src/panfrost/midgard/midgard_emit.c

@@ -244,6 +244,12 @@ mir_pack_swizzle(unsigned mask, unsigned *swizzle,
                         bool lo = swizzle[0] >= COMPONENT_Z;
                         bool hi = swizzle[1] >= COMPONENT_Z;
 
+                        assert(!(mask & ~0xf));
+                        assert(!(mask & 0x3) || !(mask & 0xc));
+
+                        if (mask > 3)
+                                mask >>= 2;
+
                         if (mask & 0x1) {
                                 /* We can't mix halves... */
                                 if (mask & 2)