From 3f9bce08e10f7dc3c454f93764e8bf474ca1765d Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 9 Sep 2021 10:38:20 +0200 Subject: [PATCH] pan/midg: Fix swizzle packing on 64bit instructions with src-expansion + dst-shrinking In that case, the mask is specified on 32bit lanes, so we need to shift it if it's > 0x3. The expand modifier will take care of selecting the right side of the 32bit vector. Signed-off-by: Boris Brezillon Part-of: --- src/panfrost/midgard/midgard_emit.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c index fc5fa8eb1d1..7c6fbd27aa1 100644 --- a/src/panfrost/midgard/midgard_emit.c +++ b/src/panfrost/midgard/midgard_emit.c @@ -244,6 +244,12 @@ mir_pack_swizzle(unsigned mask, unsigned *swizzle, bool lo = swizzle[0] >= COMPONENT_Z; bool hi = swizzle[1] >= COMPONENT_Z; + assert(!(mask & ~0xf)); + assert(!(mask & 0x3) || !(mask & 0xc)); + + if (mask > 3) + mask >>= 2; + if (mask & 0x1) { /* We can't mix halves... */ if (mask & 2)