AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

brw: add instructions missing from is_control_flow()

Browse Source 
I'm not aware of any workloads that will be impacted by this change,
but let's keep our list of control flow instructions complete. A
shader-db run on MTL tells me nothing changes.

v2: "The scheduler relies on HALT not being considered control flow to
be able to move code past HALT instructions. Doing this would prevent
such optimization from happening and would reduce performance
dramatically in some cases." - Francisco.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33021>
This commit is contained in:
Paulo Zanoni
2025-01-09 16:31:52 -08:00
committed by Marge Bot
parent 0e87acb2f3
commit 3596b4e325
4 changed files with 19 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_inst.cpp
+11
View File
@@ -826,8 +826,19 @@ brw_inst::is_control_flow() const
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_JMPI:
case BRW_OPCODE_BRD:
case BRW_OPCODE_BRC:
case BRW_OPCODE_HALT:
case BRW_OPCODE_CALLA:
case BRW_OPCODE_CALL:
case BRW_OPCODE_GOTO:
case BRW_OPCODE_RET:
case SHADER_OPCODE_FLOW:
return true;
case BRW_OPCODE_MOV:
case BRW_OPCODE_ADD:
return dst.is_ip();
default:
return false;
}
src/intel/compiler/brw_reg.cpp
+6
View File
@@ -263,6 +263,12 @@ brw_reg::is_accumulator() const
return file == ARF && (nr & 0xF0) == BRW_ARF_ACCUMULATOR;
}
bool
brw_reg::is_ip() const
{
return file == ARF && (nr & 0xF0) == BRW_ARF_IP;
}
bool
brw_reg::is_address() const
{
src/intel/compiler/brw_reg.h
+1
View File
@@ -227,6 +227,7 @@ typedef struct brw_reg {
bool is_negative_one() const;
bool is_null() const;
bool is_accumulator() const;
bool is_ip() const;
bool is_address() const;
unsigned address_slot(unsigned byte_offset) const;
src/intel/compiler/brw_schedule_instructions.cpp
+1 -1
View File
@@ -1087,7 +1087,7 @@ static bool
is_scheduling_barrier(const brw_inst *inst)
{
return inst->opcode == SHADER_OPCODE_HALT_TARGET ||
inst->is_control_flow() ||
(inst->is_control_flow() && inst->opcode != BRW_OPCODE_HALT) ||
inst->has_side_effects();
}