From 3596b4e325d719a75e818789524482f22c9ad4de Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Thu, 9 Jan 2025 16:31:52 -0800 Subject: [PATCH] brw: add instructions missing from is_control_flow() I'm not aware of any workloads that will be impacted by this change, but let's keep our list of control flow instructions complete. A shader-db run on MTL tells me nothing changes. v2: "The scheduler relies on HALT not being considered control flow to be able to move code past HALT instructions. Doing this would prevent such optimization from happening and would reduce performance dramatically in some cases." - Francisco. Reviewed-by: Francisco Jerez Signed-off-by: Paulo Zanoni Part-of: --- src/intel/compiler/brw_inst.cpp | 11 +++++++++++ src/intel/compiler/brw_reg.cpp | 6 ++++++ src/intel/compiler/brw_reg.h | 1 + src/intel/compiler/brw_schedule_instructions.cpp | 2 +- 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_inst.cpp b/src/intel/compiler/brw_inst.cpp index b5cb9bb7337..1e899f38fcb 100644 --- a/src/intel/compiler/brw_inst.cpp +++ b/src/intel/compiler/brw_inst.cpp @@ -826,8 +826,19 @@ brw_inst::is_control_flow() const case BRW_OPCODE_ENDIF: case BRW_OPCODE_BREAK: case BRW_OPCODE_CONTINUE: + case BRW_OPCODE_JMPI: + case BRW_OPCODE_BRD: + case BRW_OPCODE_BRC: + case BRW_OPCODE_HALT: + case BRW_OPCODE_CALLA: + case BRW_OPCODE_CALL: + case BRW_OPCODE_GOTO: + case BRW_OPCODE_RET: case SHADER_OPCODE_FLOW: return true; + case BRW_OPCODE_MOV: + case BRW_OPCODE_ADD: + return dst.is_ip(); default: return false; } diff --git a/src/intel/compiler/brw_reg.cpp b/src/intel/compiler/brw_reg.cpp index aab993ba296..0b513001a30 100644 --- a/src/intel/compiler/brw_reg.cpp +++ b/src/intel/compiler/brw_reg.cpp @@ -263,6 +263,12 @@ brw_reg::is_accumulator() const return file == ARF && (nr & 0xF0) == BRW_ARF_ACCUMULATOR; } +bool +brw_reg::is_ip() const +{ + return file == ARF && (nr & 0xF0) == BRW_ARF_IP; +} + bool brw_reg::is_address() const { diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index 1c63f5c1623..ec966a41118 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -227,6 +227,7 @@ typedef struct brw_reg { bool is_negative_one() const; bool is_null() const; bool is_accumulator() const; + bool is_ip() const; bool is_address() const; unsigned address_slot(unsigned byte_offset) const; diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 192cbf5dca4..f0a27fbfead 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -1087,7 +1087,7 @@ static bool is_scheduling_barrier(const brw_inst *inst) { return inst->opcode == SHADER_OPCODE_HALT_TARGET || - inst->is_control_flow() || + (inst->is_control_flow() && inst->opcode != BRW_OPCODE_HALT) || inst->has_side_effects(); }