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i965/gen6+: Merge VS/GS and WM push constant buffer upload paths.

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt
2014-05-19 10:06:15 -07:00
committed by Kenneth Graunke
parent c0f1929dd2
commit 34f4e614dd
4 changed files with 52 additions and 66 deletions
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src/mesa/drivers/dri/i965/brw_context.h
+5 -5
View File
@@ -1780,11 +1780,11 @@ brw_setup_vec4_key_clip_info(struct brw_context *brw,
bool program_uses_clip_distance);
void
gen6_upload_vec4_push_constants(struct brw_context *brw,
const struct gl_program *prog,
const struct brw_vec4_prog_data *prog_data,
struct brw_stage_state *stage_state,
enum aub_state_struct_type type);
gen6_upload_push_constants(struct brw_context *brw,
const struct gl_program *prog,
const struct brw_stage_prog_data *prog_data,
struct brw_stage_state *stage_state,
enum aub_state_struct_type type);
/* ================================================================
* From linux kernel i386 header files, copes with odd sizes better
src/mesa/drivers/dri/i965/gen6_vs_state.c
+41 -20
View File
@@ -32,13 +32,29 @@
#include "program/prog_parameter.h"
#include "program/prog_statevars.h"
#include "intel_batchbuffer.h"
#include "glsl/glsl_parser_extras.h"
/**
* Creates a streamed BO containing the push constants for the VS or GS on
* gen6+.
*
* Push constants are constant values (such as GLSL uniforms) that are
* pre-loaded into a shader stage's register space at thread spawn time.
*
* Not all GLSL uniforms will be uploaded as push constants: The hardware has
* a limitation of 32 or 64 EU registers (256 or 512 floats) per stage to be
* uploaded as push constants, while GL 4.4 requires at least 1024 components
* to be usable for the VS. Plus, currently we always use pull constants
* instead of push constants when doing variable-index array access.
*
* See brw_curbe.c for the equivalent gen4/5 code.
*/
void
gen6_upload_vec4_push_constants(struct brw_context *brw,
const struct gl_program *prog,
const struct brw_vec4_prog_data *prog_data,
struct brw_stage_state *stage_state,
enum aub_state_struct_type type)
gen6_upload_push_constants(struct brw_context *brw,
const struct gl_program *prog,
const struct brw_stage_prog_data *prog_data,
struct brw_stage_state *stage_state,
enum aub_state_struct_type type)
{
struct gl_context *ctx = &brw->ctx;
@@ -48,15 +64,14 @@ gen6_upload_vec4_push_constants(struct brw_context *brw,
/* XXX: Should this happen somewhere before to get our state flag set? */
_mesa_load_state_parameters(ctx, prog->Parameters);
if (prog_data->base.nr_params == 0) {
if (prog_data->nr_params == 0) {
stage_state->push_const_size = 0;
} else {
int params_uploaded;
float *param;
int i;
param = brw_state_batch(brw, type,
prog_data->base.nr_params * sizeof(float),
prog_data->nr_params * sizeof(float),
32, &stage_state->push_const_offset);
/* _NEW_PROGRAM_CONSTANTS
@@ -65,21 +80,27 @@ gen6_upload_vec4_push_constants(struct brw_context *brw,
* side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
* wouldn't be set for them.
*/
for (i = 0; i < prog_data->base.nr_params; i++) {
param[i] = *prog_data->base.param[i];
for (i = 0; i < prog_data->nr_params; i++) {
param[i] = *prog_data->param[i];
}
params_uploaded = prog_data->base.nr_params / 4;
if (0) {
fprintf(stderr, "Constant buffer:\n");
for (i = 0; i < params_uploaded; i++) {
float *buf = param + i * 4;
fprintf(stderr, "%d: %f %f %f %f\n",
i, buf[0], buf[1], buf[2], buf[3]);
fprintf(stderr, "%s constants:\n",
_mesa_shader_stage_to_string(stage_state->stage));
for (i = 0; i < prog_data->nr_params; i++) {
if ((i & 7) == 0)
fprintf(stderr, "g%d: ",
prog_data->dispatch_grf_start_reg + i / 8);
fprintf(stderr, "%8f ", param[i]);
if ((i & 7) == 7)
fprintf(stderr, "\n");
}
if ((i & 7) != 0)
fprintf(stderr, "\n");
fprintf(stderr, "\n");
}
stage_state->push_const_size = (params_uploaded + 1) / 2;
stage_state->push_const_size = ALIGN(prog_data->nr_params, 8) / 8;
/* We can only push 32 registers of constants at a time. */
assert(stage_state->push_const_size <= 32);
}
@@ -94,10 +115,10 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
const struct brw_vertex_program *vp =
brw_vertex_program_const(brw->vertex_program);
/* CACHE_NEW_VS_PROG */
const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base;
gen6_upload_vec4_push_constants(brw, &vp->program.Base, prog_data,
stage_state, AUB_TRACE_VS_CONSTANTS);
gen6_upload_push_constants(brw, &vp->program.Base, prog_data,
stage_state, AUB_TRACE_VS_CONSTANTS);
if (brw->gen >= 7) {
if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail)
src/mesa/drivers/dri/i965/gen6_wm_state.c
+3 -38
View File
@@ -38,50 +38,15 @@
static void
gen6_upload_wm_push_constants(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
struct brw_stage_state *stage_state = &brw->wm.base;
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
/* CACHE_NEW_WM_PROG */
const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
/* Updates the ParameterValues[i] pointers for all parameters of the
* basic type of PROGRAM_STATE_VAR.
*/
/* XXX: Should this happen somewhere before to get our state flag set? */
_mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
if (prog_data->base.nr_params == 0) {
brw->wm.base.push_const_size = 0;
} else {
float *constants;
unsigned int i;
constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
prog_data->base.nr_params * sizeof(float),
32, &brw->wm.base.push_const_offset);
for (i = 0; i < prog_data->base.nr_params; i++) {
constants[i] = *prog_data->base.param[i];
}
if (0) {
fprintf(stderr, "WM constants:\n");
for (i = 0; i < prog_data->base.nr_params; i++) {
if ((i & 7) == 0)
fprintf(stderr, "g%d: ",
prog_data->base.dispatch_grf_start_reg + i / 8);
fprintf(stderr, "%8f ", constants[i]);
if ((i & 7) == 7)
fprintf(stderr, "\n");
}
if ((i & 7) != 0)
fprintf(stderr, "\n");
fprintf(stderr, "\n");
}
brw->wm.base.push_const_size = ALIGN(prog_data->base.nr_params, 8) / 8;
}
gen6_upload_push_constants(brw, &fp->program.Base, &prog_data->base,
stage_state, AUB_TRACE_WM_CONSTANTS);
if (brw->gen >= 7) {
gen7_upload_constant_state(brw, &brw->wm.base, true,
src/mesa/drivers/dri/i965/gen7_gs_state.c
+3 -3
View File
@@ -37,11 +37,11 @@ gen7_upload_gs_push_constants(struct brw_context *brw)
if (gp) {
/* CACHE_NEW_GS_PROG */
const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
const struct brw_stage_prog_data *prog_data = &brw->gs.prog_data->base.base;
struct brw_stage_state *stage_state = &brw->gs.base;
gen6_upload_vec4_push_constants(brw, &gp->program.Base, prog_data,
stage_state, AUB_TRACE_VS_CONSTANTS);
gen6_upload_push_constants(brw, &gp->program.Base, prog_data,
stage_state, AUB_TRACE_VS_CONSTANTS);
}
gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);