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i965: Move dispatch_grf_start_reg and first_curbe_grf into stage_prog_data.

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I wanted to access this value from stage-generic code, so stop storing it
under two different names.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt
2014-05-19 10:10:01 -07:00
committed by Kenneth Graunke
parent 5ba31c34d8
commit c0f1929dd2
14 changed files with 36 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_context.h
+7 -8
View File
@@ -297,6 +297,12 @@ struct brw_stage_prog_data {
GLuint nr_params; /**< number of float params/constants */
GLuint nr_pull_params;
/**
* Register where the thread expects to find input data from the URB
* (typically uniforms, followed by vertex or fragment attributes).
*/
unsigned dispatch_grf_start_reg;
/* Pointers to tracked values (only valid once
* _mesa_load_state_parameters has been called at runtime).
*
@@ -321,8 +327,7 @@ struct brw_wm_prog_data {
GLuint curb_read_length;
GLuint num_varying_inputs;
GLuint first_curbe_grf;
GLuint first_curbe_grf_16;
GLuint dispatch_grf_start_reg_16;
GLuint reg_blocks;
GLuint reg_blocks_16;
GLuint total_scratch;
@@ -524,12 +529,6 @@ struct brw_vec4_prog_data {
struct brw_stage_prog_data base;
struct brw_vue_map vue_map;
/**
* Register where the thread expects to find input data from the URB
* (typically uniforms, followed by per-vertex inputs).
*/
unsigned dispatch_grf_start_reg;
GLuint curb_read_length;
GLuint urb_read_length;
GLuint total_grf;
src/mesa/drivers/dri/i965/brw_fs.cpp
+2 -2
View File
@@ -1465,9 +1465,9 @@ void
fs_visitor::assign_curb_setup()
{
if (dispatch_width == 8) {
prog_data->first_curbe_grf = payload.num_regs;
prog_data->base.dispatch_grf_start_reg = payload.num_regs;
} else {
prog_data->first_curbe_grf_16 = payload.num_regs;
prog_data->dispatch_grf_start_reg_16 = payload.num_regs;
}
prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8;
src/mesa/drivers/dri/i965/brw_vec4.cpp
+2 -2
View File
@@ -1529,7 +1529,7 @@ vec4_vs_visitor::setup_attributes(int payload_reg)
int
vec4_visitor::setup_uniforms(int reg)
{
prog_data->dispatch_grf_start_reg = reg;
prog_data->base.dispatch_grf_start_reg = reg;
/* The pre-gen6 VS requires that some push constants get loaded no
* matter what, or the GPU would hang.
@@ -1554,7 +1554,7 @@ vec4_visitor::setup_uniforms(int reg)
stage_prog_data->nr_params = this->uniforms * 4;
prog_data->curb_read_length = reg - prog_data->dispatch_grf_start_reg;
prog_data->curb_read_length = reg - prog_data->base.dispatch_grf_start_reg;
return reg;
}
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+1 -1
View File
@@ -98,7 +98,7 @@ vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
break;
case UNIFORM:
brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
(src[i].reg + src[i].reg_offset) / 2,
((src[i].reg + src[i].reg_offset) % 2) * 4),
0, 4, 1);
src/mesa/drivers/dri/i965/brw_vs_state.c
+1 -1
View File
@@ -96,7 +96,7 @@ brw_upload_vs_unit(struct brw_context *brw)
vs->thread3.const_urb_entry_read_length
= brw->vs.prog_data->base.curb_read_length;
vs->thread3.dispatch_grf_start_reg =
brw->vs.prog_data->base.dispatch_grf_start_reg;
brw->vs.prog_data->base.base.dispatch_grf_start_reg;
vs->thread3.urb_entry_read_offset = 0;
/* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */
src/mesa/drivers/dri/i965/brw_wm_state.c
+4 -3
View File
@@ -87,8 +87,8 @@ brw_upload_wm_unit(struct brw_context *brw)
* only have one hardware field to program for both dispatch
* widths.
*/
assert(brw->wm.prog_data->first_curbe_grf ==
brw->wm.prog_data->first_curbe_grf_16);
assert(brw->wm.prog_data->base.dispatch_grf_start_reg ==
brw->wm.prog_data->dispatch_grf_start_reg_16);
}
/* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
@@ -134,7 +134,8 @@ brw_upload_wm_unit(struct brw_context *brw)
wm->thread2.per_thread_scratch_space = 0;
}
wm->thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
wm->thread3.dispatch_grf_start_reg =
brw->wm.prog_data->base.dispatch_grf_start_reg;
wm->thread3.urb_entry_read_length =
brw->wm.prog_data->num_varying_inputs * 2;
wm->thread3.urb_entry_read_offset = 0;
src/mesa/drivers/dri/i965/gen6_vs_state.c
+1 -1
View File
@@ -186,7 +186,7 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(0);
}
OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
src/mesa/drivers/dri/i965/gen6_wm_state.c
+6 -5
View File
@@ -69,7 +69,8 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
fprintf(stderr, "WM constants:\n");
for (i = 0; i < prog_data->base.nr_params; i++) {
if ((i & 7) == 0)
fprintf(stderr, "g%d: ", prog_data->first_curbe_grf + i / 8);
fprintf(stderr, "g%d: ",
prog_data->base.dispatch_grf_start_reg + i / 8);
fprintf(stderr, "%8f ", constants[i]);
if ((i & 7) == 7)
fprintf(stderr, "\n");
@@ -174,17 +175,17 @@ upload_wm_state(struct brw_context *brw)
if (min_inv_per_frag == 1) {
dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
dw4 |= (brw->wm.prog_data->first_curbe_grf <<
dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
} else
dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
}
else {
dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
dw4 |= (brw->wm.prog_data->first_curbe_grf <<
dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
}
src/mesa/drivers/dri/i965/gen7_gs_state.c
+1 -1
View File
@@ -110,7 +110,7 @@ upload_gs_state(struct brw_context *brw)
(prog_data->urb_read_length <<
GEN6_GS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
(prog_data->dispatch_grf_start_reg <<
(prog_data->base.dispatch_grf_start_reg <<
GEN6_GS_DISPATCH_START_GRF_SHIFT);
/* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
src/mesa/drivers/dri/i965/gen7_vs_state.c
+1 -1
View File
@@ -98,7 +98,7 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(0);
}
OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
src/mesa/drivers/dri/i965/gen7_wm_state.c
+4 -4
View File
@@ -227,17 +227,17 @@ upload_ps_state(struct brw_context *brw)
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
if (min_inv_per_frag == 1) {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
dw5 |= (brw->wm.prog_data->first_curbe_grf <<
dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
} else
dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
}
else {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
dw5 |= (brw->wm.prog_data->first_curbe_grf <<
dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
}
src/mesa/drivers/dri/i965/gen8_gs_state.c
+1 -1
View File
@@ -76,7 +76,7 @@ gen8_upload_gs_state(struct brw_context *brw)
(prog_data->urb_read_length <<
GEN6_GS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
(prog_data->dispatch_grf_start_reg <<
(prog_data->base.dispatch_grf_start_reg <<
GEN6_GS_DISPATCH_START_GRF_SHIFT));
/* DW7 */
src/mesa/drivers/dri/i965/gen8_ps_state.c
+4 -4
View File
@@ -199,17 +199,17 @@ upload_ps_state(struct brw_context *brw)
dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
if (min_invocations_per_fragment == 1) {
dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
dw7 |= (brw->wm.prog_data->first_curbe_grf <<
dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
dw7 |= (brw->wm.prog_data->first_curbe_grf_16 <<
dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
} else {
dw7 |= (brw->wm.prog_data->first_curbe_grf_16 <<
dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
}
} else {
dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
dw7 |= (brw->wm.prog_data->first_curbe_grf <<
dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
}
src/mesa/drivers/dri/i965/gen8_vs_state.c
+1 -1
View File
@@ -64,7 +64,7 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(0);
}
OUT_BATCH((prog_data->dispatch_grf_start_reg <<
OUT_BATCH((prog_data->base.dispatch_grf_start_reg <<
GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));