nir/lower_wrmasks: drop callback

All drivers use the same callback and it is unlikely that new drivers will use
this pass since it has better replacements today (lower_mem_bit_sizes for
memory, and it never worked for I/O). This should discourage as much.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38533>
This commit is contained in:
Alyssa Rosenzweig
2025-11-19 10:39:50 -05:00
committed by Marge Bot
parent 5515160b55
commit 2c2dd835af
5 changed files with 9 additions and 83 deletions
+1 -16
View File
@@ -1399,21 +1399,6 @@ v3d_instr_delay_cb(nir_instr *instr, void *data)
return 0;
}
static bool
should_split_wrmask(const nir_instr *instr, const void *data)
{
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
switch (intr->intrinsic) {
case nir_intrinsic_store_ssbo:
case nir_intrinsic_store_shared:
case nir_intrinsic_store_global:
case nir_intrinsic_store_scratch:
return true;
default:
return false;
}
}
static nir_intrinsic_instr *
nir_instr_as_constant_ubo_load(nir_instr *inst)
{
@@ -1857,7 +1842,7 @@ v3d_attempt_compile(struct v3d_compile *c)
glsl_get_natural_size_align_bytes);
NIR_PASS(_, c->s, v3d_nir_lower_global_2x32);
NIR_PASS(_, c->s, nir_lower_wrmasks, should_split_wrmask, c->s);
NIR_PASS(_, c->s, nir_lower_wrmasks);
NIR_PASS(_, c->s, v3d_nir_lower_load_store_bitsize);
NIR_PASS(_, c->s, v3d_nir_lower_scratch);
+1 -1
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@@ -6092,7 +6092,7 @@ bool nir_lower_wpos_center(nir_shader *shader);
bool nir_lower_pntc_ytransform(nir_shader *shader,
const gl_state_index16 clipplane_state_tokens[][STATE_LENGTH]);
bool nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data);
bool nir_lower_wrmasks(nir_shader *shader);
bool nir_lower_fb_read(nir_shader *shader);
+4 -27
View File
@@ -165,21 +165,9 @@ split_wrmask(nir_builder *b, nir_intrinsic_instr *intr)
nir_instr_remove(&intr->instr);
}
struct nir_lower_wrmasks_state {
nir_instr_filter_cb cb;
const void *data;
};
static bool
nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data)
lower(nir_builder *b, nir_intrinsic_instr *intr, void *data)
{
struct nir_lower_wrmasks_state *state = data;
if (instr->type != nir_instr_type_intrinsic)
return false;
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
/* if no wrmask, then skip it: */
if (!nir_intrinsic_has_write_mask(intr))
return false;
@@ -194,25 +182,14 @@ nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data)
assert(offset_src(intr->intrinsic) >= 0);
/* does backend need us to lower this intrinsic? */
if (state->cb && !state->cb(instr, state->data))
return false;
split_wrmask(b, intr);
return true;
}
bool
nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data)
nir_lower_wrmasks(nir_shader *shader)
{
struct nir_lower_wrmasks_state state = {
.cb = cb,
.data = data,
};
return nir_shader_instructions_pass(shader,
nir_lower_wrmasks_instr,
nir_metadata_control_flow,
&state);
return nir_shader_intrinsics_pass(shader, lower, nir_metadata_control_flow,
NULL);
}
+2 -18
View File
@@ -426,22 +426,6 @@ ir3_optimize_loop(struct ir3_compiler *compiler,
return did_progress;
}
static bool
should_split_wrmask(const nir_instr *instr, const void *data)
{
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
switch (intr->intrinsic) {
case nir_intrinsic_store_ssbo:
case nir_intrinsic_store_shared:
case nir_intrinsic_store_global:
case nir_intrinsic_store_scratch:
return true;
default:
return false;
}
}
static bool
ir3_nir_lower_ssbo_size_filter(const nir_instr *instr, const void *data)
{
@@ -705,7 +689,7 @@ ir3_finalize_nir(struct ir3_compiler *compiler,
NIR_PASS(_, s, nir_lower_frexp);
NIR_PASS(_, s, nir_lower_amul, ir3_glsl_type_size);
OPT(s, nir_lower_wrmasks, should_split_wrmask, s);
OPT(s, nir_lower_wrmasks);
OPT(s, nir_lower_tex, &tex_options);
OPT(s, nir_lower_load_const_to_scalar);
@@ -1223,7 +1207,7 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so,
}
/* Lower scratch writemasks */
progress |= OPT(s, nir_lower_wrmasks, should_split_wrmask, s);
progress |= OPT(s, nir_lower_wrmasks);
progress |= OPT(s, nir_lower_atomics, atomic_supported);
if (OPT(s, nir_lower_locals_to_regs, 1)) {
+1 -21
View File
@@ -5413,26 +5413,6 @@ va_gather_stats(bi_context *ctx, unsigned size, struct valhall_stats *out)
MAX3(stats.v, stats.t, stats.ls));
}
/* Split stores to memory. We don't split stores to vertex outputs, since
* nir_lower_io_vars_to_temporaries will ensure there's only a single write.
*/
static bool
should_split_wrmask(const nir_instr *instr, UNUSED const void *data)
{
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
switch (intr->intrinsic) {
case nir_intrinsic_store_ssbo:
case nir_intrinsic_store_shared:
case nir_intrinsic_store_global:
case nir_intrinsic_store_scratch:
return true;
default:
return false;
}
}
/*
* Some operations are only available as 32-bit instructions. 64-bit floats are
* unsupported and ints are lowered with nir_lower_int64. Certain 8-bit and
@@ -5704,7 +5684,7 @@ bi_optimize_loop_nir(nir_shader *nir, unsigned gpu_id, bool allow_copies)
NIR_PASS(progress, nir, nir_opt_deref);
NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
NIR_PASS(progress, nir, nir_lower_wrmasks, should_split_wrmask, NULL);
NIR_PASS(progress, nir, nir_lower_wrmasks);
if (allow_copies) {
/* Only run this pass in the first call to bi_optimize_nir. Later