nir/lower_wrmasks: drop callback
All drivers use the same callback and it is unlikely that new drivers will use this pass since it has better replacements today (lower_mem_bit_sizes for memory, and it never worked for I/O). This should discourage as much. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Marek Olšák <maraeo@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38533>
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@@ -1399,21 +1399,6 @@ v3d_instr_delay_cb(nir_instr *instr, void *data)
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return 0;
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}
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static bool
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should_split_wrmask(const nir_instr *instr, const void *data)
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{
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_scratch:
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return true;
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default:
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return false;
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}
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}
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static nir_intrinsic_instr *
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nir_instr_as_constant_ubo_load(nir_instr *inst)
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{
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@@ -1857,7 +1842,7 @@ v3d_attempt_compile(struct v3d_compile *c)
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glsl_get_natural_size_align_bytes);
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NIR_PASS(_, c->s, v3d_nir_lower_global_2x32);
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NIR_PASS(_, c->s, nir_lower_wrmasks, should_split_wrmask, c->s);
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NIR_PASS(_, c->s, nir_lower_wrmasks);
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NIR_PASS(_, c->s, v3d_nir_lower_load_store_bitsize);
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NIR_PASS(_, c->s, v3d_nir_lower_scratch);
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@@ -6092,7 +6092,7 @@ bool nir_lower_wpos_center(nir_shader *shader);
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bool nir_lower_pntc_ytransform(nir_shader *shader,
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const gl_state_index16 clipplane_state_tokens[][STATE_LENGTH]);
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bool nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data);
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bool nir_lower_wrmasks(nir_shader *shader);
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bool nir_lower_fb_read(nir_shader *shader);
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@@ -165,21 +165,9 @@ split_wrmask(nir_builder *b, nir_intrinsic_instr *intr)
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nir_instr_remove(&intr->instr);
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}
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struct nir_lower_wrmasks_state {
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nir_instr_filter_cb cb;
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const void *data;
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};
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static bool
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nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data)
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lower(nir_builder *b, nir_intrinsic_instr *intr, void *data)
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{
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struct nir_lower_wrmasks_state *state = data;
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* if no wrmask, then skip it: */
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if (!nir_intrinsic_has_write_mask(intr))
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return false;
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@@ -194,25 +182,14 @@ nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data)
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assert(offset_src(intr->intrinsic) >= 0);
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/* does backend need us to lower this intrinsic? */
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if (state->cb && !state->cb(instr, state->data))
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return false;
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split_wrmask(b, intr);
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return true;
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}
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bool
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nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data)
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nir_lower_wrmasks(nir_shader *shader)
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{
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struct nir_lower_wrmasks_state state = {
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.cb = cb,
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.data = data,
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};
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return nir_shader_instructions_pass(shader,
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nir_lower_wrmasks_instr,
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nir_metadata_control_flow,
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&state);
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return nir_shader_intrinsics_pass(shader, lower, nir_metadata_control_flow,
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NULL);
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}
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@@ -426,22 +426,6 @@ ir3_optimize_loop(struct ir3_compiler *compiler,
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return did_progress;
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}
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static bool
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should_split_wrmask(const nir_instr *instr, const void *data)
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{
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_scratch:
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return true;
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default:
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return false;
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}
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}
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static bool
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ir3_nir_lower_ssbo_size_filter(const nir_instr *instr, const void *data)
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{
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@@ -705,7 +689,7 @@ ir3_finalize_nir(struct ir3_compiler *compiler,
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NIR_PASS(_, s, nir_lower_frexp);
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NIR_PASS(_, s, nir_lower_amul, ir3_glsl_type_size);
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OPT(s, nir_lower_wrmasks, should_split_wrmask, s);
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OPT(s, nir_lower_wrmasks);
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OPT(s, nir_lower_tex, &tex_options);
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OPT(s, nir_lower_load_const_to_scalar);
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@@ -1223,7 +1207,7 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so,
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}
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/* Lower scratch writemasks */
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progress |= OPT(s, nir_lower_wrmasks, should_split_wrmask, s);
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progress |= OPT(s, nir_lower_wrmasks);
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progress |= OPT(s, nir_lower_atomics, atomic_supported);
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if (OPT(s, nir_lower_locals_to_regs, 1)) {
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@@ -5413,26 +5413,6 @@ va_gather_stats(bi_context *ctx, unsigned size, struct valhall_stats *out)
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MAX3(stats.v, stats.t, stats.ls));
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}
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/* Split stores to memory. We don't split stores to vertex outputs, since
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* nir_lower_io_vars_to_temporaries will ensure there's only a single write.
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*/
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static bool
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should_split_wrmask(const nir_instr *instr, UNUSED const void *data)
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{
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_scratch:
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return true;
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default:
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return false;
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}
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}
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/*
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* Some operations are only available as 32-bit instructions. 64-bit floats are
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* unsupported and ints are lowered with nir_lower_int64. Certain 8-bit and
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@@ -5704,7 +5684,7 @@ bi_optimize_loop_nir(nir_shader *nir, unsigned gpu_id, bool allow_copies)
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NIR_PASS(progress, nir, nir_opt_deref);
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NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
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NIR_PASS(progress, nir, nir_lower_wrmasks, should_split_wrmask, NULL);
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NIR_PASS(progress, nir, nir_lower_wrmasks);
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if (allow_copies) {
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/* Only run this pass in the first call to bi_optimize_nir. Later
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