From 2c2dd835af47ece48b8fab0bce78cbcbda3a9216 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 19 Nov 2025 10:39:50 -0500 Subject: [PATCH] nir/lower_wrmasks: drop callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All drivers use the same callback and it is unlikely that new drivers will use this pass since it has better replacements today (lower_mem_bit_sizes for memory, and it never worked for I/O). This should discourage as much. Signed-off-by: Alyssa Rosenzweig Reviewed-by: Kenneth Graunke Reviewed-by: Marek Olšák Part-of: --- src/broadcom/compiler/vir.c | 17 +------------- src/compiler/nir/nir.h | 2 +- src/compiler/nir/nir_lower_wrmasks.c | 31 ++++--------------------- src/freedreno/ir3/ir3_nir.c | 20 ++-------------- src/panfrost/compiler/bifrost_compile.c | 22 +----------------- 5 files changed, 9 insertions(+), 83 deletions(-) diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c index b7209aa34c4..d0147986220 100644 --- a/src/broadcom/compiler/vir.c +++ b/src/broadcom/compiler/vir.c @@ -1399,21 +1399,6 @@ v3d_instr_delay_cb(nir_instr *instr, void *data) return 0; } -static bool -should_split_wrmask(const nir_instr *instr, const void *data) -{ - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - switch (intr->intrinsic) { - case nir_intrinsic_store_ssbo: - case nir_intrinsic_store_shared: - case nir_intrinsic_store_global: - case nir_intrinsic_store_scratch: - return true; - default: - return false; - } -} - static nir_intrinsic_instr * nir_instr_as_constant_ubo_load(nir_instr *inst) { @@ -1857,7 +1842,7 @@ v3d_attempt_compile(struct v3d_compile *c) glsl_get_natural_size_align_bytes); NIR_PASS(_, c->s, v3d_nir_lower_global_2x32); - NIR_PASS(_, c->s, nir_lower_wrmasks, should_split_wrmask, c->s); + NIR_PASS(_, c->s, nir_lower_wrmasks); NIR_PASS(_, c->s, v3d_nir_lower_load_store_bitsize); NIR_PASS(_, c->s, v3d_nir_lower_scratch); diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 075dbb06344..c9b4abb97a8 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -6092,7 +6092,7 @@ bool nir_lower_wpos_center(nir_shader *shader); bool nir_lower_pntc_ytransform(nir_shader *shader, const gl_state_index16 clipplane_state_tokens[][STATE_LENGTH]); -bool nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data); +bool nir_lower_wrmasks(nir_shader *shader); bool nir_lower_fb_read(nir_shader *shader); diff --git a/src/compiler/nir/nir_lower_wrmasks.c b/src/compiler/nir/nir_lower_wrmasks.c index 78071d3fd76..9ac063fec4a 100644 --- a/src/compiler/nir/nir_lower_wrmasks.c +++ b/src/compiler/nir/nir_lower_wrmasks.c @@ -165,21 +165,9 @@ split_wrmask(nir_builder *b, nir_intrinsic_instr *intr) nir_instr_remove(&intr->instr); } -struct nir_lower_wrmasks_state { - nir_instr_filter_cb cb; - const void *data; -}; - static bool -nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data) +lower(nir_builder *b, nir_intrinsic_instr *intr, void *data) { - struct nir_lower_wrmasks_state *state = data; - - if (instr->type != nir_instr_type_intrinsic) - return false; - - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - /* if no wrmask, then skip it: */ if (!nir_intrinsic_has_write_mask(intr)) return false; @@ -194,25 +182,14 @@ nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data) assert(offset_src(intr->intrinsic) >= 0); - /* does backend need us to lower this intrinsic? */ - if (state->cb && !state->cb(instr, state->data)) - return false; - split_wrmask(b, intr); return true; } bool -nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data) +nir_lower_wrmasks(nir_shader *shader) { - struct nir_lower_wrmasks_state state = { - .cb = cb, - .data = data, - }; - - return nir_shader_instructions_pass(shader, - nir_lower_wrmasks_instr, - nir_metadata_control_flow, - &state); + return nir_shader_intrinsics_pass(shader, lower, nir_metadata_control_flow, + NULL); } diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index b71b18f5f23..720bfef403e 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -426,22 +426,6 @@ ir3_optimize_loop(struct ir3_compiler *compiler, return did_progress; } -static bool -should_split_wrmask(const nir_instr *instr, const void *data) -{ - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - - switch (intr->intrinsic) { - case nir_intrinsic_store_ssbo: - case nir_intrinsic_store_shared: - case nir_intrinsic_store_global: - case nir_intrinsic_store_scratch: - return true; - default: - return false; - } -} - static bool ir3_nir_lower_ssbo_size_filter(const nir_instr *instr, const void *data) { @@ -705,7 +689,7 @@ ir3_finalize_nir(struct ir3_compiler *compiler, NIR_PASS(_, s, nir_lower_frexp); NIR_PASS(_, s, nir_lower_amul, ir3_glsl_type_size); - OPT(s, nir_lower_wrmasks, should_split_wrmask, s); + OPT(s, nir_lower_wrmasks); OPT(s, nir_lower_tex, &tex_options); OPT(s, nir_lower_load_const_to_scalar); @@ -1223,7 +1207,7 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, } /* Lower scratch writemasks */ - progress |= OPT(s, nir_lower_wrmasks, should_split_wrmask, s); + progress |= OPT(s, nir_lower_wrmasks); progress |= OPT(s, nir_lower_atomics, atomic_supported); if (OPT(s, nir_lower_locals_to_regs, 1)) { diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index 4065a2933ba..bfb6f52632a 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -5413,26 +5413,6 @@ va_gather_stats(bi_context *ctx, unsigned size, struct valhall_stats *out) MAX3(stats.v, stats.t, stats.ls)); } -/* Split stores to memory. We don't split stores to vertex outputs, since - * nir_lower_io_vars_to_temporaries will ensure there's only a single write. - */ - -static bool -should_split_wrmask(const nir_instr *instr, UNUSED const void *data) -{ - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - - switch (intr->intrinsic) { - case nir_intrinsic_store_ssbo: - case nir_intrinsic_store_shared: - case nir_intrinsic_store_global: - case nir_intrinsic_store_scratch: - return true; - default: - return false; - } -} - /* * Some operations are only available as 32-bit instructions. 64-bit floats are * unsupported and ints are lowered with nir_lower_int64. Certain 8-bit and @@ -5704,7 +5684,7 @@ bi_optimize_loop_nir(nir_shader *nir, unsigned gpu_id, bool allow_copies) NIR_PASS(progress, nir, nir_opt_deref); NIR_PASS(progress, nir, nir_lower_vars_to_ssa); - NIR_PASS(progress, nir, nir_lower_wrmasks, should_split_wrmask, NULL); + NIR_PASS(progress, nir, nir_lower_wrmasks); if (allow_copies) { /* Only run this pass in the first call to bi_optimize_nir. Later