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i965: Pass flags to brw_bo_map_*

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brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear
whether we were also planning to read from the buffer. I kept everything
semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE
depending on the write_enable argument.

The other flags are not used yet, but MAP_ASYNC for instance, will be
used in a later patch to remove the need for a separate
brw_bo_map_unsynchronized() function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner
2017-05-18 10:59:23 -07:00
parent 925a4222f2
commit 275401d32b
16 changed files with 49 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_bufmgr.c
+4 -4
View File
@@ -659,7 +659,7 @@ set_domain(struct brw_context *brw, const char *action,
}
void *
brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, int write_enable)
brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, unsigned flags)
{
struct brw_bufmgr *bufmgr = bo->bufmgr;
@@ -690,7 +690,7 @@ brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, int write_enable)
bo->map_cpu);
set_domain(brw, "CPU mapping", bo, I915_GEM_DOMAIN_CPU,
write_enable ? I915_GEM_DOMAIN_CPU : 0);
flags & MAP_WRITE ? I915_GEM_DOMAIN_CPU : 0);
bo_mark_mmaps_incoherent(bo);
VG(VALGRIND_MAKE_MEM_DEFINED(bo->map_cpu, bo->size));
@@ -741,7 +741,7 @@ map_gtt(struct brw_bo *bo)
}
void *
brw_bo_map_gtt(struct brw_context *brw, struct brw_bo *bo)
brw_bo_map_gtt(struct brw_context *brw, struct brw_bo *bo, unsigned flags)
{
struct brw_bufmgr *bufmgr = bo->bufmgr;
@@ -799,7 +799,7 @@ brw_bo_map_unsynchronized(struct brw_context *brw, struct brw_bo *bo)
* does reasonable things.
*/
if (!bufmgr->has_llc)
return brw_bo_map_gtt(brw, bo);
return brw_bo_map_gtt(brw, bo, MAP_READ | MAP_WRITE);
pthread_mutex_lock(&bufmgr->lock);
src/mesa/drivers/dri/i965/brw_bufmgr.h
+12 -2
View File
@@ -173,13 +173,23 @@ void brw_bo_reference(struct brw_bo *bo);
*/
void brw_bo_unreference(struct brw_bo *bo);
/* Must match MapBufferRange interface (for convenience) */
#define MAP_READ GL_MAP_READ_BIT
#define MAP_WRITE GL_MAP_WRITE_BIT
#define MAP_ASYNC GL_MAP_UNSYNCHRONIZED_BIT
#define MAP_PERSISTENT GL_MAP_PERSISTENT_BIT
#define MAP_COHERENT GL_MAP_COHERENT_BIT
/* internal */
#define MAP_INTERNAL_MASK (0xff << 24)
#define MAP_RAW (0x01 << 24)
/**
* Maps the buffer into userspace.
*
* This function will block waiting for any existing execution on the
* buffer to complete, first. The resulting mapping is returned.
*/
MUST_CHECK void *brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, int write_enable);
MUST_CHECK void *brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, unsigned flags);
/**
* Reduces the refcount on the userspace mapping of the buffer
@@ -253,7 +263,7 @@ struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
unsigned int handle);
void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr);
MUST_CHECK void *brw_bo_map_unsynchronized(struct brw_context *brw, struct brw_bo *bo);
MUST_CHECK void *brw_bo_map_gtt(struct brw_context *brw, struct brw_bo *bo);
MUST_CHECK void *brw_bo_map_gtt(struct brw_context *brw, struct brw_bo *bo, unsigned flags);
int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns);
src/mesa/drivers/dri/i965/brw_performance_query.c
+3 -3
View File
@@ -713,7 +713,7 @@ accumulate_oa_reports(struct brw_context *brw,
if (!read_oa_samples(brw))
goto error;
query_buffer = brw_bo_map_cpu(brw, obj->oa.bo, false);
query_buffer = brw_bo_map_cpu(brw, obj->oa.bo, MAP_READ);
start = last = query_buffer;
end = query_buffer + (MI_RPC_BO_END_OFFSET_BYTES / sizeof(uint32_t));
@@ -992,7 +992,7 @@ brw_begin_perf_query(struct gl_context *ctx,
MI_RPC_BO_SIZE, 64);
#ifdef DEBUG
/* Pre-filling the BO helps debug whether writes landed. */
void *map = brw_bo_map_cpu(brw, obj->oa.bo, true);
void *map = brw_bo_map_cpu(brw, obj->oa.bo, MAP_READ | MAP_WRITE);
memset(map, 0x80, MI_RPC_BO_SIZE);
brw_bo_unmap(obj->oa.bo);
#endif
@@ -1214,7 +1214,7 @@ get_pipeline_stats_data(struct brw_context *brw,
int n_counters = obj->query->n_counters;
uint8_t *p = data;
uint64_t *start = brw_bo_map_cpu(brw, obj->pipeline_stats.bo, false);
uint64_t *start = brw_bo_map_cpu(brw, obj->pipeline_stats.bo, MAP_READ);
uint64_t *end = start + (STATS_BO_END_OFFSET_BYTES / sizeof(uint64_t));
for (int i = 0; i < n_counters; i++) {
src/mesa/drivers/dri/i965/brw_program.c
+1 -1
View File
@@ -578,7 +578,7 @@ brw_collect_shader_time(struct brw_context *brw)
* delaying reading the reports, but it doesn't look like it's a big
* overhead compared to the cost of tracking the time in the first place.
*/
void *bo_map = brw_bo_map_cpu(brw, brw->shader_time.bo, true);
void *bo_map = brw_bo_map_cpu(brw, brw->shader_time.bo, MAP_READ | MAP_WRITE);
for (int i = 0; i < brw->shader_time.num_entries; i++) {
uint32_t *times = bo_map + i * 3 * BRW_SHADER_TIME_STRIDE;
src/mesa/drivers/dri/i965/brw_program_cache.c
+3 -3
View File
@@ -227,7 +227,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
if (brw->has_llc) {
memcpy(llc_map, cache->map, cache->next_offset);
} else {
void *map = brw_bo_map_cpu(brw, cache->bo, false);
void *map = brw_bo_map_cpu(brw, cache->bo, MAP_READ);
brw_bo_subdata(new_bo, 0, cache->next_offset, map);
brw_bo_unmap(cache->bo);
}
@@ -268,7 +268,7 @@ brw_lookup_prog(const struct brw_cache *cache,
void *map;
if (!brw->has_llc)
map = brw_bo_map_cpu(brw, cache->bo, false);
map = brw_bo_map_cpu(brw, cache->bo, MAP_READ);
else
map = cache->map;
@@ -550,7 +550,7 @@ brw_print_program_cache(struct brw_context *brw)
void *map;
if (!brw->has_llc)
map = brw_bo_map_cpu(brw, cache->bo, false);
map = brw_bo_map_cpu(brw, cache->bo, MAP_READ);
else
map = cache->map;
src/mesa/drivers/dri/i965/brw_queryobj.c
+1 -1
View File
@@ -146,7 +146,7 @@ brw_queryobj_get_results(struct gl_context *ctx,
}
}
results = brw_bo_map_cpu(brw, query->bo, false);
results = brw_bo_map_cpu(brw, query->bo, MAP_READ);
switch (query->Base.Target) {
case GL_TIME_ELAPSED_EXT:
/* The query BO contains the starting and ending timestamps.
src/mesa/drivers/dri/i965/gen6_queryobj.c
+1 -1
View File
@@ -221,7 +221,7 @@ gen6_queryobj_get_results(struct gl_context *ctx,
if (query->bo == NULL)
return;
uint64_t *results = brw_bo_map_cpu(brw, query->bo, false);
uint64_t *results = brw_bo_map_cpu(brw, query->bo, MAP_READ);
switch (query->Base.Target) {
case GL_TIME_ELAPSED:
/* The query BO contains the starting and ending timestamps.
src/mesa/drivers/dri/i965/gen6_sol.c
+1 -1
View File
@@ -247,7 +247,7 @@ tally_prims_generated(struct brw_context *brw,
if (unlikely(brw->perf_debug && brw_bo_busy(obj->prim_count_bo)))
perf_debug("Stalling for # of transform feedback primitives written.\n");
uint64_t *prim_counts = brw_bo_map_cpu(brw, obj->prim_count_bo, false);
uint64_t *prim_counts = brw_bo_map_cpu(brw, obj->prim_count_bo, MAP_READ);
assert(obj->prim_count_buffer_index % (2 * streams) == 0);
int pairs = obj->prim_count_buffer_index / (2 * streams);
src/mesa/drivers/dri/i965/intel_batchbuffer.c
+2 -2
View File
@@ -100,7 +100,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch,
batch->bo = brw_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
if (has_llc) {
batch->map = brw_bo_map_cpu(NULL, batch->bo, true);
batch->map = brw_bo_map_cpu(NULL, batch->bo, MAP_READ | MAP_WRITE);
}
batch->map_next = batch->map;
@@ -239,7 +239,7 @@ do_batch_dump(struct brw_context *brw)
if (batch->ring != RENDER_RING)
return;
void *map = brw_bo_map_cpu(brw, batch->bo, false);
void *map = brw_bo_map_cpu(brw, batch->bo, MAP_READ);
if (map == NULL) {
fprintf(stderr,
"WARNING: failed to map batchbuffer, "
src/mesa/drivers/dri/i965/intel_buffer_objects.c
+11 -5
View File
@@ -328,6 +328,13 @@ brw_map_buffer_range(struct gl_context *ctx,
assert(intel_obj);
STATIC_ASSERT(GL_MAP_UNSYNCHRONIZED_BIT == MAP_ASYNC);
STATIC_ASSERT(GL_MAP_WRITE_BIT == MAP_WRITE);
STATIC_ASSERT(GL_MAP_READ_BIT == MAP_READ);
STATIC_ASSERT(GL_MAP_PERSISTENT_BIT == MAP_PERSISTENT);
STATIC_ASSERT(GL_MAP_COHERENT_BIT == MAP_COHERENT);
assert((access & MAP_INTERNAL_MASK) == 0);
/* _mesa_MapBufferRange (GL entrypoint) sets these, but the vbo module also
* internally uses our functions directly.
*/
@@ -390,10 +397,9 @@ brw_map_buffer_range(struct gl_context *ctx,
alignment);
void *map;
if (brw->has_llc) {
map = brw_bo_map_cpu(brw, intel_obj->range_map_bo[index],
(access & GL_MAP_WRITE_BIT) != 0);
map = brw_bo_map_cpu(brw, intel_obj->range_map_bo[index], access);
} else {
map = brw_bo_map_gtt(brw, intel_obj->range_map_bo[index]);
map = brw_bo_map_gtt(brw, intel_obj->range_map_bo[index], access);
}
obj->Mappings[index].Pointer = map + intel_obj->map_extra[index];
return obj->Mappings[index].Pointer;
@@ -408,10 +414,10 @@ brw_map_buffer_range(struct gl_context *ctx,
map = brw_bo_map_unsynchronized(brw, intel_obj->buffer);
} else if (!brw->has_llc && (!(access & GL_MAP_READ_BIT) ||
(access & GL_MAP_PERSISTENT_BIT))) {
map = brw_bo_map_gtt(brw, intel_obj->buffer);
map = brw_bo_map_gtt(brw, intel_obj->buffer, access);
mark_buffer_inactive(intel_obj);
} else {
map = brw_bo_map_cpu(brw, intel_obj->buffer, (access & GL_MAP_WRITE_BIT) != 0);
map = brw_bo_map_cpu(brw, intel_obj->buffer, access);
mark_buffer_inactive(intel_obj);
}
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+3 -3
View File
@@ -1386,7 +1386,7 @@ intel_miptree_init_mcs(struct brw_context *brw,
*
* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
*/
void *map = brw_bo_map_gtt(brw, mt->mcs_buf->bo);
void *map = brw_bo_map_gtt(brw, mt->mcs_buf->bo, MAP_READ | MAP_WRITE);
if (unlikely(map == NULL)) {
fprintf(stderr, "Failed to map mcs buffer into GTT\n");
brw_bo_unreference(mt->mcs_buf->bo);
@@ -2439,9 +2439,9 @@ intel_miptree_map_raw(struct brw_context *brw,
* long as cache consistency is maintained).
*/
if (mt->tiling != I915_TILING_NONE || mt->is_scanout)
return brw_bo_map_gtt(brw, bo);
return brw_bo_map_gtt(brw, bo, mode);
else
return brw_bo_map_cpu(brw, bo, mode & GL_MAP_WRITE_BIT);
return brw_bo_map_cpu(brw, bo, mode);
}
static void
src/mesa/drivers/dri/i965/intel_pixel_read.c
+1 -1
View File
@@ -145,7 +145,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
intel_batchbuffer_flush(brw);
}
void *map = brw_bo_map_cpu(brw, bo, false /* write enable */);
void *map = brw_bo_map_cpu(brw, bo, MAP_READ);
if (map == NULL) {
DBG("%s: failed to map bo\n", __func__);
return false;
src/mesa/drivers/dri/i965/intel_screen.c
+2 -2
View File
@@ -1420,7 +1420,7 @@ intel_detect_pipelined_register(struct intel_screen *screen,
if (bo == NULL)
goto err_results;
map = brw_bo_map_cpu(NULL, bo, 1);
map = brw_bo_map_cpu(NULL, bo, MAP_READ | MAP_WRITE);
if (!map)
goto err_batch;
@@ -1477,7 +1477,7 @@ intel_detect_pipelined_register(struct intel_screen *screen,
drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
/* Check whether the value got written. */
void *results_map = brw_bo_map_cpu(NULL, results, false);
void *results_map = brw_bo_map_cpu(NULL, results, MAP_READ);
if (results_map) {
success = *((uint32_t *)results_map + offset) == expected_value;
brw_bo_unmap(results);
src/mesa/drivers/dri/i965/intel_tex_image.c
+1 -1
View File
@@ -534,7 +534,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
intel_batchbuffer_flush(brw);
}
void *map = brw_bo_map_cpu(brw, bo, false /* write enable */);
void *map = brw_bo_map_cpu(brw, bo, MAP_READ);
if (map == NULL) {
DBG("%s: failed to map bo\n", __func__);
return false;
src/mesa/drivers/dri/i965/intel_tex_subimage.c
+1 -1
View File
@@ -146,7 +146,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
intel_batchbuffer_flush(brw);
}
void *map = brw_bo_map_cpu(brw, bo, true /* write enable */);
void *map = brw_bo_map_cpu(brw, bo, MAP_READ | MAP_WRITE);
if (map == NULL) {
DBG("%s: failed to map bo\n", __func__);
return false;
src/mesa/drivers/dri/i965/intel_upload.c
+2 -2
View File
@@ -101,9 +101,9 @@ intel_upload_space(struct brw_context *brw,
brw->upload.bo = brw_bo_alloc(brw->bufmgr, "streamed data",
MAX2(INTEL_UPLOAD_SIZE, size), 4096);
if (brw->has_llc)
brw->upload.map = brw_bo_map_cpu(brw, brw->upload.bo, true);
brw->upload.map = brw_bo_map_cpu(brw, brw->upload.bo, MAP_READ | MAP_WRITE);
else
brw->upload.map = brw_bo_map_gtt(brw, brw->upload.bo);
brw->upload.map = brw_bo_map_gtt(brw, brw->upload.bo, MAP_READ | MAP_WRITE);
}
brw->upload.next_offset = offset + size;