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i965: Rename brw_bo_map() -> brw_bo_map_cpu()

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I'm going to make a new function named brw_bo_map() in a later patch
that is responsible for choosing the mapping type, so this patch clears
the way.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner
2017-05-17 15:44:30 -07:00
parent 3d1530d3e8
commit 925a4222f2
16 changed files with 30 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_bufmgr.c
+5 -4
View File
@@ -659,7 +659,7 @@ set_domain(struct brw_context *brw, const char *action,
}
void *
brw_bo_map(struct brw_context *brw, struct brw_bo *bo, int write_enable)
brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, int write_enable)
{
struct brw_bufmgr *bufmgr = bo->bufmgr;
@@ -668,7 +668,7 @@ brw_bo_map(struct brw_context *brw, struct brw_bo *bo, int write_enable)
if (!bo->map_cpu) {
struct drm_i915_gem_mmap mmap_arg;
DBG("bo_map: %d (%s), map_count=%d\n",
DBG("brw_bo_map_cpu: %d (%s), map_count=%d\n",
bo->gem_handle, bo->name, bo->map_count);
memclear(mmap_arg);
@@ -686,7 +686,8 @@ brw_bo_map(struct brw_context *brw, struct brw_bo *bo, int write_enable)
VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
bo->map_cpu = (void *) (uintptr_t) mmap_arg.addr_ptr;
}
DBG("bo_map: %d (%s) -> %p\n", bo->gem_handle, bo->name, bo->map_cpu);
DBG("brw_bo_map_cpu: %d (%s) -> %p\n", bo->gem_handle, bo->name,
bo->map_cpu);
set_domain(brw, "CPU mapping", bo, I915_GEM_DOMAIN_CPU,
write_enable ? I915_GEM_DOMAIN_CPU : 0);
@@ -793,7 +794,7 @@ brw_bo_map_unsynchronized(struct brw_context *brw, struct brw_bo *bo)
/* If the CPU cache isn't coherent with the GTT, then use a
* regular synchronized mapping. The problem is that we don't
* track where the buffer was last used on the CPU side in
* terms of brw_bo_map vs brw_bo_map_gtt, so
* terms of brw_bo_map_cpu vs brw_bo_map_gtt, so
* we would potentially corrupt the buffer even when the user
* does reasonable things.
*/
src/mesa/drivers/dri/i965/brw_bufmgr.h
+2 -2
View File
@@ -137,7 +137,7 @@ struct brw_bo {
*
* Buffer objects are not necessarily initially mapped into CPU virtual
* address space or graphics device aperture. They must be mapped
* using bo_map() or brw_bo_map_gtt() to be used by the CPU.
* using brw_bo_map_cpu() or brw_bo_map_gtt() to be used by the CPU.
*/
struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
uint64_t size, uint64_t alignment);
@@ -179,7 +179,7 @@ void brw_bo_unreference(struct brw_bo *bo);
* This function will block waiting for any existing execution on the
* buffer to complete, first. The resulting mapping is returned.
*/
MUST_CHECK void *brw_bo_map(struct brw_context *brw, struct brw_bo *bo, int write_enable);
MUST_CHECK void *brw_bo_map_cpu(struct brw_context *brw, struct brw_bo *bo, int write_enable);
/**
* Reduces the refcount on the userspace mapping of the buffer
src/mesa/drivers/dri/i965/brw_performance_query.c
+3 -3
View File
@@ -713,7 +713,7 @@ accumulate_oa_reports(struct brw_context *brw,
if (!read_oa_samples(brw))
goto error;
query_buffer = brw_bo_map(brw, obj->oa.bo, false);
query_buffer = brw_bo_map_cpu(brw, obj->oa.bo, false);
start = last = query_buffer;
end = query_buffer + (MI_RPC_BO_END_OFFSET_BYTES / sizeof(uint32_t));
@@ -992,7 +992,7 @@ brw_begin_perf_query(struct gl_context *ctx,
MI_RPC_BO_SIZE, 64);
#ifdef DEBUG
/* Pre-filling the BO helps debug whether writes landed. */
void *map = brw_bo_map(brw, obj->oa.bo, true);
void *map = brw_bo_map_cpu(brw, obj->oa.bo, true);
memset(map, 0x80, MI_RPC_BO_SIZE);
brw_bo_unmap(obj->oa.bo);
#endif
@@ -1214,7 +1214,7 @@ get_pipeline_stats_data(struct brw_context *brw,
int n_counters = obj->query->n_counters;
uint8_t *p = data;
uint64_t *start = brw_bo_map(brw, obj->pipeline_stats.bo, false);
uint64_t *start = brw_bo_map_cpu(brw, obj->pipeline_stats.bo, false);
uint64_t *end = start + (STATS_BO_END_OFFSET_BYTES / sizeof(uint64_t));
for (int i = 0; i < n_counters; i++) {
src/mesa/drivers/dri/i965/brw_program.c
+1 -1
View File
@@ -578,7 +578,7 @@ brw_collect_shader_time(struct brw_context *brw)
* delaying reading the reports, but it doesn't look like it's a big
* overhead compared to the cost of tracking the time in the first place.
*/
void *bo_map = brw_bo_map(brw, brw->shader_time.bo, true);
void *bo_map = brw_bo_map_cpu(brw, brw->shader_time.bo, true);
for (int i = 0; i < brw->shader_time.num_entries; i++) {
uint32_t *times = bo_map + i * 3 * BRW_SHADER_TIME_STRIDE;
src/mesa/drivers/dri/i965/brw_program_cache.c
+3 -3
View File
@@ -227,7 +227,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
if (brw->has_llc) {
memcpy(llc_map, cache->map, cache->next_offset);
} else {
void *map = brw_bo_map(brw, cache->bo, false);
void *map = brw_bo_map_cpu(brw, cache->bo, false);
brw_bo_subdata(new_bo, 0, cache->next_offset, map);
brw_bo_unmap(cache->bo);
}
@@ -268,7 +268,7 @@ brw_lookup_prog(const struct brw_cache *cache,
void *map;
if (!brw->has_llc)
map = brw_bo_map(brw, cache->bo, false);
map = brw_bo_map_cpu(brw, cache->bo, false);
else
map = cache->map;
@@ -550,7 +550,7 @@ brw_print_program_cache(struct brw_context *brw)
void *map;
if (!brw->has_llc)
map = brw_bo_map(brw, cache->bo, false);
map = brw_bo_map_cpu(brw, cache->bo, false);
else
map = cache->map;
src/mesa/drivers/dri/i965/brw_queryobj.c
+1 -1
View File
@@ -146,7 +146,7 @@ brw_queryobj_get_results(struct gl_context *ctx,
}
}
results = brw_bo_map(brw, query->bo, false);
results = brw_bo_map_cpu(brw, query->bo, false);
switch (query->Base.Target) {
case GL_TIME_ELAPSED_EXT:
/* The query BO contains the starting and ending timestamps.
src/mesa/drivers/dri/i965/gen6_queryobj.c
+1 -1
View File
@@ -221,7 +221,7 @@ gen6_queryobj_get_results(struct gl_context *ctx,
if (query->bo == NULL)
return;
uint64_t *results = brw_bo_map(brw, query->bo, false);
uint64_t *results = brw_bo_map_cpu(brw, query->bo, false);
switch (query->Base.Target) {
case GL_TIME_ELAPSED:
/* The query BO contains the starting and ending timestamps.
src/mesa/drivers/dri/i965/gen6_sol.c
+1 -1
View File
@@ -247,7 +247,7 @@ tally_prims_generated(struct brw_context *brw,
if (unlikely(brw->perf_debug && brw_bo_busy(obj->prim_count_bo)))
perf_debug("Stalling for # of transform feedback primitives written.\n");
uint64_t *prim_counts = brw_bo_map(brw, obj->prim_count_bo, false);
uint64_t *prim_counts = brw_bo_map_cpu(brw, obj->prim_count_bo, false);
assert(obj->prim_count_buffer_index % (2 * streams) == 0);
int pairs = obj->prim_count_buffer_index / (2 * streams);
src/mesa/drivers/dri/i965/intel_batchbuffer.c
+2 -2
View File
@@ -100,7 +100,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch,
batch->bo = brw_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
if (has_llc) {
batch->map = brw_bo_map(NULL, batch->bo, true);
batch->map = brw_bo_map_cpu(NULL, batch->bo, true);
}
batch->map_next = batch->map;
@@ -239,7 +239,7 @@ do_batch_dump(struct brw_context *brw)
if (batch->ring != RENDER_RING)
return;
void *map = brw_bo_map(brw, batch->bo, false);
void *map = brw_bo_map_cpu(brw, batch->bo, false);
if (map == NULL) {
fprintf(stderr,
"WARNING: failed to map batchbuffer, "
src/mesa/drivers/dri/i965/intel_buffer_objects.c
+3 -3
View File
@@ -390,8 +390,8 @@ brw_map_buffer_range(struct gl_context *ctx,
alignment);
void *map;
if (brw->has_llc) {
map = brw_bo_map(brw, intel_obj->range_map_bo[index],
(access & GL_MAP_WRITE_BIT) != 0);
map = brw_bo_map_cpu(brw, intel_obj->range_map_bo[index],
(access & GL_MAP_WRITE_BIT) != 0);
} else {
map = brw_bo_map_gtt(brw, intel_obj->range_map_bo[index]);
}
@@ -411,7 +411,7 @@ brw_map_buffer_range(struct gl_context *ctx,
map = brw_bo_map_gtt(brw, intel_obj->buffer);
mark_buffer_inactive(intel_obj);
} else {
map = brw_bo_map(brw, intel_obj->buffer, (access & GL_MAP_WRITE_BIT) != 0);
map = brw_bo_map_cpu(brw, intel_obj->buffer, (access & GL_MAP_WRITE_BIT) != 0);
mark_buffer_inactive(intel_obj);
}
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+2 -2
View File
@@ -2426,7 +2426,7 @@ intel_miptree_map_raw(struct brw_context *brw,
if (brw_batch_references(&brw->batch, bo))
intel_batchbuffer_flush(brw);
/* brw_bo_map() uses a WB mmaping of the buffer's backing storage. It
/* brw_bo_map_cpu() uses a WB mmaping of the buffer's backing storage. It
* will utilize the CPU cache even if the buffer is incoherent with the
* GPU (i.e. any writes will be stored in the cache and not flushed to
* memory and so will be invisible to the GPU or display engine). This
@@ -2441,7 +2441,7 @@ intel_miptree_map_raw(struct brw_context *brw,
if (mt->tiling != I915_TILING_NONE || mt->is_scanout)
return brw_bo_map_gtt(brw, bo);
else
return brw_bo_map(brw, bo, mode & GL_MAP_WRITE_BIT);
return brw_bo_map_cpu(brw, bo, mode & GL_MAP_WRITE_BIT);
}
static void
src/mesa/drivers/dri/i965/intel_pixel_read.c
+1 -1
View File
@@ -145,7 +145,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
intel_batchbuffer_flush(brw);
}
void *map = brw_bo_map(brw, bo, false /* write enable */);
void *map = brw_bo_map_cpu(brw, bo, false /* write enable */);
if (map == NULL) {
DBG("%s: failed to map bo\n", __func__);
return false;
src/mesa/drivers/dri/i965/intel_screen.c
+2 -2
View File
@@ -1420,7 +1420,7 @@ intel_detect_pipelined_register(struct intel_screen *screen,
if (bo == NULL)
goto err_results;
map = brw_bo_map(NULL, bo, 1);
map = brw_bo_map_cpu(NULL, bo, 1);
if (!map)
goto err_batch;
@@ -1477,7 +1477,7 @@ intel_detect_pipelined_register(struct intel_screen *screen,
drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
/* Check whether the value got written. */
void *results_map = brw_bo_map(NULL, results, false);
void *results_map = brw_bo_map_cpu(NULL, results, false);
if (results_map) {
success = *((uint32_t *)results_map + offset) == expected_value;
brw_bo_unmap(results);
src/mesa/drivers/dri/i965/intel_tex_image.c
+1 -1
View File
@@ -534,7 +534,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
intel_batchbuffer_flush(brw);
}
void *map = brw_bo_map(brw, bo, false /* write enable */);
void *map = brw_bo_map_cpu(brw, bo, false /* write enable */);
if (map == NULL) {
DBG("%s: failed to map bo\n", __func__);
return false;
src/mesa/drivers/dri/i965/intel_tex_subimage.c
+1 -1
View File
@@ -146,7 +146,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
intel_batchbuffer_flush(brw);
}
void *map = brw_bo_map(brw, bo, true /* write enable */);
void *map = brw_bo_map_cpu(brw, bo, true /* write enable */);
if (map == NULL) {
DBG("%s: failed to map bo\n", __func__);
return false;
src/mesa/drivers/dri/i965/intel_upload.c
+1 -1
View File
@@ -101,7 +101,7 @@ intel_upload_space(struct brw_context *brw,
brw->upload.bo = brw_bo_alloc(brw->bufmgr, "streamed data",
MAX2(INTEL_UPLOAD_SIZE, size), 4096);
if (brw->has_llc)
brw->upload.map = brw_bo_map(brw, brw->upload.bo, true);
brw->upload.map = brw_bo_map_cpu(brw, brw->upload.bo, true);
else
brw->upload.map = brw_bo_map_gtt(brw, brw->upload.bo);
}