AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

freedreno/regs: Properly document a7xx CP_EVENT_WRITE, CP_WAIT_TIMESTAMP

Browse Source 
Event write is changes so much in a7xx that it makes sense to
create a new event CP_EVENT_WRITE7.

All credits to Connor Abbott for finding out what different flags
in these commands are doing.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
This commit is contained in:
Danylo Piliaiev
2023-06-29 19:30:08 +02:00
committed by Marge Bot
parent aceb82b80e
commit 271ba74766
2 changed files with 108 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/computerator/a6xx.cc
+11 -3
View File
@@ -368,9 +368,17 @@ event_write(struct fd_ringbuffer *ring, struct kernel *kernel,
{
unsigned seqno = 0;
OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt) |
COND(timestamp && CHIP == A7XX, CP_EVENT_WRITE_0_SEQNO));
if (CHIP == A6XX) {
OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt));
} else {
OUT_PKT7(ring, CP_EVENT_WRITE7, timestamp ? 4 : 1);
OUT_RING(ring,
CP_EVENT_WRITE7_0_EVENT(evt) |
COND(timestamp, CP_EVENT_WRITE7_0_WRITE_ENABLED |
CP_EVENT_WRITE7_0_WRITE_SRC(EV_WRITE_USER_32B)));
}
if (timestamp) {
struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
src/freedreno/registers/adreno/adreno_pm4.xml
+97 -5
View File
@@ -298,7 +298,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/>
<value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/>
<doc>generate an event that creates a write to memory when completed</doc>
<value name="CP_EVENT_WRITE" value="0x46"/>
<value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
<value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
<doc>generate a VS|PS_done event</doc>
<value name="CP_EVENT_WRITE_SHD" value="0x58"/>
<doc>generate a cache flush done event</doc>
@@ -1592,8 +1593,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<domain varset="chip" name="CP_EVENT_WRITE" width="32">
<reg32 offset="0" name="0">
<bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
<!-- write seqno, not applicable to all events, leads to a hang on unsupported ones -->
<bitfield name="SEQNO" pos="27" type="boolean" variants="A7XX-"/>
<!-- when set, write back timestamp instead of value from packet: -->
<bitfield name="TIMESTAMP" pos="30" type="boolean"/>
<bitfield name="IRQ" pos="31" type="boolean"/>
@@ -1613,6 +1612,74 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</reg32>
</domain>
<domain varset="chip" name="CP_EVENT_WRITE7" width="32">
<enum name="event_write_src">
<!-- Write payload[0] -->
<value value="0" name="EV_WRITE_USER_32B"/>
<!-- Write payload[0] payload[1] -->
<value value="1" name="EV_WRITE_USER_64B"/>
<!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
<value value="2" name="EV_WRITE_TIMESTAMP_SUM"/>
<value value="3" name="EV_WRITE_ALWAYSON"/>
<!-- Write payload[1] regs starting at payload[0] offset -->
<value value="4" name="EV_WRITE_REGS_CONTENT"/>
</enum>
<enum name="event_write_dst">
<value value="0" name="EV_DST_RAM"/>
<value value="1" name="EV_DST_ONCHIP"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
<bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/>
<!-- Write sample count at (iova + 16) -->
<bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/>
<!-- *(iova + 8) = *(iova + 16) - *iova -->
<bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/>
<!-- Next 4 flags are valid to set only when concurrent binning is enabled -->
<!-- Increment 16b BV counter. Valid only in BV pipe -->
<bitfield name="INC_BV_COUNT" pos="16" type="boolean"/>
<!-- Increment 16b BR counter. Valid only in BR pipe -->
<bitfield name="INC_BR_COUNT" pos="17" type="boolean"/>
<bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/>
<bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/>
<bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/>
<bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/>
<!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. -->
<bitfield name="WRITE_ENABLED" pos="27" type="boolean"/>
</reg32>
<stripe varset="event_write_dst" variants="EV_DST_RAM">
<reg32 offset="1" name="1">
<bitfield name="ADDR_0_LO" low="0" high="31"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="ADDR_0_HI" low="0" high="31"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="PAYLOAD_0" low="0" high="31"/>
</reg32>
<reg32 offset="4" name="4">
<bitfield name="PAYLOAD_1" low="0" high="31"/>
</reg32>
</stripe>
<stripe varset="event_write_dst" variants="EV_DST_ONCHIP">
<reg32 offset="1" name="1">
<bitfield name="ONCHIP_ADDR_0" low="0" high="31"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="PAYLOAD_0" low="0" high="31"/>
</reg32>
<reg32 offset="4" name="4">
<bitfield name="PAYLOAD_1" low="0" high="31"/>
</reg32>
</stripe>
</domain>
<domain name="CP_BLIT" width="32">
<enum name="cp_blit_cmd">
<value value="0" name="BLIT_OP_FILL"/>
@@ -2061,10 +2128,35 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</domain>
<domain name="CP_WAIT_TIMESTAMP" width="32">
<enum name="ts_wait_value_src">
<!-- Wait for value at memory address to be >= SRC_0 (signed comparison) -->
<value value="0" name="TS_WAIT_GE_32B"/>
<!-- Wait for value at memory address to be >= SRC_0 (unsigned) -->
<value value="1" name="TS_WAIT_GE_64B"/>
<!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
<value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/>
</enum>
<enum name="ts_wait_type">
<value value="0" name="TS_WAIT_RAM"/>
<value value="1" name="TS_WAIT_ONCHIP"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/>
<bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/>
</reg32>
<reg64 offset="1" name="ADDR" type="address"/>
<reg32 offset="3" name="TIMESTAMP" type="uint"/>
<stripe varset="ts_wait_type" variants="TS_WAIT_RAM">
<reg64 offset="1" name="ADDR" type="address"/>
</stripe>
<stripe varset="ts_wait_type" variants="TS_WAIT_ONCHIP">
<reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/>
</stripe>
<reg32 offset="3" name="SRC_0"/>
<reg32 offset="4" name="SRC_1"/>
</domain>
<domain name="CP_MODIFY_TIMESTAMP" width="32">