tu: Use reg usage tables for stale reg dbg option
Defining regs to stomp as ranges in a separate header is a mistake from maintenance standpoint. Now we have this information at the point where reg is defined. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
This commit is contained in:
Danylo Piliaiev
committed by
Marge Bot
Marge Bot
parent
aecb732320
commit
aceb82b80e
@@ -9,8 +9,6 @@
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#include <stdint.h>
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#include "a6xx.xml.h"
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#include "adreno_common.xml.h"
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#include "adreno_pm4.xml.h"
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/* In order to debug issues with usage of stale reg data we need to have
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* a list of regs which we allowed to stomp.
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@@ -24,189 +22,48 @@
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* stompable before each renderpass/blit.
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*/
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struct fd_stompable_reg_range {
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uint16_t start_reg;
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uint16_t end_reg;
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};
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static const struct fd_stompable_reg_range
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a6xx_fd_cmdbuf_stompable_reg_ranges[] = {
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{REG_A6XX_VSC_BIN_SIZE, REG_A6XX_VSC_DRAW_STRM_SIZE(31)},
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{REG_A6XX_UCHE_UNKNOWN_0E12, REG_A6XX_UCHE_UNKNOWN_0E12},
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{REG_A6XX_GRAS_CL_CNTL, REG_A6XX_GRAS_LRZ_DEPTH_VIEW},
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{REG_A6XX_GRAS_2D_BLIT_CNTL, REG_A6XX_GRAS_2D_RESOLVE_CNTL_2},
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{REG_A6XX_RB_BIN_CONTROL, REG_A6XX_RB_SAMPLE_LOCATION_1},
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{REG_A6XX_RB_RENDER_CONTROL0, REG_A6XX_RB_UNKNOWN_8811},
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{REG_A6XX_RB_UNKNOWN_8818, REG_A6XX_RB_UNKNOWN_881E},
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{REG_A6XX_RB_MRT(0), REG_A6XX_RB_BLEND_CNTL},
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{REG_A6XX_RB_DEPTH_PLANE_CNTL, REG_A6XX_RB_Z_BOUNDS_MAX},
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{REG_A6XX_RB_STENCIL_CONTROL, REG_A6XX_RB_STENCILWRMASK},
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{REG_A6XX_RB_WINDOW_OFFSET, REG_A6XX_RB_SAMPLE_COUNT_CONTROL},
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{REG_A6XX_RB_LRZ_CNTL, REG_A6XX_RB_LRZ_CNTL},
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{REG_A6XX_RB_Z_CLAMP_MIN, REG_A6XX_RB_Z_CLAMP_MAX},
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{REG_A6XX_RB_UNKNOWN_88D0, REG_A6XX_RB_BLIT_SCISSOR_BR},
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{REG_A6XX_RB_BIN_CONTROL2, REG_A6XX_RB_BLIT_INFO},
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{REG_A6XX_RB_UNKNOWN_88F0, REG_A6XX_RB_UNKNOWN_88F4},
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{REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, REG_A6XX_RB_MRT_FLAG_BUFFER(7)},
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{REG_A6XX_RB_SAMPLE_COUNT_ADDR, REG_A6XX_RB_SAMPLE_COUNT_ADDR},
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{REG_A6XX_RB_2D_DST_INFO, REG_A6XX_RB_2D_SRC_SOLID_C3},
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{REG_A6XX_RB_DBG_ECO_CNTL, REG_A6XX_RB_ADDR_MODE_CNTL},
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{REG_A6XX_RB_CCU_CNTL, REG_A6XX_RB_CCU_CNTL},
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{REG_A6XX_VPC_GS_PARAM, REG_A6XX_VPC_POLYGON_MODE},
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{REG_A6XX_VPC_VARYING_INTERP(0), REG_A6XX_VPC_POINT_COORD_INVERT},
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{REG_A6XX_VPC_UNKNOWN_9300, REG_A6XX_VPC_SO_DISABLE},
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{REG_A6XX_VPC_DBG_ECO_CNTL, REG_A6XX_VPC_PERFCTR_VPC_SEL(5)},
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{REG_A6XX_PC_TESS_NUM_VERTEX, REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL},
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{REG_A6XX_PC_POLYGON_MODE, REG_A6XX_PC_RASTER_CNTL},
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{REG_A6XX_PC_PRIMITIVE_CNTL_0, REG_A6XX_PC_MULTIVIEW_MASK},
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{REG_A6XX_PC_TESSFACTOR_ADDR, REG_A6XX_PC_TESSFACTOR_ADDR},
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{REG_A6XX_PC_VSTREAM_CONTROL, REG_A6XX_PC_BIN_DRAW_STRM},
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{REG_A6XX_PC_VISIBILITY_OVERRIDE, REG_A6XX_PC_VISIBILITY_OVERRIDE},
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{REG_A6XX_VFD_CONTROL_0, REG_A6XX_VFD_DEST_CNTL(31)},
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{REG_A6XX_VFD_POWER_CNTL, REG_A6XX_VFD_POWER_CNTL},
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{REG_A6XX_SP_VS_CTRL_REG0, REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET},
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{REG_A6XX_SP_HS_CTRL_REG0, REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET},
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{REG_A6XX_SP_DS_CTRL_REG0, REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET},
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{REG_A6XX_SP_GS_CTRL_REG0, REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET},
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{REG_A6XX_SP_VS_TEX_SAMP, REG_A6XX_SP_GS_TEX_CONST},
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{REG_A6XX_SP_FS_CTRL_REG0, REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET},
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{REG_A6XX_SP_CS_CTRL_REG0, REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET},
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{REG_A6XX_SP_CS_CNTL_0, REG_A6XX_SP_CS_CNTL_1},
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{REG_A6XX_SP_FS_TEX_SAMP, REG_A6XX_SP_CS_TEX_CONST},
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{REG_A6XX_SP_CS_IBO, REG_A6XX_SP_CS_IBO},
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{REG_A6XX_SP_CS_IBO_COUNT, REG_A6XX_SP_CS_IBO_COUNT},
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{REG_A6XX_SP_MODE_CONTROL, REG_A6XX_SP_BINDLESS_BASE(0)},
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{REG_A6XX_SP_IBO, REG_A6XX_SP_IBO_COUNT},
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{REG_A6XX_SP_CHICKEN_BITS, REG_A6XX_SP_FLOAT_CNTL},
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{REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, REG_A6XX_SP_UNKNOWN_B183},
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{REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR, REG_A6XX_SP_TP_MODE_CNTL},
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{REG_A6XX_SP_PS_2D_SRC_INFO, REG_A6XX_SP_WINDOW_OFFSET},
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{REG_A6XX_TPL1_DBG_ECO_CNTL, REG_A6XX_TPL1_DBG_ECO_CNTL},
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{REG_A6XX_HLSQ_VS_CNTL, REG_A6XX_HLSQ_GS_CNTL},
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{REG_A6XX_HLSQ_FS_CNTL_0, REG_A6XX_HLSQ_CS_CNTL},
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{REG_A6XX_HLSQ_CS_NDRANGE_0, REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z},
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{REG_A6XX_HLSQ_CS_BINDLESS_BASE(0), REG_A6XX_HLSQ_CS_BINDLESS_BASE(0)},
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{REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0},
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{REG_A6XX_HLSQ_FS_CNTL, REG_A6XX_HLSQ_SHARED_CONSTS},
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{REG_A6XX_HLSQ_BINDLESS_BASE(0), REG_A6XX_HLSQ_BINDLESS_BASE(0)},
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{REG_A6XX_HLSQ_UNKNOWN_BE00, REG_A6XX_HLSQ_UNKNOWN_BE01},
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};
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/* Return true if it is expected that reg is overwritten by a renderpass or
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* not used by anything in a renderpass. So it's safe to stomp the reg
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* beforehand.
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*/
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static bool
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a6xx_fd_reg_rp_stompable(bool turnip, uint16_t reg)
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/* Stomping some regs is known to cause issues */
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static inline bool
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fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
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{
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switch (reg) {
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case REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS ... REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS + 1:
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return !turnip;
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case REG_A6XX_VSC_PRIM_STRM_ADDRESS ... REG_A6XX_VSC_DRAW_STRM_LIMIT:
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return false;
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case REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL:
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return false;
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case REG_A6XX_GRAS_SAMPLE_CONFIG ... REG_A6XX_GRAS_SAMPLE_LOCATION_1:
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return turnip;
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case REG_A6XX_GRAS_UNKNOWN_80AF:
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return false;
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case REG_A6XX_GRAS_LRZ_DEPTH_VIEW:
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return turnip;
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case REG_A6XX_GRAS_UNKNOWN_8110:
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return false;
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case REG_A6XX_GRAS_DBG_ECO_CNTL ... REG_A6XX_GRAS_PERFCTR_LRZ_SEL(3):
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return false;
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case REG_A6XX_RB_SAMPLE_CONFIG ... REG_A6XX_RB_SAMPLE_LOCATION_1:
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return turnip;
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case REG_A6XX_RB_DITHER_CNTL:
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return !turnip;
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case REG_A6XX_RB_UNKNOWN_8811 ... REG_A6XX_RB_UNKNOWN_881E:
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return false;
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case REG_A6XX_RB_ALPHA_CONTROL:
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return !turnip;
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case REG_A6XX_RB_UNKNOWN_88F0:
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return false;
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case REG_A6XX_RB_SAMPLE_COUNT_ADDR ... REG_A6XX_RB_SAMPLE_COUNT_ADDR + 1:
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return false;
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case REG_A6XX_RB_UNKNOWN_8E01:
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return false;
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case REG_A6XX_RB_DBG_ECO_CNTL ... REG_A6XX_RB_CCU_CNTL:
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return false;
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case REG_A6XX_RB_PERFCTR_RB_SEL(0)... REG_A6XX_RB_UNKNOWN_8E51:
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return false;
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case REG_A6XX_VPC_UNKNOWN_9210 ... REG_A6XX_VPC_UNKNOWN_9211:
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return false;
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case REG_A6XX_VPC_SO(0) ... REG_A6XX_VPC_POINT_COORD_INVERT:
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return false;
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case REG_A6XX_VPC_UNKNOWN_9300:
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return false;
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case REG_A6XX_VPC_DBG_ECO_CNTL ... REG_A6XX_VPC_PERFCTR_VPC_SEL(5):
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return false;
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case REG_A6XX_PC_DRAW_CMD ... REG_A6XX_PC_MARKER:
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return false;
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case REG_A6XX_PC_DBG_ECO_CNTL ... REG_A6XX_PC_ADDR_MODE_CNTL:
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return false;
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case REG_A6XX_PC_TESSFACTOR_ADDR:
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return false;
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case REG_A6XX_VFD_MODE_CNTL:
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return false;
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case REG_A6XX_VFD_ADD_OFFSET:
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return false;
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case REG_A6XX_SP_UNKNOWN_A9A8:
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return false;
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case REG_A6XX_SP_DBG_ECO_CNTL ... REG_A6XX_SP_PERFCTR_SP_SEL(23):
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return false;
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case REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR ... REG_A6XX_SP_UNKNOWN_B183:
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return false;
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case REG_A6XX_SP_UNKNOWN_B190 ... REG_A6XX_SP_UNKNOWN_B191:
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return false;
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case REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR ... REG_A6XX_SP_TP_SAMPLE_LOCATION_1:
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return false;
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case REG_A6XX_SP_TP_MODE_CNTL:
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return false;
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case REG_A6XX_TPL1_DBG_ECO_CNTL ... REG_A6XX_TPL1_PERFCTR_TP_SEL(11):
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return false;
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case REG_A6XX_HLSQ_UNKNOWN_BE00 ... REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(5):
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return false;
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/* We should not stomp compute pipeline since they write registers directly
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* into command stream and should survive renderpass.
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*/
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case REG_A6XX_SP_CS_CTRL_REG0 ... REG_A6XX_SP_CS_CNTL_1:
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return false;
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case REG_A6XX_HLSQ_CS_CNTL ... REG_A6XX_HLSQ_CS_CNTL_1:
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return false;
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switch (CHIP) {
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case A6XX: {
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switch (reg) {
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/* Faults in
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* dEQP-VK.renderpass.suballocation.formats.r5g6b5_unorm_pack16.clear.clear
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* It seems that PC_CCU_FLUSH_COLOR_TS reads REG_A6XX_RB_DEPTH_PLANE_CNTL.
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*/
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case REG_A6XX_RB_DEPTH_PLANE_CNTL:
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/* Faults in
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* dEQP-VK.conditional_rendering.draw.condition_host_memory_expect_noop.draw
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*/
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case REG_A6XX_HLSQ_VS_CNTL ... REG_A6XX_HLSQ_GS_CNTL:
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case REG_A6XX_HLSQ_FS_CNTL:
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/* Faults in
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* dEQP-VK.memory_model.message_passing.ext.u32.coherent.atomic_atomic.atomicrmw.device.payload_local.image.guard_local.image.comp
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* while there is even no fragment shaders.
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*/
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case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1:
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return false;
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}
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break;
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}
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case A7XX: {
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switch (reg) {
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case REG_A6XX_RB_DEPTH_PLANE_CNTL:
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case REG_A7XX_HLSQ_VS_CNTL ... REG_A7XX_HLSQ_GS_CNTL:
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case REG_A7XX_HLSQ_FS_CNTL:
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case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1:
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return false;
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}
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break;
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}
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default: {
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unreachable("Unknown GPU");
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}
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}
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return true;
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}
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/* Stomping some regs is known to cause issues */
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static bool
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a6xx_fd_reg_do_not_stomp(bool turnip, uint16_t reg)
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{
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switch (reg) {
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/* Faults in
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* dEQP-VK.renderpass.suballocation.formats.r5g6b5_unorm_pack16.clear.clear
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* It seems that PC_CCU_FLUSH_COLOR_TS reads REG_A6XX_RB_DEPTH_PLANE_CNTL.
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*/
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case REG_A6XX_RB_DEPTH_PLANE_CNTL:
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return true;
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/* Faults in
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* dEQP-VK.conditional_rendering.draw.condition_host_memory_expect_noop.draw */
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case REG_A6XX_HLSQ_VS_CNTL ... REG_A6XX_HLSQ_GS_CNTL:
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return true;
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case REG_A6XX_HLSQ_FS_CNTL:
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return true;
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/* Faults in
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* dEQP-VK.memory_model.message_passing.ext.u32.coherent.atomic_atomic.atomicrmw.device.payload_local.image.guard_local.image.comp
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* while there is even no fragment shaders.
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*/
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case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1:
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return true;
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}
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return false;
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}
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#endif /* __FREEDRENO_STOMPABLE_REGS_H__ */
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@@ -1873,6 +1873,39 @@ static const struct debug_named_value tu_reg_stomper_options[] = {
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{ NULL, 0 }
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};
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template <chip CHIP>
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static inline void
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tu_cs_dbg_stomp_regs(struct tu_cs *cs,
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bool is_rp_blit,
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uint32_t first_reg,
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uint32_t last_reg,
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bool inverse)
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{
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const uint16_t *regs = NULL;
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size_t count = 0;
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if (is_rp_blit) {
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regs = &RP_BLIT_REGS<CHIP>[0];
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count = ARRAY_SIZE(RP_BLIT_REGS<CHIP>);
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} else {
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regs = &CMD_REGS<CHIP>[0];
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count = ARRAY_SIZE(CMD_REGS<CHIP>);
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}
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for (size_t i = 0; i < count; i++) {
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if (inverse) {
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if (regs[i] >= first_reg && regs[i] <= last_reg)
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continue;
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} else {
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if (regs[i] < first_reg || regs[i] > last_reg)
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continue;
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}
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if (fd_reg_stomp_allowed(CHIP, regs[i]))
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tu_cs_emit_write_reg(cs, regs[i], 0xffffffff);
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}
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}
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static void
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tu_init_dbg_reg_stomper(struct tu_device *device)
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{
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@@ -1901,32 +1934,9 @@ tu_init_dbg_reg_stomper(struct tu_device *device)
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tu_cs_init(rp_cs, device, TU_CS_MODE_GROW, 4096, "rp reg stomp cs");
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tu_cs_begin(rp_cs);
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size_t reg_ranges_count = ARRAY_SIZE(a6xx_fd_cmdbuf_stompable_reg_ranges);
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for (size_t i = 0; i < reg_ranges_count; i++) {
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struct fd_stompable_reg_range reg_range =
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a6xx_fd_cmdbuf_stompable_reg_ranges[i];
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for (uint16_t reg = reg_range.start_reg; reg <= reg_range.end_reg;
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reg++) {
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if (debug_flags & TU_DEBUG_REG_STOMP_INVERSE) {
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if (reg >= first_reg && reg <= last_reg)
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continue;
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} else {
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if (reg < first_reg || reg > last_reg)
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continue;
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}
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if (a6xx_fd_reg_do_not_stomp(true, reg))
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continue;
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if (debug_flags & TU_DEBUG_REG_STOMP_CMDBUF)
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tu_cs_emit_write_reg(cmdbuf_cs, reg, 0xffffffff);
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if ((debug_flags & TU_DEBUG_REG_STOMP_RENDERPASS) &&
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a6xx_fd_reg_rp_stompable(true, reg)) {
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tu_cs_emit_write_reg(rp_cs, reg, 0xffffffff);
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}
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}
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}
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bool inverse = debug_flags & TU_DEBUG_REG_STOMP_INVERSE;
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tu_cs_dbg_stomp_regs<A6XX>(cmdbuf_cs, false, first_reg, last_reg, inverse);
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tu_cs_dbg_stomp_regs<A6XX>(rp_cs, true, first_reg, last_reg, inverse);
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tu_cs_end(cmdbuf_cs);
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tu_cs_end(rp_cs);
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