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gallium/radeon: re-order radeon_surf::dcc and htile members

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2016-10-23 21:28:29 +02:00
parent 2a2e537577
commit 2664351dfe
1 changed files with 5 additions and 5 deletions
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src/gallium/drivers/radeon/radeon_winsys.h
+5 -5
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@@ -298,7 +298,12 @@ struct radeon_surf {
* changed by the calculator.
*/
uint64_t surf_size;
uint64_t dcc_size;
uint64_t htile_size;
uint32_t surf_alignment;
uint32_t dcc_alignment;
uint32_t htile_alignment;
/* This applies to EG and later. */
unsigned bankw:4; /* max 8 */
@@ -323,11 +328,6 @@ struct radeon_surf {
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
uint64_t dcc_size;
uint32_t dcc_alignment;
uint64_t htile_size;
uint32_t htile_alignment;
};
struct radeon_bo_list_item {