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gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignment

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these names were misleading.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2016-10-23 21:26:43 +02:00
parent 67a44c97af
commit 2a2e537577
7 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeon/r600_test_dma.c
+1 -1
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@@ -301,7 +301,7 @@ void r600_test_dma(struct r600_common_screen *rscreen)
set_random_pixels(ctx, src, &src_cpu);
/* clear dst pixels */
rctx->clear_buffer(ctx, dst, 0, rdst->surface.bo_size, 0, true);
rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
/* preparation */
src/gallium/drivers/radeon/r600_texture.c
+5 -5
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@@ -637,8 +637,8 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
out->tile_mode_index = fmask.tiling_index[0];
out->pitch_in_pixels = fmask.level[0].nblk_x;
out->bank_height = fmask.bankh;
out->alignment = MAX2(256, fmask.bo_alignment);
out->size = fmask.bo_size;
out->alignment = MAX2(256, fmask.surf_alignment);
out->size = fmask.surf_size;
}
static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
@@ -916,7 +916,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
fprintf(f, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.bankw,
rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
rtex->surface.tile_split, rtex->surface.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
@@ -1014,7 +1014,7 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
rtex->surface = *surface;
rtex->size = rtex->surface.bo_size;
rtex->size = rtex->surface.surf_size;
rtex->tc_compatible_htile = rtex->surface.htile_size != 0;
assert(!!(rtex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) ==
@@ -1088,7 +1088,7 @@ r600_texture_create_object(struct pipe_screen *screen,
/* Now create the backing buffer. */
if (!buf) {
r600_init_resource_fields(rscreen, resource, rtex->size,
rtex->surface.bo_alignment);
rtex->surface.surf_alignment);
resource->flags |= RADEON_FLAG_HANDLE;
src/gallium/drivers/radeon/radeon_video.c
+2 -2
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@@ -172,10 +172,10 @@ void rvid_join_surfaces(struct radeon_winsys* ws,
surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
/* adjust the texture layer offsets */
off = align(off, surfaces[i]->bo_alignment);
off = align(off, surfaces[i]->surf_alignment);
for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
surfaces[i]->level[j].offset += off;
off += surfaces[i]->bo_size;
off += surfaces[i]->surf_size;
}
for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
src/gallium/drivers/radeon/radeon_winsys.h
+2 -2
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@@ -297,8 +297,8 @@ struct radeon_surf {
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
uint64_t bo_size;
uint32_t bo_alignment;
uint64_t surf_size;
uint32_t surf_alignment;
/* This applies to EG and later. */
unsigned bankw:4; /* max 8 */
src/gallium/drivers/radeonsi/cik_sdma.c
+1 -1
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@@ -342,7 +342,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
(tiled_x + copy_width) % granularity;
if (start_linear_address < 0 ||
end_linear_address > linear->surface.bo_size)
end_linear_address > linear->surface.surf_size)
return false;
/* Check requirements. */
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+5 -5
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@@ -189,7 +189,7 @@ static int compute_level(struct amdgpu_winsys *ws,
}
surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
surf_level->nblk_x = AddrSurfInfoOut->pitch;
@@ -214,7 +214,7 @@ static int compute_level(struct amdgpu_winsys *ws,
else
surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
/* Clear DCC fields at the beginning. */
surf_level->dcc_offset = 0;
@@ -484,7 +484,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
}
}
surf->bo_size = 0;
surf->surf_size = 0;
surf->dcc_size = 0;
surf->dcc_alignment = 1;
surf->htile_size = 0;
@@ -499,7 +499,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
return r;
if (level == 0) {
surf->bo_alignment = AddrSurfInfoOut.baseAlign;
surf->surf_alignment = AddrSurfInfoOut.baseAlign;
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
set_micro_tile_mode(surf, &ws->info);
@@ -552,7 +552,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
* complicated.
*/
if (surf->dcc_size && tex->last_level > 0) {
surf->dcc_size = align64(surf->bo_size >> 8,
surf->dcc_size = align64(surf->surf_size >> 8,
ws->info.pipe_interleave_bytes *
ws->info.num_tile_pipes);
}
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+4 -4
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@@ -146,8 +146,8 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
assert(0);
}
surf_drm->bo_size = surf_ws->bo_size;
surf_drm->bo_alignment = surf_ws->bo_alignment;
surf_drm->bo_size = surf_ws->surf_size;
surf_drm->bo_alignment = surf_ws->surf_alignment;
surf_drm->bankw = surf_ws->bankw;
surf_drm->bankh = surf_ws->bankh;
@@ -178,8 +178,8 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
surf_ws->bpe = surf_drm->bpe;
surf_ws->flags = surf_drm->flags;
surf_ws->bo_size = surf_drm->bo_size;
surf_ws->bo_alignment = surf_drm->bo_alignment;
surf_ws->surf_size = surf_drm->bo_size;
surf_ws->surf_alignment = surf_drm->bo_alignment;
surf_ws->bankw = surf_drm->bankw;
surf_ws->bankh = surf_drm->bankh;