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iris: replace constant cache invalidate with hdc flush

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This implements Wa_14010840176.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21364>
This commit is contained in:
Tapani Pälli
2024-01-11 17:51:17 +02:00
parent c16645c091
commit 231ede4f0c
1 changed files with 16 additions and 1 deletions
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src/gallium/drivers/iris/iris_state.c
+16 -1
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@@ -9632,6 +9632,22 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
PIPE_CONTROL_CS_STALL, NULL, 0, 0);
}
batch_mark_sync_for_pipe_control(batch, flags);
#if INTEL_NEEDS_WA_14010840176
/* "If the intention of “constant cache invalidate” is
* to invalidate the L1 cache (which can cache constants), use “HDC
* pipeline flush” instead of Constant Cache invalidate command."
*
* "If L3 invalidate is needed, the w/a should be to set state invalidate
* in the pipe control command, in addition to the HDC pipeline flush."
*/
if (flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE) {
flags &= ~PIPE_CONTROL_CONST_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_FLUSH_HDC | PIPE_CONTROL_STATE_CACHE_INVALIDATE;
}
#endif
/* Emit --------------------------------------------------------------- */
if (INTEL_DEBUG(DEBUG_PIPE_CONTROL)) {
@@ -9667,7 +9683,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
imm, reason);
}
batch_mark_sync_for_pipe_control(batch, flags);
iris_batch_sync_region_start(batch);
const bool trace_pc =