r600: remove r600_get_param and r600_get_paramf
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32955>
This commit is contained in:
Qiang Yu
@@ -229,296 +229,6 @@ fail:
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* pipe_screen
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*/
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static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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{
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struct r600_screen *rscreen = (struct r600_screen *)pscreen;
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enum radeon_family family = rscreen->b.family;
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switch (param) {
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/* Supported features (boolean caps). */
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_OCCLUSION_QUERY:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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case PIPE_CAP_TEXTURE_SWIZZLE:
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
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case PIPE_CAP_SHADER_STENCIL_EXPORT:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
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case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_PRIMITIVE_RESTART:
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case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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case PIPE_CAP_VS_INSTANCEID:
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case PIPE_CAP_START_INSTANCE:
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
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case PIPE_CAP_VS_LAYER_VIEWPORT:
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case PIPE_CAP_SAMPLE_SHADING:
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case PIPE_CAP_MEMOBJ:
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case PIPE_CAP_CLIP_HALFZ:
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case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
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case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
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case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
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case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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case PIPE_CAP_INVALIDATE_BUFFER:
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case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
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case PIPE_CAP_QUERY_MEMORY_INFO:
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_LEGACY_MATH_RULES:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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return 1;
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case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
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return PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
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case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
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case PIPE_CAP_GL_SPIRV:
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return 1;
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case PIPE_CAP_TEXTURE_TRANSFER_MODES:
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return PIPE_TEXTURE_TRANSFER_BLIT;
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case PIPE_CAP_SHAREABLE_SHADERS:
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return 0;
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case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
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/* Optimal number for good TexSubImage performance on Polaris10. */
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return 64 * 1024 * 1024;
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case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
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return 1;
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case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
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return !UTIL_ARCH_BIG_ENDIAN && rscreen->b.info.has_userptr;
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case PIPE_CAP_COMPUTE:
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return rscreen->b.gfx_level > R700;
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case PIPE_CAP_TGSI_TEXCOORD:
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return 1;
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case PIPE_CAP_NIR_IMAGES_AS_DEREF:
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case PIPE_CAP_FAKE_SW_MSAA:
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return 0;
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case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
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return MIN2(rscreen->b.info.max_heap_size_kb * 1024ull / 4, INT_MAX);
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return R600_MAP_BUFFER_ALIGNMENT;
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case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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return 256;
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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return 4;
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case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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if (family >= CHIP_CEDAR)
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return 450;
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return 330;
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/* Supported except the original R600. */
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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/* R600 doesn't support per-MRT blends */
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return family == CHIP_R600 ? 0 : 1;
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/* Supported on Evergreen. */
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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case PIPE_CAP_FS_FINE_DERIVATIVE:
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
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case PIPE_CAP_SHADER_CLOCK:
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case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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case PIPE_CAP_IMAGE_STORE_FORMATTED:
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case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
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return family >= CHIP_CEDAR ? 1 : 0;
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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return family >= CHIP_CEDAR ? 4 : 0;
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case PIPE_CAP_DRAW_INDIRECT:
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/* kernel command checker support is also required */
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return family >= CHIP_CEDAR;
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case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
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return family >= CHIP_CEDAR ? 0 : 1;
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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return 8;
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case PIPE_CAP_MAX_GS_INVOCATIONS:
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return 32;
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/* shader buffer objects */
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case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
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return 1 << 27;
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case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
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return 8;
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case PIPE_CAP_INT64:
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case PIPE_CAP_DOUBLES:
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if (rscreen->b.family == CHIP_ARUBA ||
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rscreen->b.family == CHIP_CAYMAN ||
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rscreen->b.family == CHIP_CYPRESS ||
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rscreen->b.family == CHIP_HEMLOCK)
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return 1;
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if (rscreen->b.family >= CHIP_CEDAR)
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return 1;
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return 0;
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case PIPE_CAP_TWO_SIDED_COLOR:
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return 0;
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case PIPE_CAP_CULL_DISTANCE:
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return 1;
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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if (family >= CHIP_CEDAR)
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return 256;
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return 0;
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case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
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if (family >= CHIP_CEDAR)
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return 30;
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else
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return 0;
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/* Stream output. */
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case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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return rscreen->b.has_streamout ? 4 : 0;
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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return rscreen->b.has_streamout ? 1 : 0;
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case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
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case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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return 32*4;
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/* Geometry shader output. */
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case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
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return 1024;
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case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
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return 16384;
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case PIPE_CAP_MAX_VERTEX_STREAMS:
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return family >= CHIP_CEDAR ? 4 : 1;
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case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
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/* Should be 2047, but 2048 is a requirement for GL 4.4 */
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return 2048;
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/* Texturing. */
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case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
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if (family >= CHIP_CEDAR)
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return 16384;
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else
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return 8192;
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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if (family >= CHIP_CEDAR)
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return 15;
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else
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return 14;
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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/* textures support 8192, but layered rendering supports 2048 */
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return 12;
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case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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/* textures support 8192, but layered rendering supports 2048 */
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return 2048;
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/* Render targets. */
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case PIPE_CAP_MAX_RENDER_TARGETS:
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/* XXX some r6xx are buggy and can only do 4 */
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return 8;
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case PIPE_CAP_MAX_VIEWPORTS:
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return R600_MAX_VIEWPORTS;
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case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
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case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
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return 8;
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/* Timer queries, present when the clock frequency is non zero. */
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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case PIPE_CAP_QUERY_TIMESTAMP:
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return rscreen->b.info.clock_crystal_freq != 0;
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case PIPE_CAP_TIMER_RESOLUTION:
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/* Conversion to nanos from cycles per millisecond */
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return DIV_ROUND_UP(1000000, rscreen->b.info.clock_crystal_freq);
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case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
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case PIPE_CAP_MIN_TEXEL_OFFSET:
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return -8;
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case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
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case PIPE_CAP_MAX_TEXEL_OFFSET:
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return 7;
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case PIPE_CAP_MAX_VARYINGS:
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return 32;
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case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
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case PIPE_CAP_ENDIANNESS:
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return PIPE_ENDIAN_LITTLE;
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case PIPE_CAP_VENDOR_ID:
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return ATI_VENDOR_ID;
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case PIPE_CAP_DEVICE_ID:
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return rscreen->b.info.pci_id;
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case PIPE_CAP_ACCELERATED:
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return 1;
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case PIPE_CAP_VIDEO_MEMORY:
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return rscreen->b.info.vram_size_kb >> 10;
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case PIPE_CAP_UMA:
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return 0;
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case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
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return rscreen->b.gfx_level >= R700;
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case PIPE_CAP_PCI_GROUP:
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return rscreen->b.info.pci.domain;
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case PIPE_CAP_PCI_BUS:
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return rscreen->b.info.pci.bus;
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case PIPE_CAP_PCI_DEVICE:
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return rscreen->b.info.pci.dev;
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case PIPE_CAP_PCI_FUNCTION:
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return rscreen->b.info.pci.func;
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case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
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if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
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return 8;
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return 0;
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case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
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if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
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return EG_MAX_ATOMIC_BUFFERS;
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return 0;
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case PIPE_CAP_VALIDATE_ALL_DIRTY_STATES:
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return 1;
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default:
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return u_pipe_screen_get_param_defaults(pscreen, param);
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}
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}
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static int r600_get_shader_param(struct pipe_screen* pscreen,
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enum pipe_shader_type shader,
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enum pipe_shader_cap param)
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@@ -881,7 +591,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
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/* Set functions first. */
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rscreen->b.b.context_create = r600_create_context;
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rscreen->b.b.destroy = r600_destroy_screen;
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rscreen->b.b.get_param = r600_get_param;
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rscreen->b.b.get_shader_param = r600_get_shader_param;
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rscreen->b.b.resource_create = r600_resource_create;
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@@ -773,37 +773,6 @@ static const char* r600_get_name(struct pipe_screen* pscreen)
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return rscreen->renderer_string;
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}
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static float r600_get_paramf(struct pipe_screen* pscreen,
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enum pipe_capf param)
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{
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switch (param) {
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case PIPE_CAPF_MIN_LINE_WIDTH:
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case PIPE_CAPF_MIN_LINE_WIDTH_AA:
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case PIPE_CAPF_MIN_POINT_SIZE:
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case PIPE_CAPF_MIN_POINT_SIZE_AA:
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return 1;
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case PIPE_CAPF_POINT_SIZE_GRANULARITY:
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case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
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return 0.1;
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case PIPE_CAPF_MAX_LINE_WIDTH:
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case PIPE_CAPF_MAX_LINE_WIDTH_AA:
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case PIPE_CAPF_MAX_POINT_SIZE:
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case PIPE_CAPF_MAX_POINT_SIZE_AA:
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return 8191.0f;
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case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
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return 16.0f;
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case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
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return 16.0f;
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case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
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case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
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case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
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return 0.0f;
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}
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return 0.0f;
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}
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static int r600_get_video_param(struct pipe_screen *screen,
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enum pipe_video_profile profile,
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enum pipe_video_entrypoint entrypoint,
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@@ -1266,7 +1235,6 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
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rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
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rscreen->b.get_compute_param = r600_get_compute_param;
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rscreen->b.get_screen_fd = r600_get_screen_fd;
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rscreen->b.get_paramf = r600_get_paramf;
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rscreen->b.get_timestamp = r600_get_timestamp;
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rscreen->b.get_compiler_options = r600_get_compiler_options;
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rscreen->b.fence_finish = r600_fence_finish;
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