AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: adjust the base upload offset when DGC uses task shaders

Browse Source 
The upload space is after the DGC ACE IB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
This commit is contained in:
Samuel Pitoiset
2024-06-27 16:04:20 +02:00
committed by Marge Bot
parent f55d4f2f09
commit 1ffb420edd
1 changed files with 3 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_device_generated_commands.c
+3 -1
View File
@@ -2562,7 +2562,9 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
offset += radv_dgc_preamble_cmdbuf_size(device, AMD_IP_COMPUTE);
ace_cmd_buf_main_offset = offset;
const uint32_t upload_main_offset = cmd_buf_main_offset + cmd_buf_size;
uint32_t upload_main_offset = cmd_buf_main_offset + cmd_buf_size;
if (radv_dgc_with_task_shader(pGeneratedCommandsInfo))
upload_main_offset = ace_cmd_buf_main_offset + ace_cmd_buf_size;
struct radv_dgc_params params = {
.cmd_buf_main_offset = cmd_buf_main_offset,