From 1ffb420eddda644e32704ade71d688f695f057cc Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 27 Jun 2024 16:04:20 +0200 Subject: [PATCH] radv: adjust the base upload offset when DGC uses task shaders The upload space is after the DGC ACE IB. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_device_generated_commands.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 330c81e7943..80dbdf8d7e0 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -2562,7 +2562,9 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn offset += radv_dgc_preamble_cmdbuf_size(device, AMD_IP_COMPUTE); ace_cmd_buf_main_offset = offset; - const uint32_t upload_main_offset = cmd_buf_main_offset + cmd_buf_size; + uint32_t upload_main_offset = cmd_buf_main_offset + cmd_buf_size; + if (radv_dgc_with_task_shader(pGeneratedCommandsInfo)) + upload_main_offset = ace_cmd_buf_main_offset + ace_cmd_buf_size; struct radv_dgc_params params = { .cmd_buf_main_offset = cmd_buf_main_offset,