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radv: disable SINGLE clear codes to workaround a hw bug with DCC on GFX11

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This fixes a very weird cache-related corruption with DCC on GFX11 due
to a hw bug according to PAL.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12932
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34790>
This commit is contained in:
Samuel Pitoiset
2025-05-02 11:02:41 +02:00
committed by Marge Bot
parent 55ad0fd35c
commit 1356d20042
1 changed files with 6 additions and 0 deletions
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src/amd/vulkan/radv_queue.c
+6
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@@ -916,6 +916,12 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
ac_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0);
}
if (pdev->info.family >= CHIP_NAVI31 && pdev->info.family <= CHIP_GFX1150) {
/* Disable SINGLE clear codes on GFX11 (including first GFX11.5 rev) to workaround a hw bug
* with DCC. */
ac_pm4_set_reg(pm4, R_028424_CB_FDCC_CONTROL, S_028424_DISABLE_CONSTANT_ENCODE_SINGLE(1));
}
ac_pm4_finalize(pm4);
radv_emit_pm4_commands(cs, pm4);
ac_pm4_free_state(pm4);