From 1356d2004287354fdd959f495097ad6be4a34dcb Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 2 May 2025 11:02:41 +0200 Subject: [PATCH] radv: disable SINGLE clear codes to workaround a hw bug with DCC on GFX11 This fixes a very weird cache-related corruption with DCC on GFX11 due to a hw bug according to PAL. Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12932 Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_queue.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 5b110c4dd1f..30a24a98bca 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -916,6 +916,12 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) ac_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0); } + if (pdev->info.family >= CHIP_NAVI31 && pdev->info.family <= CHIP_GFX1150) { + /* Disable SINGLE clear codes on GFX11 (including first GFX11.5 rev) to workaround a hw bug + * with DCC. */ + ac_pm4_set_reg(pm4, R_028424_CB_FDCC_CONTROL, S_028424_DISABLE_CONSTANT_ENCODE_SINGLE(1)); + } + ac_pm4_finalize(pm4); radv_emit_pm4_commands(cs, pm4); ac_pm4_free_state(pm4);