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svga: Redo the way generated files are handled

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Long time ago svga had a sourceforge project where auto-generated
header files for the SVGA device were hosted. Gallium's svga driver
copied those files and when the sourceforge project became
obsolete they started being updated by hand.

Kernel and igt projects switched to the official way in which the SVGA
header files are generated but Mesa3d wasn't ported at the time.

The official SVGA headers diverged from the official ones creating bugs.
Fix it by porting the SVGA Gallium driver to the auto-generated SVGA
header files.

Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31653>
This commit is contained in:
Zack Rusin
2024-10-10 08:02:26 -04:00
committed by Marge Bot
parent 8423998d69
commit 05e0554d76
43 changed files with 6206 additions and 8717 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/svga/include/README
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This directory contains the headers from the VMware SVGA Device Developer Kit:
Files in this directory are auto-generated from description files and any changes made to them will be discarded on the next update.
https://vmware-svga.svn.sourceforge.net/svnroot/vmware-svga/trunk/lib/vmware/
Only vmw_surf_defs.h and vm_basic_types.h are written from scratch and provide the glue necessary for the auto-generated files (the rest of them).
src/gallium/drivers/svga/include/VGPU10ShaderTokens.h
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src/gallium/drivers/svga/include/includeCheck.h
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@@ -1 +0,0 @@
/* dummy file */
src/gallium/drivers/svga/include/svga3d_caps.h
-96
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@@ -1,96 +0,0 @@
/*
* Copyright (c) 2007-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*/
/*
* svga3d_caps.h --
*
* Definitions for SVGA3D hardware capabilities. Capabilities
* are used to query for optional rendering features during
* driver initialization. The capability data is stored as very
* basic key/value dictionary within the "FIFO register" memory
* area at the beginning of BAR2.
*
* Note that these definitions are only for 3D capabilities.
* The SVGA device also has "device capabilities" and "FIFO
* capabilities", which are non-3D-specific and are stored as
* bitfields rather than key/value pairs.
*/
#ifndef _SVGA3D_CAPS_H_
#define _SVGA3D_CAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#include "includeCheck.h"
#include <string.h>
#include "svga_reg.h"
#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \
SVGA_FIFO_3D_CAPS + 1)
/*
* SVGA3dCapsRecordType
*
* Record types that can be found in the caps block.
* Related record types are grouped together numerically so that
* SVGA3dCaps_FindRecord() can be applied on a range of record
* types.
*/
typedef enum {
SVGA3DCAPS_RECORD_UNKNOWN = 0,
SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
} SVGA3dCapsRecordType;
/*
* SVGA3dCapsRecordHeader
*
* Header field leading each caps block record. Contains the offset (in
* register words, NOT bytes) to the next caps block record (or the end
* of caps block records which will be a zero word) and the record type
* as defined above.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecordHeader {
uint32 length;
SVGA3dCapsRecordType type;
}
#include "vmware_pack_end.h"
SVGA3dCapsRecordHeader;
/*
* SVGA3dCapsRecord
*
* Caps block record; "data" is a placeholder for the actual data structure
* contained within the record; for example a record containing a FOOBAR
* structure would be of size "sizeof(SVGA3dCapsRecordHeader) +
* sizeof(FOOBAR)".
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecord {
SVGA3dCapsRecordHeader header;
uint32 data[1];
}
#include "vmware_pack_end.h"
SVGA3dCapsRecord;
typedef uint32 SVGA3dCapPair[2];
#endif
src/gallium/drivers/svga/include/svga3d_cmd.h
+971 -1731
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src/gallium/drivers/svga/include/svga3d_devcaps.h
+320 -415
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@@ -1,463 +1,368 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (c) 1998-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-3.0 OR MIT
* Copyright (c) 1998-2021 Broadcom. All Rights Reserved. The term
* "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
/*
* svga3d_devcaps.h --
*
* SVGA 3d caps definitions
* SVGA 3d caps definitions
*/
#ifndef _SVGA3D_DEVCAPS_H_
#define _SVGA3D_DEVCAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "svga3d_types.h"
#include "includeCheck.h"
/*
* 3D Hardware Version
*
* The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
* register. Is set by the host and read by the guest. This lets
* us make new guest drivers which are backwards-compatible with old
* SVGA hardware revisions. It does not let us support old guest
* drivers. Good enough for now.
*
*/
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
typedef enum {
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
} SVGA3dHardwareVersion;
/*
* DevCap indexes.
*/
typedef uint32 SVGA3dDevCapIndex;
typedef enum {
SVGA3D_DEVCAP_INVALID = ((uint32)-1),
SVGA3D_DEVCAP_3D = 0,
SVGA3D_DEVCAP_MAX_LIGHTS = 1,
#define SVGA3D_DEVCAP_INVALID ((uint32) - 1)
#define SVGA3D_DEVCAP_3D 0
#define SVGA3D_DEVCAP_MAX_LIGHTS 1
/*
* SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
* fixed-function texture units available. Each of these units
* work in both FFP and Shader modes, and they support texture
* transforms and texture coordinates. The host may have additional
* texture image units that are only usable with shaders.
*/
SVGA3D_DEVCAP_MAX_TEXTURES = 2,
SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
SVGA3D_DEVCAP_VERTEX_SHADER = 5,
SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12,
SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13,
SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14,
SVGA3D_DEVCAP_QUERY_TYPES = 15,
SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
SVGA3D_DEVCAP_TEXTURE_OPS = 31,
SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
#define SVGA3D_DEVCAP_MAX_TEXTURES 2
#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
#define SVGA3D_DEVCAP_VERTEX_SHADER 5
#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
#define SVGA3D_DEVCAP_QUERY_TYPES 15
#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
#define SVGA3D_DEVCAP_TEXTURE_OPS 31
#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
/*
* There is a hole in our devcap definitions for
* historical reasons.
*
* Define a constant just for completeness.
*/
SVGA3D_DEVCAP_MISSING62 = 62,
#define SVGA3D_DEVCAP_MISSING62 62
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
/*
* Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
* render targets. This does not include the depth or stencil targets.
*/
SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
/*
* Deprecated.
*/
SVGA3D_DEVCAP_DEAD4 = 70,
SVGA3D_DEVCAP_DEAD5 = 71,
SVGA3D_DEVCAP_DEAD7 = 72,
SVGA3D_DEVCAP_DEAD6 = 73,
#define SVGA3D_DEVCAP_DEAD4 70
#define SVGA3D_DEVCAP_DEAD5 71
#define SVGA3D_DEVCAP_DEAD7 72
#define SVGA3D_DEVCAP_DEAD6 73
SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
#define SVGA3D_DEVCAP_DEAD10 76
/*
* This is the maximum number of SVGA context IDs that the guest
* can define using SVGA_3D_CMD_CONTEXT_DEFINE.
*/
SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
/*
* This is the maximum number of SVGA surface IDs that the guest
* can define using SVGA_3D_CMD_SURFACE_DEFINE*.
*/
SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
SVGA3D_DEVCAP_SURFACEFMT_ATI1 = 82,
SVGA3D_DEVCAP_SURFACEFMT_ATI2 = 83,
#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
/*
* Deprecated.
*/
SVGA3D_DEVCAP_DEAD1 = 84,
SVGA3D_DEVCAP_DEAD8 = 85,
SVGA3D_DEVCAP_DEAD9 = 86,
#define SVGA3D_DEVCAP_DEAD1 84
#define SVGA3D_DEVCAP_DEAD8 85
#define SVGA3D_DEVCAP_DEAD9 86
SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
#define SVGA3D_DEVCAP_LINE_AA 87
#define SVGA3D_DEVCAP_LINE_STIPPLE 88
#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89
#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90
SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
/*
* Deprecated.
*/
SVGA3D_DEVCAP_DEAD3 = 92,
#define SVGA3D_DEVCAP_DEAD3 92
/*
* Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
*/
SVGA3D_DEVCAP_TS_COLOR_KEY = 93, /* boolean */
#define SVGA3D_DEVCAP_TS_COLOR_KEY 93
/*
* Deprecated.
*/
SVGA3D_DEVCAP_DEAD2 = 94,
#define SVGA3D_DEVCAP_DEAD2 94
/*
* Does the device support DXContexts? (ie DX10 era rendering)
*/
SVGA3D_DEVCAP_DXCONTEXT = 95,
#define SVGA3D_DEVCAP_DXCONTEXT 95
/*
* What is the maximum size of a texture array?
*
* (Even if this cap is zero, cubemaps are still allowed.)
*/
SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96,
#define SVGA3D_DEVCAP_DEAD11 96
/*
* What is the maximum number of vertex buffers or vertex input registers
* that can be expected to work correctly with a DXContext?
*
* The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
* anything in excess of this cap is not guaranteed to render correctly.
*
* Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
* input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
* SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
* but only the registers up to this cap value are guaranteed to render
* correctly.
*
* If guest-drivers are able to expose a lower-limit, it's recommended
* that they clamp to this value. Otherwise, the host will make a
* best-effort on case-by-case basis if guests exceed this.
*/
SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97,
#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
/*
* What is the maximum number of constant buffers that can be expected to
* work correctly with a DX context?
*
* The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
* anything in excess of this cap is not guaranteed to render correctly.
*
* If guest-drivers are able to expose a lower-limit, it's recommended
* that they clamp to this value. Otherwise, the host will make a
* best-effort on case-by-case basis if guests exceed this.
*/
SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98,
#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
/*
* Does the device support provoking vertex control?
*
* If this cap is present, the provokingVertexLast field in the
* rasterizer state is enabled. (Guests can then set it to FALSE,
* meaning that the first vertex is the provoking vertex, or TRUE,
* meaning that the last vertex is the provoking vertex.)
*
* If this cap is FALSE, then guests should set the provokingVertexLast
* to FALSE, otherwise rendering behavior is undefined.
*/
SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99,
#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
SVGA3D_DEVCAP_DXFMT_X8R8G8B8 = 100,
SVGA3D_DEVCAP_DXFMT_A8R8G8B8 = 101,
SVGA3D_DEVCAP_DXFMT_R5G6B5 = 102,
SVGA3D_DEVCAP_DXFMT_X1R5G5B5 = 103,
SVGA3D_DEVCAP_DXFMT_A1R5G5B5 = 104,
SVGA3D_DEVCAP_DXFMT_A4R4G4B4 = 105,
SVGA3D_DEVCAP_DXFMT_Z_D32 = 106,
SVGA3D_DEVCAP_DXFMT_Z_D16 = 107,
SVGA3D_DEVCAP_DXFMT_Z_D24S8 = 108,
SVGA3D_DEVCAP_DXFMT_Z_D15S1 = 109,
SVGA3D_DEVCAP_DXFMT_LUMINANCE8 = 110,
SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 = 111,
SVGA3D_DEVCAP_DXFMT_LUMINANCE16 = 112,
SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 = 113,
SVGA3D_DEVCAP_DXFMT_DXT1 = 114,
SVGA3D_DEVCAP_DXFMT_DXT2 = 115,
SVGA3D_DEVCAP_DXFMT_DXT3 = 116,
SVGA3D_DEVCAP_DXFMT_DXT4 = 117,
SVGA3D_DEVCAP_DXFMT_DXT5 = 118,
SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119,
SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120,
SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121,
SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 = 122,
SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123,
SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124,
SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125,
SVGA3D_DEVCAP_DXFMT_V8U8 = 126,
SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 = 127,
SVGA3D_DEVCAP_DXFMT_CxV8U8 = 128,
SVGA3D_DEVCAP_DXFMT_X8L8V8U8 = 129,
SVGA3D_DEVCAP_DXFMT_A2W10V10U10 = 130,
SVGA3D_DEVCAP_DXFMT_ALPHA8 = 131,
SVGA3D_DEVCAP_DXFMT_R_S10E5 = 132,
SVGA3D_DEVCAP_DXFMT_R_S23E8 = 133,
SVGA3D_DEVCAP_DXFMT_RG_S10E5 = 134,
SVGA3D_DEVCAP_DXFMT_RG_S23E8 = 135,
SVGA3D_DEVCAP_DXFMT_BUFFER = 136,
SVGA3D_DEVCAP_DXFMT_Z_D24X8 = 137,
SVGA3D_DEVCAP_DXFMT_V16U16 = 138,
SVGA3D_DEVCAP_DXFMT_G16R16 = 139,
SVGA3D_DEVCAP_DXFMT_A16B16G16R16 = 140,
SVGA3D_DEVCAP_DXFMT_UYVY = 141,
SVGA3D_DEVCAP_DXFMT_YUY2 = 142,
SVGA3D_DEVCAP_DXFMT_NV12 = 143,
SVGA3D_DEVCAP_FORMAT_DEAD2 = 144,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS = 145,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT = 146,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT = 147,
SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS = 148,
SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT = 149,
SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT = 150,
SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT = 151,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS = 152,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT = 153,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM = 154,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT = 155,
SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS = 156,
SVGA3D_DEVCAP_DXFMT_R32G32_UINT = 157,
SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158,
SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159,
SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160,
SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 = 161,
SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT = 162,
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163,
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164,
SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS = 166,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM = 167,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB = 168,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT = 169,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT = 170,
SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS = 171,
SVGA3D_DEVCAP_DXFMT_R16G16_UINT = 172,
SVGA3D_DEVCAP_DXFMT_R16G16_SINT = 173,
SVGA3D_DEVCAP_DXFMT_R32_TYPELESS = 174,
SVGA3D_DEVCAP_DXFMT_D32_FLOAT = 175,
SVGA3D_DEVCAP_DXFMT_R32_UINT = 176,
SVGA3D_DEVCAP_DXFMT_R32_SINT = 177,
SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178,
SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179,
SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 = 180,
SVGA3D_DEVCAP_DXFMT_X24_G8_UINT = 181,
SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182,
SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183,
SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184,
SVGA3D_DEVCAP_DXFMT_R8G8_SINT = 185,
SVGA3D_DEVCAP_DXFMT_R16_TYPELESS = 186,
SVGA3D_DEVCAP_DXFMT_R16_UNORM = 187,
SVGA3D_DEVCAP_DXFMT_R16_UINT = 188,
SVGA3D_DEVCAP_DXFMT_R16_SNORM = 189,
SVGA3D_DEVCAP_DXFMT_R16_SINT = 190,
SVGA3D_DEVCAP_DXFMT_R8_TYPELESS = 191,
SVGA3D_DEVCAP_DXFMT_R8_UNORM = 192,
SVGA3D_DEVCAP_DXFMT_R8_UINT = 193,
SVGA3D_DEVCAP_DXFMT_R8_SNORM = 194,
SVGA3D_DEVCAP_DXFMT_R8_SINT = 195,
SVGA3D_DEVCAP_DXFMT_P8 = 196,
SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP = 197,
SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM = 198,
SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM = 199,
SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS = 200,
SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB = 201,
SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS = 202,
SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB = 203,
SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS = 204,
SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB = 205,
SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS = 206,
SVGA3D_DEVCAP_DXFMT_ATI1 = 207,
SVGA3D_DEVCAP_DXFMT_BC4_SNORM = 208,
SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS = 209,
SVGA3D_DEVCAP_DXFMT_ATI2 = 210,
SVGA3D_DEVCAP_DXFMT_BC5_SNORM = 211,
SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM = 212,
SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS = 213,
SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB = 214,
SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS = 215,
SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB = 216,
SVGA3D_DEVCAP_DXFMT_Z_DF16 = 217,
SVGA3D_DEVCAP_DXFMT_Z_DF24 = 218,
SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT = 219,
SVGA3D_DEVCAP_DXFMT_YV12 = 220,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT = 221,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT = 222,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM = 223,
SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT = 224,
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM = 225,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM = 226,
SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT = 227,
SVGA3D_DEVCAP_DXFMT_R16G16_UNORM = 228,
SVGA3D_DEVCAP_DXFMT_R16G16_SNORM = 229,
SVGA3D_DEVCAP_DXFMT_R32_FLOAT = 230,
SVGA3D_DEVCAP_DXFMT_R8G8_SNORM = 231,
SVGA3D_DEVCAP_DXFMT_R16_FLOAT = 232,
SVGA3D_DEVCAP_DXFMT_D16_UNORM = 233,
SVGA3D_DEVCAP_DXFMT_A8_UNORM = 234,
SVGA3D_DEVCAP_DXFMT_BC1_UNORM = 235,
SVGA3D_DEVCAP_DXFMT_BC2_UNORM = 236,
SVGA3D_DEVCAP_DXFMT_BC3_UNORM = 237,
SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM = 238,
SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM = 239,
SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM = 240,
SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM = 241,
SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242,
SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243,
#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
#define SVGA3D_DEVCAP_DXFMT_DXT1 114
#define SVGA3D_DEVCAP_DXFMT_DXT2 115
#define SVGA3D_DEVCAP_DXFMT_DXT3 116
#define SVGA3D_DEVCAP_DXFMT_DXT4 117
#define SVGA3D_DEVCAP_DXFMT_DXT5 118
#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
#define SVGA3D_DEVCAP_DXFMT_V8U8 126
#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
#define SVGA3D_DEVCAP_DXFMT_V16U16 138
#define SVGA3D_DEVCAP_DXFMT_G16R16 139
#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
#define SVGA3D_DEVCAP_DXFMT_UYVY 141
#define SVGA3D_DEVCAP_DXFMT_YUY2 142
#define SVGA3D_DEVCAP_DXFMT_NV12 143
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
#define SVGA3D_DEVCAP_DXFMT_P8 196
#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
#define SVGA3D_DEVCAP_DXFMT_ATI1 207
#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
#define SVGA3D_DEVCAP_DXFMT_ATI2 210
#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
#define SVGA3D_DEVCAP_DXFMT_YV12 220
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
SVGA3D_DEVCAP_SM41 = 244,
SVGA3D_DEVCAP_MULTISAMPLE_2X = 245,
SVGA3D_DEVCAP_MULTISAMPLE_4X = 246,
SVGA3D_DEVCAP_MS_FULL_QUALITY = 247,
SVGA3D_DEVCAP_LOGICOPS = 248,
SVGA3D_DEVCAP_LOGIC_BLENDOPS = 249,
#define SVGA3D_DEVCAP_SM41 244
#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
SVGA3D_DEVCAP_DEAD12 = 250,
#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS = 251,
SVGA3D_DEVCAP_DXFMT_BC6H_UF16 = 252,
SVGA3D_DEVCAP_DXFMT_BC6H_SF16 = 253,
SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS = 254,
SVGA3D_DEVCAP_DXFMT_BC7_UNORM = 255,
SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB = 256,
SVGA3D_DEVCAP_DEAD13 = 257,
SVGA3D_DEVCAP_SM5 = 258,
SVGA3D_DEVCAP_MULTISAMPLE_8X = 259,
SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT = 260,
SVGA3D_DEVCAP_GL43 = 261,
SVGA3D_DEVCAP_MAX = 262,
#define SVGA3D_DEVCAP_LOGICOPS 248
} SVGA3dDevCapIndex;
#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
/*
* Bit definitions for DXFMT devcaps
*
* See also:
* http://msdn.microsoft.com/en-gb/library/windows/hardware/ff539390.aspx
*
* SUPPORTED: Can the format be defined?
* SHADER_SAMPLE: Can the format be sampled from a shader?
* COLOR_RENDERTARGET: Can the format be a color render target?
* DEPTH_RENDERTARGET: Can the format be a depth render target?
* BLENDABLE: Is the format blendable?
* MIPS: Does the format support mip levels?
* ARRAY: Does the format support texture arrays?
* VOLUME: Does the format support having volume?
* MULTISAMPLE: Does the format support multisample?
*/
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
#define SVGA3D_DXFMT_MIPS (1 << 5)
#define SVGA3D_DXFMT_ARRAY (1 << 6)
#define SVGA3D_DXFMT_VOLUME (1 << 7)
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
#define SVGA3D_DXFMT_MAX (1 << 10)
#define SVGA3D_DEVCAP_DEAD12 250
#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
#define SVGA3D_DEVCAP_DEAD13 257
#define SVGA3D_DEVCAP_SM5 258
#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
#define SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT 260
#define SVGA3D_DEVCAP_GL43 261
#define SVGA3D_DEVCAP_MAX 262
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
#define SVGA3D_DXFMT_MIPS (1 << 5)
#define SVGA3D_DXFMT_ARRAY (1 << 6)
#define SVGA3D_DXFMT_VOLUME (1 << 7)
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
#define SVGA3D_DXFMT_MAX (1 << 10)
typedef union {
SVGA3dBool b;
@@ -466,4 +371,4 @@ typedef union {
float f;
} SVGA3dDevCapResult;
#endif /* _SVGA3D_DEVCAPS_H_ */
#endif
src/gallium/drivers/svga/include/svga3d_dx.h
+736 -1079
View File
File diff suppressed because it is too large Load Diff
src/gallium/drivers/svga/include/svga3d_limits.h
+43 -43
View File
@@ -1,8 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (c) 2012-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0 OR MIT
* Copyright (c) 2012-2021 Broadcom. All Rights Reserved. The term
* "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
/*
@@ -11,70 +31,50 @@
* SVGA 3d hardware limits
*/
#ifndef _SVGA3D_LIMITS_H_
#define _SVGA3D_LIMITS_H_
#define SVGA3D_HB_MAX_CONTEXT_IDS 256
#define SVGA3D_HB_MAX_SURFACE_IDS (32 * 1024)
#define SVGA3D_NUM_CLIPPLANES 6
#define SVGA3D_MAX_CONTEXT_IDS 256
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
#define SVGA3D_MAX_RENDER_TARGETS 8
#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
#define SVGA3D_MAX_UAVIEWS 8
#define SVGA3D_DX11_1_MAX_UAVIEWS 64
#define SVGA3D_DX_MAX_RENDER_TARGETS 8
#define SVGA3D_DX11_MAX_UAVIEWS 8
#define SVGA3D_DX11_1_MAX_UAVIEWS 64
#define SVGA3D_MAX_UAVIEWS (SVGA3D_DX11_1_MAX_UAVIEWS)
#define SVGA3D_DX11_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_MAX_UAVIEWS)
#define SVGA3D_DX11_1_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_1_MAX_UAVIEWS)
#define SVGA3D_MAX_SIMULTANEOUS_RTUAV (SVGA3D_MAX_UAVIEWS)
#define SVGA3D_HB_MAX_SURFACE_SIZE MBYTES_2_BYTES(128)
#define SVGA3D_MAX_SHADERIDS 5000
#define SVGA3D_MAX_SHADERIDS 5000
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
#define SVGA3D_MAX_SHADER_MEMORY_BYTES (8 * 1024 * 1024)
#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
sizeof(uint32))
#define SVGA3D_MAX_SHADER_MEMORY \
(SVGA3D_MAX_SHADER_MEMORY_BYTES / sizeof(uint32))
#define SVGA3D_MAX_SHADER_THREAD_GROUPS 65535
#define SVGA3D_MAX_CLIP_PLANES 6
#define SVGA3D_MAX_CLIP_PLANES 6
#define SVGA3D_MAX_TEXTURE_COORDS 8
#define SVGA3D_MAX_SURFACE_FACES 6
#define SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE 512
#define SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE 2048
#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
#define SVGA3D_MAX_VERTEX_ARRAYS 32
#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
#define SVGA3D_MAX_VERTEX_ARRAYS 32
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
#define SVGA3D_MAX_SAMPLES 8
#endif
src/gallium/drivers/svga/include/svga3d_reg.h
+29 -16
View File
@@ -1,32 +1,45 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (c) 1998-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0 OR MIT
* Copyright (c) 1998-2015 Broadcom. All Rights Reserved. The term
* "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
/*
* svga3d_reg.h --
*
* SVGA 3d hardware definitions
* SVGA 3d hardware definitions
*/
#ifndef _SVGA3D_REG_H_
#define _SVGA3D_REG_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga_reg.h"
#include "svga3d_types.h"
#include "svga3d_limits.h"
#include "svga3d_cmd.h"
#include "svga3d_dx.h"
#include "svga3d_devcaps.h"
#include "svga3d_dx.h"
#include "svga3d_limits.h"
#include "svga3d_types.h"
#endif /* _SVGA3D_REG_H_ */
#endif
src/gallium/drivers/svga/include/svga3d_shaderdefs.h
+226 -274
View File
@@ -1,78 +1,88 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (c) 2007-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0 OR MIT
* Copyright (c) 2007-2020 Broadcom. All Rights Reserved. The term
* "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
/*
* svga3d_shaderdefs.h --
*
* SVGA3D byte code format and limit definitions.
*
* The format of the byte code directly corresponds to that defined
* by Microsoft DirectX SDK 9.0c (file d3d9types.h). The format can
* also be extended so that different shader formats can be supported
* for example GLSL, ARB vp/fp, NV/ATI shader formats, etc.
*
* SVGA3D byte code format and limit definitions.
*/
#ifndef __SVGA3D_SHADER_DEFS__
#define __SVGA3D_SHADER_DEFS__
/* SVGA3D shader hardware limits. */
#include "svga3d_types.h"
#define SVGA3D_INPUTREG_MAX 16
#define SVGA3D_OUTPUTREG_MAX 12
#define SVGA3D_VERTEX_SAMPLERREG_MAX 4
#define SVGA3D_PIXEL_SAMPLERREG_MAX 16
#define SVGA3D_SAMPLERREG_MAX (SVGA3D_PIXEL_SAMPLERREG_MAX+\
SVGA3D_VERTEX_SAMPLERREG_MAX)
#define SVGA3D_TEMPREG_MAX 32
#define SVGA3D_CONSTREG_MAX 256
#define SVGA3D_CONSTINTREG_MAX 16
#define SVGA3D_CONSTBOOLREG_MAX 16
#define SVGA3D_ADDRREG_MAX 1
#define SVGA3D_PREDREG_MAX 1
#if defined __cplusplus
extern "C" {
#endif
/* SVGA3D byte code specific limits */
#define SVGA3D_INPUTREG_MAX 16
#define SVGA3D_OUTPUTREG_MAX 12
#define SVGA3D_VERTEX_SAMPLERREG_MAX 4
#define SVGA3D_PIXEL_SAMPLERREG_MAX 16
#define SVGA3D_SAMPLERREG_MAX \
(SVGA3D_PIXEL_SAMPLERREG_MAX + SVGA3D_VERTEX_SAMPLERREG_MAX)
#define SVGA3D_TEMPREG_MAX 32
#define SVGA3D_ADDRREG_MAX 1
#define SVGA3D_PREDREG_MAX 1
#define SVGA3D_MAX_SRC_REGS 4
#define SVGA3D_MAX_NESTING_LEVEL 32
/* SVGA3D version information. */
#define SVGA3D_VS_TYPE 0xFFFE
#define SVGA3D_PS_TYPE 0xFFFF
#define SVGA3D_VS_TYPE 0xFFFE
#define SVGA3D_PS_TYPE 0xFFFF
typedef struct {
union {
struct {
uint32 minor : 8;
uint32 major : 8;
uint32 type : 16;
uint32 type : 16;
};
uint32 value;
};
} SVGA3dShaderVersion;
#define SVGA3D_VS_10 ((SVGA3D_VS_TYPE << 16) | 1 << 8)
#define SVGA3D_VS_11 (SVGA3D_VS_10 | 1)
#define SVGA3D_VS_20 ((SVGA3D_VS_TYPE << 16) | 2 << 8)
#define SVGA3D_VS_21 (SVGA3D_VS_20 | 1)
#define SVGA3D_VS_30 ((SVGA3D_VS_TYPE << 16) | 3 << 8)
#define SVGA3D_VS_10 ((uint32)((SVGA3D_VS_TYPE << 16) | 1 << 8))
#define SVGA3D_VS_11 ((uint32)(SVGA3D_VS_10 | 1))
#define SVGA3D_VS_20 ((uint32)((SVGA3D_VS_TYPE << 16) | 2 << 8))
#define SVGA3D_VS_21 ((uint32)(SVGA3D_VS_20 | 1))
#define SVGA3D_VS_30 ((uint32)((SVGA3D_VS_TYPE << 16) | 3 << 8))
#define SVGA3D_PS_10 ((SVGA3D_PS_TYPE << 16) | 1 << 8)
#define SVGA3D_PS_11 (SVGA3D_PS_10 | 1)
#define SVGA3D_PS_12 (SVGA3D_PS_10 | 2)
#define SVGA3D_PS_13 (SVGA3D_PS_10 | 3)
#define SVGA3D_PS_14 (SVGA3D_PS_10 | 4)
#define SVGA3D_PS_20 ((SVGA3D_PS_TYPE << 16) | 2 << 8)
#define SVGA3D_PS_21 (SVGA3D_PS_20 | 1)
#define SVGA3D_PS_30 ((SVGA3D_PS_TYPE << 16) | 3 << 8)
#define SVGA3D_PS_10 ((uint32)((SVGA3D_PS_TYPE << 16) | 1 << 8))
#define SVGA3D_PS_11 ((uint32)(SVGA3D_PS_10 | 1))
#define SVGA3D_PS_12 ((uint32)(SVGA3D_PS_10 | 2))
#define SVGA3D_PS_13 ((uint32)(SVGA3D_PS_10 | 3))
#define SVGA3D_PS_14 ((uint32)(SVGA3D_PS_10 | 4))
#define SVGA3D_PS_20 ((uint32)((SVGA3D_PS_TYPE << 16) | 2 << 8))
#define SVGA3D_PS_21 ((uint32)(SVGA3D_PS_20 | 1))
#define SVGA3D_PS_30 ((uint32)((SVGA3D_PS_TYPE << 16) | 3 << 8))
/* The *_ENABLED are for backwards compatibility with old drivers */
typedef enum {
SVGA3DPSVERSION_NONE = 0,
SVGA3DPSVERSION_ENABLED = 1,
@@ -96,90 +106,89 @@ typedef enum {
SVGA3DVSVERSION_MAX
} SVGA3dVertexShaderVersion;
/* SVGA3D instruction op codes. */
typedef enum {
SVGA3DOP_NOP = 0,
SVGA3DOP_MOV,
SVGA3DOP_ADD,
SVGA3DOP_SUB,
SVGA3DOP_MAD,
SVGA3DOP_MUL,
SVGA3DOP_RCP,
SVGA3DOP_RSQ,
SVGA3DOP_DP3,
SVGA3DOP_DP4,
SVGA3DOP_MIN,
SVGA3DOP_MAX,
SVGA3DOP_SLT,
SVGA3DOP_SGE,
SVGA3DOP_EXP,
SVGA3DOP_LOG,
SVGA3DOP_LIT,
SVGA3DOP_DST,
SVGA3DOP_LRP,
SVGA3DOP_FRC,
SVGA3DOP_M4x4,
SVGA3DOP_M4x3,
SVGA3DOP_M3x4,
SVGA3DOP_M3x3,
SVGA3DOP_M3x2,
SVGA3DOP_CALL,
SVGA3DOP_CALLNZ,
SVGA3DOP_LOOP,
SVGA3DOP_RET,
SVGA3DOP_ENDLOOP,
SVGA3DOP_LABEL,
SVGA3DOP_DCL,
SVGA3DOP_POW,
SVGA3DOP_CRS,
SVGA3DOP_SGN,
SVGA3DOP_ABS,
SVGA3DOP_NRM,
SVGA3DOP_SINCOS,
SVGA3DOP_REP,
SVGA3DOP_ENDREP,
SVGA3DOP_IF,
SVGA3DOP_IFC,
SVGA3DOP_ELSE,
SVGA3DOP_ENDIF,
SVGA3DOP_BREAK,
SVGA3DOP_BREAKC,
SVGA3DOP_MOVA,
SVGA3DOP_DEFB,
SVGA3DOP_DEFI,
SVGA3DOP_MOV = 1,
SVGA3DOP_ADD = 2,
SVGA3DOP_SUB = 3,
SVGA3DOP_MAD = 4,
SVGA3DOP_MUL = 5,
SVGA3DOP_RCP = 6,
SVGA3DOP_RSQ = 7,
SVGA3DOP_DP3 = 8,
SVGA3DOP_DP4 = 9,
SVGA3DOP_MIN = 10,
SVGA3DOP_MAX = 11,
SVGA3DOP_SLT = 12,
SVGA3DOP_SGE = 13,
SVGA3DOP_EXP = 14,
SVGA3DOP_LOG = 15,
SVGA3DOP_LIT = 16,
SVGA3DOP_DST = 17,
SVGA3DOP_LRP = 18,
SVGA3DOP_FRC = 19,
SVGA3DOP_M4x4 = 20,
SVGA3DOP_M4x3 = 21,
SVGA3DOP_M3x4 = 22,
SVGA3DOP_M3x3 = 23,
SVGA3DOP_M3x2 = 24,
SVGA3DOP_CALL = 25,
SVGA3DOP_CALLNZ = 26,
SVGA3DOP_LOOP = 27,
SVGA3DOP_RET = 28,
SVGA3DOP_ENDLOOP = 29,
SVGA3DOP_LABEL = 30,
SVGA3DOP_DCL = 31,
SVGA3DOP_POW = 32,
SVGA3DOP_CRS = 33,
SVGA3DOP_SGN = 34,
SVGA3DOP_ABS = 35,
SVGA3DOP_NRM = 36,
SVGA3DOP_SINCOS = 37,
SVGA3DOP_REP = 38,
SVGA3DOP_ENDREP = 39,
SVGA3DOP_IF = 40,
SVGA3DOP_IFC = 41,
SVGA3DOP_ELSE = 42,
SVGA3DOP_ENDIF = 43,
SVGA3DOP_BREAK = 44,
SVGA3DOP_BREAKC = 45,
SVGA3DOP_MOVA = 46,
SVGA3DOP_DEFB = 47,
SVGA3DOP_DEFI = 48,
SVGA3DOP_TEXCOORD = 64,
SVGA3DOP_TEXKILL,
SVGA3DOP_TEX,
SVGA3DOP_TEXBEM,
SVGA3DOP_TEXBEML,
SVGA3DOP_TEXREG2AR,
SVGA3DOP_TEXKILL = 65,
SVGA3DOP_TEX = 66,
SVGA3DOP_TEXBEM = 67,
SVGA3DOP_TEXBEML = 68,
SVGA3DOP_TEXREG2AR = 69,
SVGA3DOP_TEXREG2GB = 70,
SVGA3DOP_TEXM3x2PAD,
SVGA3DOP_TEXM3x2TEX,
SVGA3DOP_TEXM3x3PAD,
SVGA3DOP_TEXM3x3TEX,
SVGA3DOP_RESERVED0,
SVGA3DOP_TEXM3x3SPEC,
SVGA3DOP_TEXM3x3VSPEC,
SVGA3DOP_EXPP,
SVGA3DOP_LOGP,
SVGA3DOP_TEXM3x2PAD = 71,
SVGA3DOP_TEXM3x2TEX = 72,
SVGA3DOP_TEXM3x3PAD = 73,
SVGA3DOP_TEXM3x3TEX = 74,
SVGA3DOP_RESERVED0 = 75,
SVGA3DOP_TEXM3x3SPEC = 76,
SVGA3DOP_TEXM3x3VSPEC = 77,
SVGA3DOP_EXPP = 78,
SVGA3DOP_LOGP = 79,
SVGA3DOP_CND = 80,
SVGA3DOP_DEF,
SVGA3DOP_TEXREG2RGB,
SVGA3DOP_TEXDP3TEX,
SVGA3DOP_TEXM3x2DEPTH,
SVGA3DOP_TEXDP3,
SVGA3DOP_TEXM3x3,
SVGA3DOP_TEXDEPTH,
SVGA3DOP_CMP,
SVGA3DOP_BEM,
SVGA3DOP_DEF = 81,
SVGA3DOP_TEXREG2RGB = 82,
SVGA3DOP_TEXDP3TEX = 83,
SVGA3DOP_TEXM3x2DEPTH = 84,
SVGA3DOP_TEXDP3 = 85,
SVGA3DOP_TEXM3x3 = 86,
SVGA3DOP_TEXDEPTH = 87,
SVGA3DOP_CMP = 88,
SVGA3DOP_BEM = 89,
SVGA3DOP_DP2ADD = 90,
SVGA3DOP_DSX,
SVGA3DOP_DSY,
SVGA3DOP_TEXLDD,
SVGA3DOP_SETP,
SVGA3DOP_TEXLDL,
SVGA3DOP_DSX = 91,
SVGA3DOP_DSY = 92,
SVGA3DOP_TEXLDD = 93,
SVGA3DOP_SETP = 94,
SVGA3DOP_TEXLDL = 95,
SVGA3DOP_BREAKP = 96,
SVGA3DOP_LAST_INST,
SVGA3DOP_PHASE = 0xFFFD,
@@ -187,12 +196,10 @@ typedef enum {
SVGA3DOP_END = 0xFFFF,
} SVGA3dShaderOpCodeType;
/* SVGA3D operation control/comparison function types */
typedef enum {
SVGA3DOPCONT_NONE,
SVGA3DOPCONT_PROJECT, /* Projective texturing */
SVGA3DOPCONT_BIAS, /* Texturing with a LOD bias */
SVGA3DOPCONT_PROJECT,
SVGA3DOPCONT_BIAS,
} SVGA3dShaderOpCodeControlFnType;
typedef enum {
@@ -201,103 +208,78 @@ typedef enum {
SVGA3DOPCOMP_EQ,
SVGA3DOPCOMP_GE,
SVGA3DOPCOMP_LT,
SVGA3DOPCOMPC_NE,
SVGA3DOPCOMP_NE,
SVGA3DOPCOMP_LE,
SVGA3DOPCOMP_RESERVED1
} SVGA3dShaderOpCodeCompFnType;
/* SVGA3D register types */
typedef enum {
SVGA3DREG_TEMP = 0, /* Temporary register file */
SVGA3DREG_INPUT, /* Input register file */
SVGA3DREG_CONST, /* Constant register file */
SVGA3DREG_ADDR, /* Address register for VS */
SVGA3DREG_TEXTURE = 3, /* Texture register file for PS */
SVGA3DREG_RASTOUT, /* Rasterizer register file */
SVGA3DREG_ATTROUT, /* Attribute output register file */
SVGA3DREG_TEXCRDOUT, /* Texture coordinate output register file */
SVGA3DREG_OUTPUT = 6, /* Output register file for VS 3.0+ */
SVGA3DREG_CONSTINT, /* Constant integer vector register file */
SVGA3DREG_COLOROUT, /* Color output register file */
SVGA3DREG_DEPTHOUT, /* Depth output register file */
SVGA3DREG_SAMPLER, /* Sampler state register file */
SVGA3DREG_CONST2, /* Constant register file 2048 - 4095 */
SVGA3DREG_CONST3, /* Constant register file 4096 - 6143 */
SVGA3DREG_CONST4, /* Constant register file 6144 - 8191 */
SVGA3DREG_CONSTBOOL, /* Constant boolean register file */
SVGA3DREG_LOOP, /* Loop counter register file */
SVGA3DREG_TEMPFLOAT16, /* 16-bit float temp register file */
SVGA3DREG_MISCTYPE, /* Miscellaneous (single) registers */
SVGA3DREG_LABEL, /* Label */
SVGA3DREG_PREDICATE, /* Predicate register */
SVGA3DREG_TEMP = 0,
SVGA3DREG_INPUT,
SVGA3DREG_CONST,
SVGA3DREG_ADDR,
SVGA3DREG_TEXTURE = 3,
SVGA3DREG_RASTOUT,
SVGA3DREG_ATTROUT,
SVGA3DREG_TEXCRDOUT,
SVGA3DREG_OUTPUT = 6,
SVGA3DREG_CONSTINT,
SVGA3DREG_COLOROUT,
SVGA3DREG_DEPTHOUT,
SVGA3DREG_SAMPLER,
SVGA3DREG_CONST2,
SVGA3DREG_CONST3,
SVGA3DREG_CONST4,
SVGA3DREG_CONSTBOOL,
SVGA3DREG_LOOP,
SVGA3DREG_TEMPFLOAT16,
SVGA3DREG_MISCTYPE,
SVGA3DREG_LABEL,
SVGA3DREG_PREDICATE,
} SVGA3dShaderRegType;
/* SVGA3D rasterizer output register types */
typedef enum {
SVGA3DRASTOUT_POSITION = 0,
SVGA3DRASTOUT_FOG,
SVGA3DRASTOUT_PSIZE
} SVGA3dShaderRastOutRegType;
/* SVGA3D miscellaneous register types */
typedef enum {
SVGA3DMISCREG_POSITION = 0, /* Input position x,y,z,rhw (PS) */
SVGA3DMISCREG_FACE /* Floating point primitive area (PS) */
SVGA3DMISCREG_POSITION = 0,
SVGA3DMISCREG_FACE
} SVGA3DShaderMiscRegType;
/* SVGA3D sampler types */
typedef enum {
SVGA3DSAMP_UNKNOWN = 0, /* Uninitialized value */
SVGA3DSAMP_2D = 2, /* dcl_2d s# (for declaring a 2D texture) */
SVGA3DSAMP_CUBE, /* dcl_cube s# (for declaring a cube texture) */
SVGA3DSAMP_VOLUME, /* dcl_volume s# (for declaring a volume texture) */
SVGA3DSAMP_2D_SHADOW, /* dcl_2d s# (for declaring a 2D shadow texture) */
SVGA3DSAMP_UNKNOWN = 0,
SVGA3DSAMP_2D = 2,
SVGA3DSAMP_CUBE,
SVGA3DSAMP_VOLUME,
SVGA3DSAMP_2D_SHADOW,
SVGA3DSAMP_MAX,
} SVGA3dShaderSamplerType;
/* SVGA3D write mask */
#define SVGA3DWRITEMASK_0 1
#define SVGA3DWRITEMASK_1 2
#define SVGA3DWRITEMASK_2 4
#define SVGA3DWRITEMASK_3 8
#define SVGA3DWRITEMASK_ALL 15
#define SVGA3DWRITEMASK_0 1 /* Component 0 (X;Red) */
#define SVGA3DWRITEMASK_1 2 /* Component 1 (Y;Green) */
#define SVGA3DWRITEMASK_2 4 /* Component 2 (Z;Blue) */
#define SVGA3DWRITEMASK_3 8 /* Component 3 (W;Alpha) */
#define SVGA3DWRITEMASK_ALL 15 /* All components */
#define SVGA3DDSTMOD_NONE 0
#define SVGA3DDSTMOD_SATURATE 1
#define SVGA3DDSTMOD_PARTIALPRECISION 2
/* SVGA3D destination modifiers */
#define SVGA3DDSTMOD_NONE 0 /* nop */
#define SVGA3DDSTMOD_SATURATE 1 /* clamp to [0, 1] */
#define SVGA3DDSTMOD_PARTIALPRECISION 2 /* Partial precision hint */
/*
* Relevant to multisampling only:
* When the pixel center is not covered, sample
* attribute or compute gradients/LOD
* using multisample "centroid" location.
* "Centroid" is some location within the covered
* region of the pixel.
*/
#define SVGA3DDSTMOD_MSAMPCENTROID 4
/* SVGA3D destination shift scale */
#define SVGA3DDSTMOD_MSAMPCENTROID 4
typedef enum {
SVGA3DDSTSHFSCALE_X1 = 0, /* 1.0 */
SVGA3DDSTSHFSCALE_X2 = 1, /* 2.0 */
SVGA3DDSTSHFSCALE_X4 = 2, /* 4.0 */
SVGA3DDSTSHFSCALE_X8 = 3, /* 8.0 */
SVGA3DDSTSHFSCALE_D8 = 13, /* 0.125 */
SVGA3DDSTSHFSCALE_D4 = 14, /* 0.25 */
SVGA3DDSTSHFSCALE_D2 = 15 /* 0.5 */
SVGA3DDSTSHFSCALE_X1 = 0,
SVGA3DDSTSHFSCALE_X2 = 1,
SVGA3DDSTSHFSCALE_X4 = 2,
SVGA3DDSTSHFSCALE_X8 = 3,
SVGA3DDSTSHFSCALE_D8 = 13,
SVGA3DDSTSHFSCALE_D4 = 14,
SVGA3DDSTSHFSCALE_D2 = 15
} SVGA3dShaderDstShfScaleType;
/* SVGA3D source swizzle */
#define SVGA3DSWIZZLE_REPLICATEX 0x00
#define SVGA3DSWIZZLE_REPLICATEY 0x55
#define SVGA3DSWIZZLE_REPLICATEZ 0xAA
@@ -307,106 +289,96 @@ typedef enum {
#define SVGA3DSWIZZLE_ZXYW 0xD2
#define SVGA3DSWIZZLE_WXYZ 0x1B
/* SVGA3D source modifiers */
typedef enum {
SVGA3DSRCMOD_NONE = 0, /* nop */
SVGA3DSRCMOD_NEG, /* negate */
SVGA3DSRCMOD_BIAS, /* bias */
SVGA3DSRCMOD_BIASNEG, /* bias and negate */
SVGA3DSRCMOD_SIGN, /* sign */
SVGA3DSRCMOD_SIGNNEG, /* sign and negate */
SVGA3DSRCMOD_COMP, /* complement */
SVGA3DSRCMOD_X2, /* x2 */
SVGA3DSRCMOD_X2NEG, /* x2 and negate */
SVGA3DSRCMOD_DZ, /* divide through by z component */
SVGA3DSRCMOD_DW, /* divide through by w component */
SVGA3DSRCMOD_ABS, /* abs() */
SVGA3DSRCMOD_ABSNEG, /* -abs() */
SVGA3DSRCMOD_NOT, /* ! (for predicate register) */
SVGA3DSRCMOD_NONE = 0,
SVGA3DSRCMOD_NEG,
SVGA3DSRCMOD_BIAS,
SVGA3DSRCMOD_BIASNEG,
SVGA3DSRCMOD_SIGN,
SVGA3DSRCMOD_SIGNNEG,
SVGA3DSRCMOD_COMP,
SVGA3DSRCMOD_X2,
SVGA3DSRCMOD_X2NEG,
SVGA3DSRCMOD_DZ,
SVGA3DSRCMOD_DW,
SVGA3DSRCMOD_ABS,
SVGA3DSRCMOD_ABSNEG,
SVGA3DSRCMOD_NOT,
} SVGA3dShaderSrcModType;
/* SVGA3D instruction token */
typedef struct {
union {
struct {
uint32 comment_op : 16;
uint32 comment_op : 16;
uint32 comment_size : 16;
};
struct {
uint32 op : 16;
uint32 control : 3;
uint32 reserved2 : 5;
uint32 size : 4;
uint32 op : 16;
uint32 control : 3;
uint32 reserved2 : 5;
uint32 size : 4;
uint32 predicated : 1;
uint32 reserved1 : 1;
uint32 coissue : 1;
uint32 reserved0 : 1;
uint32 reserved1 : 1;
uint32 coissue : 1;
uint32 reserved0 : 1;
};
uint32 value;
};
} SVGA3dShaderInstToken;
/* SVGA3D destination parameter token */
typedef struct {
union {
struct {
uint32 num : 11;
uint32 num : 11;
uint32 type_upper : 2;
uint32 relAddr : 1;
uint32 reserved1 : 2;
uint32 mask : 4;
uint32 dstMod : 4;
uint32 shfScale : 4;
uint32 relAddr : 1;
uint32 reserved1 : 2;
uint32 mask : 4;
uint32 dstMod : 4;
uint32 shfScale : 4;
uint32 type_lower : 3;
uint32 reserved0 : 1;
uint32 reserved0 : 1;
};
uint32 value;
};
} SVGA3dShaderDestToken;
/* SVGA3D source parameter token */
typedef struct {
union {
struct {
uint32 num : 11;
uint32 num : 11;
uint32 type_upper : 2;
uint32 relAddr : 1;
uint32 reserved1 : 2;
uint32 swizzle : 8;
uint32 srcMod : 4;
uint32 relAddr : 1;
uint32 reserved1 : 2;
uint32 swizzle : 8;
uint32 srcMod : 4;
uint32 type_lower : 3;
uint32 reserved0 : 1;
uint32 reserved0 : 1;
};
uint32 value;
};
} SVGA3dShaderSrcToken;
/* SVGA3DOP_DCL parameter tokens */
typedef struct {
union {
struct {
union {
struct {
uint32 usage : 5;
uint32 usage : 5;
uint32 reserved1 : 11;
uint32 index : 4;
uint32 index : 4;
uint32 reserved0 : 12;
}; /* input / output declaration */
};
struct {
uint32 reserved3 : 27;
uint32 type : 4;
uint32 type : 4;
uint32 reserved2 : 1;
}; /* sampler declaration */
};
};
SVGA3dShaderDestToken dst;
@@ -416,8 +388,6 @@ typedef struct {
};
} SVGA3DOpDclArgs;
/* SVGA3DOP_DEF parameter tokens */
typedef struct {
union {
struct {
@@ -434,8 +404,6 @@ typedef struct {
};
} SVGA3DOpDefArgs;
/* SVGA3D shader token */
typedef union {
uint32 value;
SVGA3dShaderInstToken inst;
@@ -443,14 +411,10 @@ typedef union {
SVGA3dShaderSrcToken src;
} SVGA3dShaderToken;
/* SVGA3D shader program */
typedef struct {
SVGA3dShaderVersion version;
/* SVGA3dShaderToken stream */
} SVGA3dShaderProgram;
/* SVGA3D version specific register assignments */
} SVGA3dShaderProgram;
static const uint32 SVGA3D_INPUT_REG_POSITION_VS11 = 0;
static const uint32 SVGA3D_INPUT_REG_PSIZE_VS11 = 1;
@@ -473,23 +437,7 @@ static const uint32 SVGA3D_OUTPUT_REG_COLOR_NUM_PS20 = 4;
static const uint32 SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20 = 0;
static const uint32 SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20 = 1;
/*
*----------------------------------------------------------------------
*
* SVGA3dShaderGetRegType --
*
* As the register type is split into two non sequential fields,
* this function provides an useful way of accessing the actual
* register type without having to manually concatenate the
* type_upper and type_lower fields.
*
* Results:
* Returns the register type.
*
*----------------------------------------------------------------------
*/
static inline SVGA3dShaderRegType
static INLINE SVGA3dShaderRegType
SVGA3dShaderGetRegType(uint32 token)
{
SVGA3dShaderSrcToken src;
@@ -497,4 +445,8 @@ SVGA3dShaderGetRegType(uint32 token)
return (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
}
#endif /* __SVGA3D_SHADER_DEFS__ */
#if defined __cplusplus
}
#endif
#endif
src/gallium/drivers/svga/include/svga3d_surfacedefs.h
+1305 -1339
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File diff suppressed because it is too large Load Diff
src/gallium/drivers/svga/include/svga3d_types.h
+1065 -1364
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File diff suppressed because it is too large Load Diff
src/gallium/drivers/svga/include/svga_escape.h
+31 -47
View File
@@ -1,8 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (c) 2007-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0 OR MIT
* Copyright (c) 2007,2020 Broadcom. All Rights Reserved. The term
* "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
/*
@@ -14,58 +34,22 @@
#ifndef _SVGA_ESCAPE_H_
#define _SVGA_ESCAPE_H_
/*
* Namespace IDs for the escape command
*/
#define SVGA_ESCAPE_NSID_VMWARE 0x00000000
#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
/*
* Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to
* the first DWORD of escape data (after the nsID and size). As a
* guideline we're using the high word and low word as a major and
* minor command number, respectively.
*
* Major command number allocation:
*
* 0000: Reserved
* 0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h)
* 0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h)
* 0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h)
*/
#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001
#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
/*
* SVGA Hint commands.
*
* These escapes let the SVGA driver provide optional information to
* he host about the state of the guest or guest applications. The
* host can use these hints to make user interface or performance
* decisions.
*
* Notes:
*
* - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests
* that use the SVGA Screen Object extension. Instead of sending
* this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your
* Screen Object.
*/
#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 /* Deprecated */
typedef
struct {
#pragma pack(push, 1)
typedef struct {
uint32 command;
uint32 fullscreen;
struct {
int32 x, y;
} monitorPosition;
} SVGAEscapeHintFullscreen;
#pragma pack(pop)
#endif /* _SVGA_ESCAPE_H_ */
#endif
src/gallium/drivers/svga/include/svga_overlay.h
+51 -116
View File
@@ -1,8 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (c) 2007-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0 OR MIT
* Copyright (c) 2007-2021 Broadcom. All Rights Reserved. The term
* "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
/*
@@ -16,13 +36,13 @@
#include "svga_reg.h"
/*
* Video formats we support
*/
#if defined __cplusplus
extern "C" {
#endif
#define VMWARE_FOURCC_YV12 0x32315659 /* 'Y' 'V' '1' '2' */
#define VMWARE_FOURCC_YUY2 0x32595559 /* 'Y' 'U' 'Y' '2' */
#define VMWARE_FOURCC_UYVY 0x59565955 /* 'U' 'Y' 'V' 'Y' */
#define VMWARE_FOURCC_YV12 0x32315659
#define VMWARE_FOURCC_YUY2 0x32595559
#define VMWARE_FOURCC_UYVY 0x59565955
typedef enum {
SVGA_OVERLAY_FORMAT_INVALID = 0,
@@ -31,151 +51,66 @@ typedef enum {
SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
} SVGAOverlayFormat;
#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
/* FIFO escape layout:
* Type, Stream Id, (Register Id, Value) pairs */
#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
/* FIFO escape layout:
* Type, Stream Id */
#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
typedef
struct SVGAEscapeVideoSetRegs {
typedef struct SVGAEscapeVideoSetRegs {
struct {
uint32 cmdType;
uint32 streamId;
} header;
/* May include zero or more items. */
struct {
uint32 registerId;
uint32 value;
} items[1];
} SVGAEscapeVideoSetRegs;
typedef
struct SVGAEscapeVideoFlush {
typedef struct SVGAEscapeVideoFlush {
uint32 cmdType;
uint32 streamId;
} SVGAEscapeVideoFlush;
/*
* Struct definitions for the video overlay commands built on
* SVGAFifoCmdEscape.
*/
typedef
struct {
#pragma pack(push, 1)
typedef struct {
uint32 command;
uint32 overlay;
} SVGAFifoEscapeCmdVideoBase;
#pragma pack(pop)
typedef
struct {
#pragma pack(push, 1)
typedef struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
} SVGAFifoEscapeCmdVideoFlush;
#pragma pack(pop)
typedef
struct {
#pragma pack(push, 1)
typedef struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[1];
} SVGAFifoEscapeCmdVideoSetRegs;
#pragma pack(pop)
typedef
struct {
#pragma pack(push, 1)
typedef struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[SVGA_VIDEO_NUM_REGS];
} SVGAFifoEscapeCmdVideoSetAllRegs;
#pragma pack(pop)
/*
*----------------------------------------------------------------------
*
* VMwareVideoGetAttributes --
*
* Computes the size, pitches and offsets for YUV frames.
*
* Results:
* TRUE on success; otherwise FALSE on failure.
*
* Side effects:
* Pitches and offsets for the given YUV frame are put in 'pitches'
* and 'offsets' respectively. They are both optional though.
*
*----------------------------------------------------------------------
*/
static inline Bool
VMwareVideoGetAttributes(const SVGAOverlayFormat format, /* IN */
uint32 *width, /* IN / OUT */
uint32 *height, /* IN / OUT */
uint32 *size, /* OUT */
uint32 *pitches, /* OUT (optional) */
uint32 *offsets) /* OUT (optional) */
{
int tmp;
*width = (*width + 1) & ~1;
if (offsets) {
offsets[0] = 0;
}
switch (format) {
case VMWARE_FOURCC_YV12:
*height = (*height + 1) & ~1;
*size = (*width) * (*height);
if (pitches) {
pitches[0] = *width;
}
if (offsets) {
offsets[1] = *size;
}
tmp = *width >> 1;
if (pitches) {
pitches[1] = pitches[2] = tmp;
}
tmp *= (*height >> 1);
*size += tmp;
if (offsets) {
offsets[2] = *size;
}
*size += tmp;
break;
case VMWARE_FOURCC_YUY2:
case VMWARE_FOURCC_UYVY:
*size = *width * 2;
if (pitches) {
pitches[0] = *size;
}
*size *= *height;
break;
default:
return false;
}
return true;
#if defined __cplusplus
}
#endif
#endif /* _SVGA_OVERLAY_H_ */
#endif
src/gallium/drivers/svga/include/svga_reg.h
+556 -1526
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File diff suppressed because it is too large Load Diff
src/gallium/drivers/svga/include/svga_types.h
-39
View File
@@ -1,39 +0,0 @@
/*
* Copyright (c) 1998-2024 Broadcom. All Rights Reserved.
* The term “Broadcom” refers to Broadcom Inc.
* and/or its subsidiaries.
* SPDX-License-Identifier: GPL-2.0 OR MIT
*/
#ifndef _SVGA_TYPES_H_
#define _SVGA_TYPES_H_
#include "util/compiler.h"
#ifndef __HAIKU__
typedef int64_t int64;
typedef uint64_t uint64;
typedef int32_t int32;
typedef uint32_t uint32;
typedef int16_t int16;
typedef uint16_t uint16;
typedef int8_t int8;
typedef uint8_t uint8;
#else
#include <OS.h>
#endif /* HAIKU */
typedef uint8_t Bool;
typedef uint64 PA;
typedef uint32 PPN;
typedef uint64 PPN64;
#undef MAX_UINT32
#define MAX_UINT32 0xffffffffU
#endif /* _SVGA_TYPES_H_ */
src/gallium/drivers/svga/include/vm_basic_types.h
+44
View File
@@ -0,0 +1,44 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
*
* Copyright (c) 2024 Broadcom.
* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
**********************************************************/
#ifndef VM_BASIC_TYPES_H
#define VM_BASIC_TYPES_H
#include <stdbool.h>
#include <stdint.h>
typedef uint32_t uint32;
typedef int32_t int32;
typedef uint64_t uint64;
typedef uint16_t uint16;
typedef int16_t int16;
typedef uint8_t uint8;
typedef int8_t int8;
typedef uint64 PA;
typedef uint32 PPN;
typedef uint32 PPN32;
typedef uint64 PPN64;
typedef bool Bool;
#define MAX_UINT64 UINT64_MAX
#define MAX_UINT32 UINT32_MAX
#define MAX_UINT16 UINT16_MAX
#define CONST64U(x) x##ULL
#ifndef MBYTES_SHIFT
#define MBYTES_SHIFT 20
#endif
#ifndef MBYTES_2_BYTES
#define MBYTES_2_BYTES(_nbytes) ((uint64)(_nbytes) << MBYTES_SHIFT)
#endif
#define INLINE inline
#endif
src/gallium/drivers/svga/include/vmw_surf_defs.h
+196
View File
@@ -0,0 +1,196 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
*
* Copyright (c) 2024 Broadcom.
* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
**********************************************************/
#ifndef VMW_SURF_DEFS_H
#define VMW_SURF_DEFS_H
#include "util/macros.h"
#include "svga3d_surfacedefs.h"
#include "svga3d_types.h"
static inline uint32
clamped_umul32(uint32 a, uint32 b)
{
uint64_t tmp = (uint64_t)a * b;
return (tmp > (uint64_t)((uint32)-1)) ? (uint32)-1 : tmp;
}
static inline uint32
clamped_uadd32(uint32 a, uint32 b)
{
uint32 c = a + b;
if (c < a || c < b) {
return MAX_UINT32;
}
return c;
}
static inline const struct SVGA3dSurfaceDesc *
vmw_surf_get_desc(SVGA3dSurfaceFormat format)
{
if (format < ARRAY_SIZE(g_SVGA3dSurfaceDescs))
return &g_SVGA3dSurfaceDescs[format];
return &g_SVGA3dSurfaceDescs[SVGA3D_FORMAT_INVALID];
}
static inline SVGA3dSize
vmw_surf_get_mip_size(SVGA3dSize base_level, uint32 mip_level)
{
SVGA3dSize size;
size.width = MAX2(base_level.width >> mip_level, 1);
size.height = MAX2(base_level.height >> mip_level, 1);
size.depth = MAX2(base_level.depth >> mip_level, 1);
return size;
}
static inline void
vmw_surf_get_size_in_blocks(const struct SVGA3dSurfaceDesc *desc,
const SVGA3dSize *pixel_size,
SVGA3dSize *block_size)
{
block_size->width = DIV_ROUND_UP(pixel_size->width, desc->blockSize.width);
block_size->height =
DIV_ROUND_UP(pixel_size->height, desc->blockSize.height);
block_size->depth = DIV_ROUND_UP(pixel_size->depth, desc->blockSize.depth);
}
static inline bool
vmw_surf_is_planar_surface(const struct SVGA3dSurfaceDesc *desc)
{
return (desc->blockDesc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
}
static inline uint32
vmw_surf_calculate_pitch(const struct SVGA3dSurfaceDesc *desc,
const SVGA3dSize *size)
{
uint32 pitch;
SVGA3dSize blocks;
vmw_surf_get_size_in_blocks(desc, size, &blocks);
pitch = blocks.width * desc->pitchBytesPerBlock;
return pitch;
}
static inline uint32
vmw_surf_get_image_buffer_size(const struct SVGA3dSurfaceDesc *desc,
const SVGA3dSize *size, uint32 pitch)
{
SVGA3dSize image_blocks;
uint32 slice_size, total_size;
vmw_surf_get_size_in_blocks(desc, size, &image_blocks);
if (vmw_surf_is_planar_surface(desc)) {
total_size = clamped_umul32(image_blocks.width, image_blocks.height);
total_size = clamped_umul32(total_size, image_blocks.depth);
total_size = clamped_umul32(total_size, desc->bytesPerBlock);
return total_size;
}
if (pitch == 0)
pitch = vmw_surf_calculate_pitch(desc, size);
slice_size = clamped_umul32(image_blocks.height, pitch);
total_size = clamped_umul32(slice_size, image_blocks.depth);
return total_size;
}
static inline uint32
vmw_surf_get_serialized_size(SVGA3dSurfaceFormat format,
SVGA3dSize base_level_size, uint32 num_mip_levels,
uint32 num_layers)
{
const struct SVGA3dSurfaceDesc *desc = vmw_surf_get_desc(format);
uint64_t total_size = 0;
uint32 mip;
for (mip = 0; mip < num_mip_levels; mip++) {
SVGA3dSize size = vmw_surf_get_mip_size(base_level_size, mip);
total_size += vmw_surf_get_image_buffer_size(desc, &size, 0);
}
total_size *= num_layers;
return (total_size > (uint64_t)MAX_UINT32) ? MAX_UINT32 : (uint32)total_size;
}
/**
* vmw_surf_get_serialized_size_extended - Returns the number of bytes
* required for a surface with given parameters. Support for sample count.
*
*/
static inline uint32
vmw_surf_get_serialized_size_extended(SVGA3dSurfaceFormat format,
SVGA3dSize base_level_size,
uint32 num_mip_levels, uint32 num_layers,
uint32 num_samples)
{
uint64_t total_size = vmw_surf_get_serialized_size(
format, base_level_size, num_mip_levels, num_layers);
total_size *= (num_samples > 1 ? num_samples : 1);
return (total_size > (uint64_t)MAX_UINT32) ? MAX_UINT32 : (uint32)total_size;
}
static inline uint32
vmw_surf_get_image_offset(SVGA3dSurfaceFormat format, SVGA3dSize baseLevelSize,
uint32 numMipLevels, uint32 layer, uint32 mip)
{
uint32 offset;
uint32 mipChainBytes;
uint32 mipChainBytesToLevel;
uint32 i;
const struct SVGA3dSurfaceDesc *desc;
SVGA3dSize mipSize;
uint32 bytes;
desc = vmw_surf_get_desc(format);
mipChainBytes = 0;
mipChainBytesToLevel = 0;
for (i = 0; i < numMipLevels; i++) {
mipSize = vmw_surf_get_mip_size(baseLevelSize, i);
bytes = vmw_surf_get_image_buffer_size(desc, &mipSize, 0);
mipChainBytes += bytes;
if (i < mip) {
mipChainBytesToLevel += bytes;
}
}
offset = mipChainBytes * layer + mipChainBytesToLevel;
return offset;
}
/**
* Compute the offset (in bytes) to a pixel in an image (or volume).
* 'width' is the image width in pixels
* 'height' is the image height in pixels
*/
static inline uint32
vmw_surf_get_pixel_offset(SVGA3dSurfaceFormat format, uint32 width,
uint32 height, uint32 x, uint32 y, uint32 z)
{
const struct SVGA3dSurfaceDesc *desc = vmw_surf_get_desc(format);
const uint32 bw = desc->blockSize.width, bh = desc->blockSize.height;
const uint32 bd = desc->blockSize.depth;
const uint32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytesPerBlock;
const uint32 imgstride = DIV_ROUND_UP(height, bh) * rowstride;
const uint32 offset =
(z / bd * imgstride + y / bh * rowstride + x / bw * desc->bytesPerBlock);
return offset;
}
#endif /* VMW_SURF_DEFS_H */
src/gallium/drivers/svga/include/vmware_pack_begin.h
-1
View File
@@ -1 +0,0 @@
/* dummy file */
src/gallium/drivers/svga/include/vmware_pack_end.h
-1
View File
@@ -1 +0,0 @@
/* dummy file */
src/gallium/drivers/svga/svga_cmd.h
-1
View File
@@ -16,7 +16,6 @@
#define __SVGA3D_H__
#include "svga_types.h"
#include "svga_winsys.h"
#include "svga_reg.h"
#include "svga3d_reg.h"
src/gallium/drivers/svga/svga_cmd_vgpu10.c
+1 -1
View File
@@ -872,7 +872,7 @@ SVGA3D_vgpu10_DefineBlendState(struct svga_winsys_context *swc,
SVGA3D_CREATE_COMMAND(DefineBlendState, DEFINE_BLEND_STATE);
for (i = 0; i < SVGA3D_MAX_RENDER_TARGETS; i++) {
for (i = 0; i < SVGA3D_DX_MAX_RENDER_TARGETS; i++) {
/* At most, one of blend or logicop can be enabled */
assert(perRT[i].blendEnable == 0 || perRT[i].logicOpEnable == 0);
}
src/gallium/drivers/svga/svga_context.h
+5 -4
View File
@@ -18,6 +18,7 @@
#include "util/u_blitter.h"
#include "util/list.h"
#include "vm_basic_types.h"
#include "svga_screen.h"
#include "svga_state.h"
#include "svga_winsys.h"
@@ -82,9 +83,9 @@ enum svga_hud {
#define CONST0_UPLOAD_ALIGNMENT 256
#define SVGA_MAX_UAVIEWS SVGA3D_DX11_1_MAX_UAVIEWS
#define SVGA_MAX_IMAGES SVGA3D_MAX_UAVIEWS
#define SVGA_MAX_SHADER_BUFFERS SVGA3D_MAX_UAVIEWS
#define SVGA_MAX_ATOMIC_BUFFERS SVGA3D_MAX_UAVIEWS
#define SVGA_MAX_IMAGES SVGA3D_DX11_MAX_UAVIEWS
#define SVGA_MAX_SHADER_BUFFERS SVGA3D_DX11_MAX_UAVIEWS
#define SVGA_MAX_ATOMIC_BUFFERS SVGA3D_DX11_MAX_UAVIEWS
enum svga_surface_state
{
@@ -387,7 +388,7 @@ struct svga_hw_clear_state
unsigned num_prescale;
unsigned num_rendertargets;
struct pipe_surface *rtv[SVGA3D_MAX_RENDER_TARGETS];
struct pipe_surface *rtv[SVGA3D_DX_MAX_RENDER_TARGETS];
struct pipe_surface *dsv;
};
src/gallium/drivers/svga/svga_format.h
-1
View File
@@ -11,7 +11,6 @@
#include "util/format/u_formats.h"
#include "svga_context.h"
#include "svga_types.h"
#include "svga_reg.h"
#include "svga3d_reg.h"
src/gallium/drivers/svga/svga_hw_reg.h
-2
View File
@@ -10,8 +10,6 @@
#include "util/compiler.h"
#include "svga_types.h"
#include "svga3d_reg.h"
src/gallium/drivers/svga/svga_pipe_blend.c
+1 -1
View File
@@ -126,7 +126,7 @@ static void
define_blend_state_object(struct svga_context *svga,
struct svga_blend_state *bs)
{
SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS];
int i;
assert(svga_have_vgpu10(svga));
src/gallium/drivers/svga/svga_resource_texture.c
+15 -14
View File
@@ -6,8 +6,9 @@
*/
#include "svga3d_reg.h"
#include "svga3d_surfacedefs.h"
#include "vmw_surf_defs.h"
#include "include/svga3d_surfacedefs.h"
#include "pipe/p_state.h"
#include "pipe/p_defines.h"
#include "util/u_thread.h"
@@ -422,13 +423,13 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
(tex->b.target == PIPE_TEXTURE_2D_ARRAY) ||
(tex->b.target == PIPE_TEXTURE_CUBE_ARRAY)) {
st->base.layer_stride =
svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
tex->b.last_level + 1, 1, 0);
vmw_surf_get_image_offset(tex->key.format, baseLevelSize,
tex->b.last_level + 1, 1, 0);
}
offset = svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
tex->b.last_level + 1, /* numMips */
st->slice, level);
offset = vmw_surf_get_image_offset(tex->key.format, baseLevelSize,
tex->b.last_level + 1, /* numMips */
st->slice, level);
if (level > 0) {
assert(offset > 0);
}
@@ -436,11 +437,11 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
mip_width = u_minify(tex->b.width0, level);
mip_height = u_minify(tex->b.height0, level);
offset += svga3dsurface_get_pixel_offset(tex->key.format,
mip_width, mip_height,
st->box.x,
st->box.y,
st->box.z);
offset += vmw_surf_get_pixel_offset(tex->key.format,
mip_width, mip_height,
st->box.x,
st->box.y,
st->box.z);
return (void *) (map + offset);
}
@@ -1541,10 +1542,10 @@ svga_texture_device_format_has_alpha(struct pipe_resource *texture)
/* the svga_texture() call below is invalid for PIPE_BUFFER resources */
assert(texture->target != PIPE_BUFFER);
const struct svga3d_surface_desc *surf_desc =
svga3dsurface_get_desc(svga_texture(texture)->key.format);
const struct SVGA3dSurfaceDesc *surf_desc =
vmw_surf_get_desc(svga_texture(texture)->key.format);
enum svga3d_block_desc block_desc = surf_desc->block_desc;
enum SVGA3dBlockDesc block_desc = surf_desc->blockDesc;
return !!((block_desc & SVGA3DBLOCKDESC_ALPHA) ||
((block_desc == SVGA3DBLOCKDESC_TYPELESS) &&
src/gallium/drivers/svga/svga_screen.c
+4 -3
View File
@@ -25,6 +25,7 @@
#include "svga_resource.h"
#include "svga_debug.h"
#include "vm_basic_types.h"
#include "svga3d_shaderdefs.h"
#include "VGPU10ShaderTokens.h"
@@ -350,7 +351,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
/* According to the spec, max varyings does not include the components
* for position, so remove one count from the max for position.
*/
return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS-1 : 10;
return sws->have_vgpu10 ? VGPU10_MAX_PS_INPUTS-1 : 10;
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
return sws->have_coherent;
@@ -632,7 +633,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
return 64;
case PIPE_SHADER_CAP_MAX_INPUTS:
if (shader == PIPE_SHADER_FRAGMENT)
return VGPU10_MAX_FS_INPUTS;
return VGPU10_MAX_PS_INPUTS;
else if (shader == PIPE_SHADER_GEOMETRY)
return svgascreen->max_gs_inputs;
else if (shader == PIPE_SHADER_TESS_CTRL)
@@ -643,7 +644,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
return svgascreen->max_vs_inputs;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
if (shader == PIPE_SHADER_FRAGMENT)
return VGPU10_MAX_FS_OUTPUTS;
return VGPU10_MAX_PS_OUTPUTS;
else if (shader == PIPE_SHADER_GEOMETRY)
return VGPU10_MAX_GS_OUTPUTS;
else if (shader == PIPE_SHADER_TESS_CTRL)
src/gallium/drivers/svga/svga_screen_cache.h
-2
View File
@@ -8,8 +8,6 @@
#ifndef SVGA_SCREEN_CACHE_H_
#define SVGA_SCREEN_CACHE_H_
#include "svga_types.h"
#include "svga_reg.h"
#include "svga3d_reg.h"
src/gallium/drivers/svga/svga_state_constants.c
+1 -1
View File
@@ -28,7 +28,7 @@ static unsigned
svga_get_image_size_constant(const struct svga_context *svga, float **dest,
enum pipe_shader_type shader,
unsigned num_image_views,
const struct svga_image_view images[PIPE_SHADER_TYPES][SVGA3D_MAX_UAVIEWS])
const struct svga_image_view images[PIPE_SHADER_TYPES][SVGA_MAX_IMAGES])
{
uint32_t *dest_u = (uint32_t *) *dest;
src/gallium/drivers/svga/svga_state_framebuffer.c
+1 -1
View File
@@ -166,7 +166,7 @@ static enum pipe_error
emit_fb_vgpu10(struct svga_context *svga)
{
const struct svga_screen *ss = svga_screen(svga->pipe.screen);
struct pipe_surface *rtv[SVGA3D_MAX_RENDER_TARGETS];
struct pipe_surface *rtv[SVGA3D_DX_MAX_RENDER_TARGETS];
struct pipe_surface *dsv;
struct pipe_framebuffer_state *curr = &svga->curr.framebuffer;
struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer;
src/gallium/drivers/svga/svga_swtnl_backend.c
-1
View File
@@ -18,7 +18,6 @@
#include "svga_state.h"
#include "svga_swtnl.h"
#include "svga_types.h"
#include "svga_reg.h"
#include "svga3d_reg.h"
#include "svga_draw.h"
src/gallium/drivers/svga/svga_swtnl_private.h
-1
View File
@@ -11,7 +11,6 @@
#include "svga_swtnl.h"
#include "draw/draw_vertex.h"
#include "svga_types.h"
#include "svga3d_reg.h"
/**
src/gallium/drivers/svga/svga_tgsi_emit.h
+1
View File
@@ -12,6 +12,7 @@
#include "svga_hw_reg.h"
#include "svga_shader.h"
#include "svga_tgsi.h"
#include "vm_basic_types.h"
#include "svga3d_shaderdefs.h"
struct src_register
src/gallium/drivers/svga/svga_tgsi_insn.c
+2 -2
View File
@@ -1039,7 +1039,7 @@ emit_if(struct svga_shader_emitter *emit,
struct src_register zero = get_zero_immediate(emit);
SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
if_token.control = SVGA3DOPCOMPC_NE;
if_token.control = SVGA3DOPCOMP_NE;
if (SVGA3dShaderGetRegType(src0.base.value) == SVGA3DREG_CONST) {
/*
@@ -1444,7 +1444,7 @@ emit_conditional(struct svga_shader_emitter *emit,
setp_token = inst_token_setp(SVGA3DOPCOMP_GT);
break;
case PIPE_FUNC_NOTEQUAL:
setp_token = inst_token_setp(SVGA3DOPCOMPC_NE);
setp_token = inst_token_setp(SVGA3DOPCOMP_NE);
break;
case PIPE_FUNC_GEQUAL:
setp_token = inst_token_setp(SVGA3DOPCOMP_GE);
src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+2 -2
View File
@@ -664,7 +664,7 @@ check_register_index(struct svga_shader_emitter_v10 *emit,
(emit->unit == PIPE_SHADER_GEOMETRY &&
index >= emit->max_gs_inputs) ||
(emit->unit == PIPE_SHADER_FRAGMENT &&
index >= VGPU10_MAX_FS_INPUTS) ||
index >= VGPU10_MAX_PS_INPUTS) ||
(emit->unit == PIPE_SHADER_TESS_CTRL &&
index >= VGPU11_MAX_HS_INPUT_CONTROL_POINTS) ||
(emit->unit == PIPE_SHADER_TESS_EVAL &&
@@ -687,7 +687,7 @@ check_register_index(struct svga_shader_emitter_v10 *emit,
(emit->unit == PIPE_SHADER_GEOMETRY &&
index >= VGPU10_MAX_GS_OUTPUTS) ||
(emit->unit == PIPE_SHADER_FRAGMENT &&
index >= VGPU10_MAX_FS_OUTPUTS) ||
index >= VGPU10_MAX_PS_OUTPUTS) ||
(emit->unit == PIPE_SHADER_TESS_CTRL &&
index >= VGPU11_MAX_HS_OUTPUTS + 2) ||
(emit->unit == PIPE_SHADER_TESS_EVAL &&
src/gallium/drivers/svga/svga_winsys.h
-1
View File
@@ -17,7 +17,6 @@
#ifndef SVGA_WINSYS_H_
#define SVGA_WINSYS_H_
#include "svga_types.h"
#include "svga3d_types.h"
#include "svga_reg.h"
#include "svga3d_reg.h"
src/gallium/drivers/svga/svgadump/svga_dump.c
-1
View File
@@ -13,7 +13,6 @@
*/
#include "../svga_format.h"
#include "svga_types.h"
#include "svga_shader_dump.h"
#include "svga3d_reg.h"
src/gallium/drivers/svga/svgadump/svga_dump.py
+1 -3
View File
@@ -300,7 +300,6 @@ def main():
print ' * Generated automatically from svga3d_reg.h by svga_dump.py.'
print ' */'
print
print '#include "svga_types.h"'
print '#include "svga_shader_dump.h"'
print '#include "svga3d_reg.h"'
print
@@ -314,8 +313,7 @@ def main():
)
headers = [
'svga_types.h',
'svga3d_reg.h',
'svga3d_reg.h',
]
decls = parser.parse(headers, config, parser.COMPILATION_MODE.ALL_AT_ONCE)
src/gallium/drivers/svga/svgadump/svga_shader_dump.c
+1 -1
View File
@@ -95,7 +95,7 @@ static void dump_op( struct sh_op op, const char *mnemonic )
case SVGA3DOPCOMP_LT:
_debug_printf("_lt");
break;
case SVGA3DOPCOMPC_NE:
case SVGA3DOPCOMP_NE:
_debug_printf("_ne");
break;
case SVGA3DOPCOMP_LE:
src/gallium/winsys/svga/drm/vmw_screen_dri.c
+4 -4
View File
@@ -15,7 +15,7 @@
#include "vmw_surface.h"
#include "vmw_buffer.h"
#include "svga_drm_public.h"
#include "svga3d_surfacedefs.h"
#include "vmw_surf_defs.h"
#include "frontend/drm_driver.h"
@@ -290,9 +290,9 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
base_size.width = size.width;
base_size.height = size.height;
base_size.depth = size.depth;
vsrf->size = svga3dsurface_get_serialized_size(rep->format, base_size,
rep->mip_levels[0],
false);
vsrf->size = vmw_surf_get_serialized_size(rep->format, base_size,
rep->mip_levels[0],
false);
return ssrf;
src/gallium/winsys/svga/drm/vmw_screen_ioctl.c
+13 -8
View File
@@ -25,7 +25,7 @@
#include "vmw_fence.h"
#include "xf86drm.h"
#include "vmwgfx_drm.h"
#include "svga3d_caps.h"
#include "svga3d_devcaps.h"
#include "svga3d_reg.h"
#include "util/os_mman.h"
@@ -902,6 +902,11 @@ vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid)
}
struct svga_3d_compat_cap {
SVGA3dFifoCapsRecordHeader header;
SVGA3dFifoCapPair pairs[SVGA3D_DEVCAP_MAX];
};
static int
vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws,
const uint32_t *cap_buffer)
@@ -916,9 +921,9 @@ vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws,
return 0;
} else {
const uint32 *capsBlock;
const SVGA3dCapsRecord *capsRecord = NULL;
const struct svga_3d_compat_cap *capsRecord = NULL;
uint32 offset;
const SVGA3dCapPair *capArray;
const SVGA3dFifoCapPair *capArray;
int numCaps, index;
/*
@@ -926,11 +931,11 @@ vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws,
*/
capsBlock = cap_buffer;
for (offset = 0; capsBlock[offset] != 0; offset += capsBlock[offset]) {
const SVGA3dCapsRecord *record;
const struct svga_3d_compat_cap *record;
assert(offset < SVGA_FIFO_3D_CAPS_SIZE);
record = (const SVGA3dCapsRecord *) (capsBlock + offset);
if ((record->header.type >= SVGA3DCAPS_RECORD_DEVCAPS_MIN) &&
(record->header.type <= SVGA3DCAPS_RECORD_DEVCAPS_MAX) &&
record = (const struct svga_3d_compat_cap *) (capsBlock + offset);
if ((record->header.type >= 0) &&
(record->header.type <= SVGA3D_DEVCAP_MAX) &&
(!capsRecord || (record->header.type > capsRecord->header.type))) {
capsRecord = record;
}
@@ -942,7 +947,7 @@ vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws,
/*
* Calculate the number of caps from the size of the record.
*/
capArray = (const SVGA3dCapPair *) capsRecord->data;
capArray = (const SVGA3dFifoCapPair *) capsRecord->pairs;
numCaps = (int) ((capsRecord->header.length * sizeof(uint32) -
sizeof capsRecord->header) / (2 * sizeof(uint32)));
src/gallium/winsys/svga/drm/vmw_screen_svga.c
+9 -9
View File
@@ -20,7 +20,8 @@
#include <sys/mman.h>
#include "svga_cmd.h"
#include "svga3d_caps.h"
#include "svga3d_devcaps.h"
#include "vmw_surf_defs.h"
#include "c11/threads.h"
#include "util/os_file.h"
@@ -39,7 +40,6 @@
#include "vmw_shader.h"
#include "vmw_query.h"
#include "vmwgfx_drm.h"
#include "svga3d_surfacedefs.h"
#include "xf86drm.h"
/**
@@ -505,10 +505,10 @@ vmw_svga_winsys_surface_create(struct svga_winsys_screen *sws,
* Used for the backing buffer GB surfaces, and to approximate
* when to flush on non-GB hosts.
*/
buffer_size = svga3dsurface_get_serialized_size_extended(format, size,
numMipLevels,
numLayers,
num_samples);
buffer_size = vmw_surf_get_serialized_size_extended(format, size,
numMipLevels,
numLayers,
num_samples);
if (flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
buffer_size += sizeof(SVGA3dDXSOState);
@@ -578,9 +578,9 @@ vmw_svga_winsys_surface_can_create(struct svga_winsys_screen *sws,
struct vmw_winsys_screen *vws = vmw_winsys_screen(sws);
uint32_t buffer_size;
buffer_size = svga3dsurface_get_serialized_size(format, size,
numMipLevels,
numLayers);
buffer_size = vmw_surf_get_serialized_size(format, size,
numMipLevels,
numLayers);
if (numSamples > 1)
buffer_size *= numSamples;