From 05e0554d76dd4aca09e20f0361aa5901b5e2a9a8 Mon Sep 17 00:00:00 2001 From: Zack Rusin Date: Thu, 10 Oct 2024 08:02:26 -0400 Subject: [PATCH] svga: Redo the way generated files are handled Long time ago svga had a sourceforge project where auto-generated header files for the SVGA device were hosted. Gallium's svga driver copied those files and when the sourceforge project became obsolete they started being updated by hand. Kernel and igt projects switched to the official way in which the SVGA header files are generated but Mesa3d wasn't ported at the time. The official SVGA headers diverged from the official ones creating bugs. Fix it by porting the SVGA Gallium driver to the auto-generated SVGA header files. Signed-off-by: Zack Rusin Part-of: --- src/gallium/drivers/svga/include/README | 4 +- .../drivers/svga/include/VGPU10ShaderTokens.h | 1133 +++---- .../drivers/svga/include/includeCheck.h | 1 - .../drivers/svga/include/svga3d_caps.h | 96 - src/gallium/drivers/svga/include/svga3d_cmd.h | 2702 ++++++----------- .../drivers/svga/include/svga3d_devcaps.h | 735 ++--- src/gallium/drivers/svga/include/svga3d_dx.h | 1815 +++++------ .../drivers/svga/include/svga3d_limits.h | 86 +- src/gallium/drivers/svga/include/svga3d_reg.h | 45 +- .../drivers/svga/include/svga3d_shaderdefs.h | 500 ++- .../drivers/svga/include/svga3d_surfacedefs.h | 2644 ++++++++-------- .../drivers/svga/include/svga3d_types.h | 2429 +++++++-------- .../drivers/svga/include/svga_escape.h | 78 +- .../drivers/svga/include/svga_overlay.h | 167 +- src/gallium/drivers/svga/include/svga_reg.h | 2082 ++++--------- src/gallium/drivers/svga/include/svga_types.h | 39 - .../drivers/svga/include/vm_basic_types.h | 44 + .../drivers/svga/include/vmw_surf_defs.h | 196 ++ .../drivers/svga/include/vmware_pack_begin.h | 1 - .../drivers/svga/include/vmware_pack_end.h | 1 - src/gallium/drivers/svga/svga_cmd.h | 1 - src/gallium/drivers/svga/svga_cmd_vgpu10.c | 2 +- src/gallium/drivers/svga/svga_context.h | 9 +- src/gallium/drivers/svga/svga_format.h | 1 - src/gallium/drivers/svga/svga_hw_reg.h | 2 - src/gallium/drivers/svga/svga_pipe_blend.c | 2 +- .../drivers/svga/svga_resource_texture.c | 29 +- src/gallium/drivers/svga/svga_screen.c | 7 +- src/gallium/drivers/svga/svga_screen_cache.h | 2 - .../drivers/svga/svga_state_constants.c | 2 +- .../drivers/svga/svga_state_framebuffer.c | 2 +- src/gallium/drivers/svga/svga_swtnl_backend.c | 1 - src/gallium/drivers/svga/svga_swtnl_private.h | 1 - src/gallium/drivers/svga/svga_tgsi_emit.h | 1 + src/gallium/drivers/svga/svga_tgsi_insn.c | 4 +- src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 4 +- src/gallium/drivers/svga/svga_winsys.h | 1 - src/gallium/drivers/svga/svgadump/svga_dump.c | 1 - .../drivers/svga/svgadump/svga_dump.py | 4 +- .../drivers/svga/svgadump/svga_shader_dump.c | 2 +- src/gallium/winsys/svga/drm/vmw_screen_dri.c | 8 +- .../winsys/svga/drm/vmw_screen_ioctl.c | 21 +- src/gallium/winsys/svga/drm/vmw_screen_svga.c | 18 +- 43 files changed, 6206 insertions(+), 8717 deletions(-) delete mode 100644 src/gallium/drivers/svga/include/includeCheck.h delete mode 100644 src/gallium/drivers/svga/include/svga3d_caps.h delete mode 100644 src/gallium/drivers/svga/include/svga_types.h create mode 100644 src/gallium/drivers/svga/include/vm_basic_types.h create mode 100644 src/gallium/drivers/svga/include/vmw_surf_defs.h delete mode 100644 src/gallium/drivers/svga/include/vmware_pack_begin.h delete mode 100644 src/gallium/drivers/svga/include/vmware_pack_end.h diff --git a/src/gallium/drivers/svga/include/README b/src/gallium/drivers/svga/include/README index a0b8916104e..87f1dca79d4 100644 --- a/src/gallium/drivers/svga/include/README +++ b/src/gallium/drivers/svga/include/README @@ -1,3 +1,3 @@ -This directory contains the headers from the VMware SVGA Device Developer Kit: +Files in this directory are auto-generated from description files and any changes made to them will be discarded on the next update. - https://vmware-svga.svn.sourceforge.net/svnroot/vmware-svga/trunk/lib/vmware/ +Only vmw_surf_defs.h and vm_basic_types.h are written from scratch and provide the glue necessary for the auto-generated files (the rest of them). diff --git a/src/gallium/drivers/svga/include/VGPU10ShaderTokens.h b/src/gallium/drivers/svga/include/VGPU10ShaderTokens.h index f645d4c767a..c0a6fddd842 100644 --- a/src/gallium/drivers/svga/include/VGPU10ShaderTokens.h +++ b/src/gallium/drivers/svga/include/VGPU10ShaderTokens.h @@ -1,8 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2012-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2012-2023 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* @@ -11,311 +31,302 @@ * VGPU10 shader token definitions. */ - - - - #ifndef VGPU10SHADERTOKENS_H #define VGPU10SHADERTOKENS_H +#ifdef __cplusplus +extern "C" { +#endif -#define VGPU10_MAX_VS_INPUTS 16 -#define VGPU10_MAX_VS_OUTPUTS 16 -#define VGPU10_MAX_GS_INPUTS 16 -#define VGPU10_MAX_GS_OUTPUTS 32 -#define VGPU10_MAX_FS_INPUTS 32 -#define VGPU10_MAX_FS_OUTPUTS 8 -#define VGPU10_MAX_TEMPS 4096 -#define VGPU10_MAX_CONSTANT_BUFFERS (14 + 1) -#define VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT 4096 +#include "vm_basic_types.h" + +#define VGPU10_MAX_VS_INPUTS 16 +#define VGPU10_MAX_VS_OUTPUTS 16 +#define VGPU10_MAX_GS_INPUTS 16 +#define VGPU10_MAX_GS_OUTPUTS 32 +#define VGPU10_MAX_PS_INPUTS 32 +#define VGPU10_MAX_PS_OUTPUTS 8 +#define VGPU10_MAX_TEMPS 4096 +#define VGPU10_MAX_CONSTANT_BUFFERS (14 + 1) +#define VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT 4096 #define VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT 4096 -#define VGPU10_MAX_SAMPLERS 16 -#define VGPU10_MAX_RESOURCES 128 -#define VGPU10_MIN_TEXEL_FETCH_OFFSET -8 -#define VGPU10_MAX_TEXEL_FETCH_OFFSET 7 +#define VGPU10_MAX_SAMPLERS 16 +#define VGPU10_MAX_RESOURCES 128 +#define VGPU10_MIN_TEXEL_FETCH_OFFSET -8 +#define VGPU10_MAX_TEXEL_FETCH_OFFSET 7 +#define VGPU10_1_MAX_VS_INPUTS 32 +#define VGPU10_1_MAX_VS_OUTPUTS 32 +#define VGPU10_1_MAX_GS_INPUTS 32 -#define VGPU10_1_MAX_VS_INPUTS 32 -#define VGPU10_1_MAX_VS_OUTPUTS 32 -#define VGPU10_1_MAX_GS_INPUTS 32 +#define VGPU11_MAX_HS_INPUT_CONTROL_POINTS 32 +#define VGPU11_MAX_HS_INPUT_PATCH_CONSTANTS 32 +#define VGPU11_MAX_HS_OUTPUT_CP_PHASE_ELEMENTS 32 +#define VGPU11_MAX_HS_OUTPUT_CONTROL_POINTS 32 +#define VGPU11_MAX_HS_OUTPUTS 32 +#define VGPU11_MAX_DS_INPUT_CONTROL_POINTS 32 +#define VGPU11_MAX_DS_INPUT_PATCH_CONSTANTS 32 +#define VGPU11_MAX_DS_OUTPUTS 32 +#define VGPU11_MAX_GS_STREAMS 4 +#define VGPU11_MAX_FUNCTION_BODIES 256 +#define VGPU11_MAX_FUNCTION_TABLES 256 +#define VGPU11_MAX_INTERFACES 253 - -#define VGPU11_MAX_HS_INPUT_CONTROL_POINTS 32 -#define VGPU11_MAX_HS_INPUT_PATCH_CONSTANTS 32 -#define VGPU11_MAX_HS_OUTPUT_CP_PHASE_ELEMENTS 32 -#define VGPU11_MAX_HS_OUTPUT_CONTROL_POINTS 32 -#define VGPU11_MAX_HS_OUTPUTS 32 -#define VGPU11_MAX_DS_INPUT_CONTROL_POINTS 32 -#define VGPU11_MAX_DS_INPUT_PATCH_CONSTANTS 32 -#define VGPU11_MAX_DS_OUTPUTS 32 -#define VGPU11_MAX_GS_STREAMS 4 -#define VGPU11_MAX_FUNCTION_BODIES 256 -#define VGPU11_MAX_FUNCTION_TABLES 256 -#define VGPU11_MAX_INTERFACES 253 - - -#define VGPU10_MAX_INPUTS 32 -#define VGPU10_MAX_OUTPUTS 32 -#define VGPU10_MAX_INPUT_PATCH_CONSTANTS 32 +#define VGPU10_MAX_INPUTS 32 +#define VGPU10_MAX_OUTPUTS 32 +#define VGPU10_MAX_INPUT_PATCH_CONSTANTS 32 typedef enum { - VGPU10_PIXEL_SHADER = 0, - VGPU10_VERTEX_SHADER = 1, - VGPU10_GEOMETRY_SHADER = 2, + VGPU10_PIXEL_SHADER = 0, + VGPU10_VERTEX_SHADER = 1, + VGPU10_GEOMETRY_SHADER = 2, - - VGPU10_HULL_SHADER = 3, - VGPU10_DOMAIN_SHADER = 4, - VGPU10_COMPUTE_SHADER = 5 + VGPU10_HULL_SHADER = 3, + VGPU10_DOMAIN_SHADER = 4, + VGPU10_COMPUTE_SHADER = 5 } VGPU10_PROGRAM_TYPE; typedef union { struct { - unsigned int minorVersion : 4; - unsigned int majorVersion : 4; - unsigned int : 8; - unsigned int programType : 16; + unsigned int minorVersion : 4; + unsigned int majorVersion : 4; + unsigned int : 8; + unsigned int programType : 16; }; uint32 value; } VGPU10ProgramToken; - typedef enum { - VGPU10_OPCODE_ADD = 0, - VGPU10_OPCODE_AND = 1, - VGPU10_OPCODE_BREAK = 2, - VGPU10_OPCODE_BREAKC = 3, - VGPU10_OPCODE_CALL = 4, - VGPU10_OPCODE_CALLC = 5, - VGPU10_OPCODE_CASE = 6, - VGPU10_OPCODE_CONTINUE = 7, - VGPU10_OPCODE_CONTINUEC = 8, - VGPU10_OPCODE_CUT = 9, - VGPU10_OPCODE_DEFAULT = 10, - VGPU10_OPCODE_DERIV_RTX = 11, - VGPU10_OPCODE_DERIV_RTY = 12, - VGPU10_OPCODE_DISCARD = 13, - VGPU10_OPCODE_DIV = 14, - VGPU10_OPCODE_DP2 = 15, - VGPU10_OPCODE_DP3 = 16, - VGPU10_OPCODE_DP4 = 17, - VGPU10_OPCODE_ELSE = 18, - VGPU10_OPCODE_EMIT = 19, - VGPU10_OPCODE_EMITTHENCUT = 20, - VGPU10_OPCODE_ENDIF = 21, - VGPU10_OPCODE_ENDLOOP = 22, - VGPU10_OPCODE_ENDSWITCH = 23, - VGPU10_OPCODE_EQ = 24, - VGPU10_OPCODE_EXP = 25, - VGPU10_OPCODE_FRC = 26, - VGPU10_OPCODE_FTOI = 27, - VGPU10_OPCODE_FTOU = 28, - VGPU10_OPCODE_GE = 29, - VGPU10_OPCODE_IADD = 30, - VGPU10_OPCODE_IF = 31, - VGPU10_OPCODE_IEQ = 32, - VGPU10_OPCODE_IGE = 33, - VGPU10_OPCODE_ILT = 34, - VGPU10_OPCODE_IMAD = 35, - VGPU10_OPCODE_IMAX = 36, - VGPU10_OPCODE_IMIN = 37, - VGPU10_OPCODE_IMUL = 38, - VGPU10_OPCODE_INE = 39, - VGPU10_OPCODE_INEG = 40, - VGPU10_OPCODE_ISHL = 41, - VGPU10_OPCODE_ISHR = 42, - VGPU10_OPCODE_ITOF = 43, - VGPU10_OPCODE_LABEL = 44, - VGPU10_OPCODE_LD = 45, - VGPU10_OPCODE_LD_MS = 46, - VGPU10_OPCODE_LOG = 47, - VGPU10_OPCODE_LOOP = 48, - VGPU10_OPCODE_LT = 49, - VGPU10_OPCODE_MAD = 50, - VGPU10_OPCODE_MIN = 51, - VGPU10_OPCODE_MAX = 52, - VGPU10_OPCODE_CUSTOMDATA = 53, - VGPU10_OPCODE_MOV = 54, - VGPU10_OPCODE_MOVC = 55, - VGPU10_OPCODE_MUL = 56, - VGPU10_OPCODE_NE = 57, - VGPU10_OPCODE_NOP = 58, - VGPU10_OPCODE_NOT = 59, - VGPU10_OPCODE_OR = 60, - VGPU10_OPCODE_RESINFO = 61, - VGPU10_OPCODE_RET = 62, - VGPU10_OPCODE_RETC = 63, - VGPU10_OPCODE_ROUND_NE = 64, - VGPU10_OPCODE_ROUND_NI = 65, - VGPU10_OPCODE_ROUND_PI = 66, - VGPU10_OPCODE_ROUND_Z = 67, - VGPU10_OPCODE_RSQ = 68, - VGPU10_OPCODE_SAMPLE = 69, - VGPU10_OPCODE_SAMPLE_C = 70, - VGPU10_OPCODE_SAMPLE_C_LZ = 71, - VGPU10_OPCODE_SAMPLE_L = 72, - VGPU10_OPCODE_SAMPLE_D = 73, - VGPU10_OPCODE_SAMPLE_B = 74, - VGPU10_OPCODE_SQRT = 75, - VGPU10_OPCODE_SWITCH = 76, - VGPU10_OPCODE_SINCOS = 77, - VGPU10_OPCODE_UDIV = 78, - VGPU10_OPCODE_ULT = 79, - VGPU10_OPCODE_UGE = 80, - VGPU10_OPCODE_UMUL = 81, - VGPU10_OPCODE_UMAD = 82, - VGPU10_OPCODE_UMAX = 83, - VGPU10_OPCODE_UMIN = 84, - VGPU10_OPCODE_USHR = 85, - VGPU10_OPCODE_UTOF = 86, - VGPU10_OPCODE_XOR = 87, - VGPU10_OPCODE_DCL_RESOURCE = 88, - VGPU10_OPCODE_DCL_CONSTANT_BUFFER = 89, - VGPU10_OPCODE_DCL_SAMPLER = 90, - VGPU10_OPCODE_DCL_INDEX_RANGE = 91, - VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY = 92, - VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE = 93, - VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT = 94, - VGPU10_OPCODE_DCL_INPUT = 95, - VGPU10_OPCODE_DCL_INPUT_SGV = 96, - VGPU10_OPCODE_DCL_INPUT_SIV = 97, - VGPU10_OPCODE_DCL_INPUT_PS = 98, - VGPU10_OPCODE_DCL_INPUT_PS_SGV = 99, - VGPU10_OPCODE_DCL_INPUT_PS_SIV = 100, - VGPU10_OPCODE_DCL_OUTPUT = 101, - VGPU10_OPCODE_DCL_OUTPUT_SGV = 102, - VGPU10_OPCODE_DCL_OUTPUT_SIV = 103, - VGPU10_OPCODE_DCL_TEMPS = 104, - VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105, - VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106, + VGPU10_OPCODE_ADD = 0, + VGPU10_OPCODE_AND = 1, + VGPU10_OPCODE_BREAK = 2, + VGPU10_OPCODE_BREAKC = 3, + VGPU10_OPCODE_CALL = 4, + VGPU10_OPCODE_CALLC = 5, + VGPU10_OPCODE_CASE = 6, + VGPU10_OPCODE_CONTINUE = 7, + VGPU10_OPCODE_CONTINUEC = 8, + VGPU10_OPCODE_CUT = 9, + VGPU10_OPCODE_DEFAULT = 10, + VGPU10_OPCODE_DERIV_RTX = 11, + VGPU10_OPCODE_DERIV_RTY = 12, + VGPU10_OPCODE_DISCARD = 13, + VGPU10_OPCODE_DIV = 14, + VGPU10_OPCODE_DP2 = 15, + VGPU10_OPCODE_DP3 = 16, + VGPU10_OPCODE_DP4 = 17, + VGPU10_OPCODE_ELSE = 18, + VGPU10_OPCODE_EMIT = 19, + VGPU10_OPCODE_EMITTHENCUT = 20, + VGPU10_OPCODE_ENDIF = 21, + VGPU10_OPCODE_ENDLOOP = 22, + VGPU10_OPCODE_ENDSWITCH = 23, + VGPU10_OPCODE_EQ = 24, + VGPU10_OPCODE_EXP = 25, + VGPU10_OPCODE_FRC = 26, + VGPU10_OPCODE_FTOI = 27, + VGPU10_OPCODE_FTOU = 28, + VGPU10_OPCODE_GE = 29, + VGPU10_OPCODE_IADD = 30, + VGPU10_OPCODE_IF = 31, + VGPU10_OPCODE_IEQ = 32, + VGPU10_OPCODE_IGE = 33, + VGPU10_OPCODE_ILT = 34, + VGPU10_OPCODE_IMAD = 35, + VGPU10_OPCODE_IMAX = 36, + VGPU10_OPCODE_IMIN = 37, + VGPU10_OPCODE_IMUL = 38, + VGPU10_OPCODE_INE = 39, + VGPU10_OPCODE_INEG = 40, + VGPU10_OPCODE_ISHL = 41, + VGPU10_OPCODE_ISHR = 42, + VGPU10_OPCODE_ITOF = 43, + VGPU10_OPCODE_LABEL = 44, + VGPU10_OPCODE_LD = 45, + VGPU10_OPCODE_LD_MS = 46, + VGPU10_OPCODE_LOG = 47, + VGPU10_OPCODE_LOOP = 48, + VGPU10_OPCODE_LT = 49, + VGPU10_OPCODE_MAD = 50, + VGPU10_OPCODE_MIN = 51, + VGPU10_OPCODE_MAX = 52, + VGPU10_OPCODE_CUSTOMDATA = 53, + VGPU10_OPCODE_MOV = 54, + VGPU10_OPCODE_MOVC = 55, + VGPU10_OPCODE_MUL = 56, + VGPU10_OPCODE_NE = 57, + VGPU10_OPCODE_NOP = 58, + VGPU10_OPCODE_NOT = 59, + VGPU10_OPCODE_OR = 60, + VGPU10_OPCODE_RESINFO = 61, + VGPU10_OPCODE_RET = 62, + VGPU10_OPCODE_RETC = 63, + VGPU10_OPCODE_ROUND_NE = 64, + VGPU10_OPCODE_ROUND_NI = 65, + VGPU10_OPCODE_ROUND_PI = 66, + VGPU10_OPCODE_ROUND_Z = 67, + VGPU10_OPCODE_RSQ = 68, + VGPU10_OPCODE_SAMPLE = 69, + VGPU10_OPCODE_SAMPLE_C = 70, + VGPU10_OPCODE_SAMPLE_C_LZ = 71, + VGPU10_OPCODE_SAMPLE_L = 72, + VGPU10_OPCODE_SAMPLE_D = 73, + VGPU10_OPCODE_SAMPLE_B = 74, + VGPU10_OPCODE_SQRT = 75, + VGPU10_OPCODE_SWITCH = 76, + VGPU10_OPCODE_SINCOS = 77, + VGPU10_OPCODE_UDIV = 78, + VGPU10_OPCODE_ULT = 79, + VGPU10_OPCODE_UGE = 80, + VGPU10_OPCODE_UMUL = 81, + VGPU10_OPCODE_UMAD = 82, + VGPU10_OPCODE_UMAX = 83, + VGPU10_OPCODE_UMIN = 84, + VGPU10_OPCODE_USHR = 85, + VGPU10_OPCODE_UTOF = 86, + VGPU10_OPCODE_XOR = 87, + VGPU10_OPCODE_DCL_RESOURCE = 88, + VGPU10_OPCODE_DCL_CONSTANT_BUFFER = 89, + VGPU10_OPCODE_DCL_SAMPLER = 90, + VGPU10_OPCODE_DCL_INDEX_RANGE = 91, + VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY = 92, + VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE = 93, + VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT = 94, + VGPU10_OPCODE_DCL_INPUT = 95, + VGPU10_OPCODE_DCL_INPUT_SGV = 96, + VGPU10_OPCODE_DCL_INPUT_SIV = 97, + VGPU10_OPCODE_DCL_INPUT_PS = 98, + VGPU10_OPCODE_DCL_INPUT_PS_SGV = 99, + VGPU10_OPCODE_DCL_INPUT_PS_SIV = 100, + VGPU10_OPCODE_DCL_OUTPUT = 101, + VGPU10_OPCODE_DCL_OUTPUT_SGV = 102, + VGPU10_OPCODE_DCL_OUTPUT_SIV = 103, + VGPU10_OPCODE_DCL_TEMPS = 104, + VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105, + VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106, + VGPU10_OPCODE_VMWARE = 107, - VGPU10_OPCODE_VMWARE = 107, + VGPU10_OPCODE_LOD = 108, + VGPU10_OPCODE_GATHER4 = 109, + VGPU10_OPCODE_SAMPLE_POS = 110, + VGPU10_OPCODE_SAMPLE_INFO = 111, + VGPU10_OPCODE_RESERVED1 = 112, + VGPU10_OPCODE_HS_DECLS = 113, + VGPU10_OPCODE_HS_CONTROL_POINT_PHASE = 114, + VGPU10_OPCODE_HS_FORK_PHASE = 115, + VGPU10_OPCODE_HS_JOIN_PHASE = 116, + VGPU10_OPCODE_EMIT_STREAM = 117, + VGPU10_OPCODE_CUT_STREAM = 118, + VGPU10_OPCODE_EMITTHENCUT_STREAM = 119, + VGPU10_OPCODE_INTERFACE_CALL = 120, + VGPU10_OPCODE_BUFINFO = 121, + VGPU10_OPCODE_DERIV_RTX_COARSE = 122, + VGPU10_OPCODE_DERIV_RTX_FINE = 123, + VGPU10_OPCODE_DERIV_RTY_COARSE = 124, + VGPU10_OPCODE_DERIV_RTY_FINE = 125, + VGPU10_OPCODE_GATHER4_C = 126, + VGPU10_OPCODE_GATHER4_PO = 127, + VGPU10_OPCODE_GATHER4_PO_C = 128, + VGPU10_OPCODE_RCP = 129, + VGPU10_OPCODE_F32TOF16 = 130, + VGPU10_OPCODE_F16TOF32 = 131, + VGPU10_OPCODE_UADDC = 132, + VGPU10_OPCODE_USUBB = 133, + VGPU10_OPCODE_COUNTBITS = 134, + VGPU10_OPCODE_FIRSTBIT_HI = 135, + VGPU10_OPCODE_FIRSTBIT_LO = 136, + VGPU10_OPCODE_FIRSTBIT_SHI = 137, + VGPU10_OPCODE_UBFE = 138, + VGPU10_OPCODE_IBFE = 139, + VGPU10_OPCODE_BFI = 140, + VGPU10_OPCODE_BFREV = 141, + VGPU10_OPCODE_SWAPC = 142, + VGPU10_OPCODE_DCL_STREAM = 143, + VGPU10_OPCODE_DCL_FUNCTION_BODY = 144, + VGPU10_OPCODE_DCL_FUNCTION_TABLE = 145, + VGPU10_OPCODE_DCL_INTERFACE = 146, + VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT = 147, + VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT = 148, + VGPU10_OPCODE_DCL_TESS_DOMAIN = 149, + VGPU10_OPCODE_DCL_TESS_PARTITIONING = 150, + VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE = 151, + VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR = 152, + VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT = 153, + VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT = 154, + VGPU10_OPCODE_DCL_THREAD_GROUP = 155, + VGPU10_OPCODE_DCL_UAV_TYPED = 156, + VGPU10_OPCODE_DCL_UAV_RAW = 157, + VGPU10_OPCODE_DCL_UAV_STRUCTURED = 158, + VGPU10_OPCODE_DCL_TGSM_RAW = 159, + VGPU10_OPCODE_DCL_TGSM_STRUCTURED = 160, + VGPU10_OPCODE_DCL_RESOURCE_RAW = 161, + VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED = 162, + VGPU10_OPCODE_LD_UAV_TYPED = 163, + VGPU10_OPCODE_STORE_UAV_TYPED = 164, + VGPU10_OPCODE_LD_RAW = 165, + VGPU10_OPCODE_STORE_RAW = 166, + VGPU10_OPCODE_LD_STRUCTURED = 167, + VGPU10_OPCODE_STORE_STRUCTURED = 168, + VGPU10_OPCODE_ATOMIC_AND = 169, + VGPU10_OPCODE_ATOMIC_OR = 170, + VGPU10_OPCODE_ATOMIC_XOR = 171, + VGPU10_OPCODE_ATOMIC_CMP_STORE = 172, + VGPU10_OPCODE_ATOMIC_IADD = 173, + VGPU10_OPCODE_ATOMIC_IMAX = 174, + VGPU10_OPCODE_ATOMIC_IMIN = 175, + VGPU10_OPCODE_ATOMIC_UMAX = 176, + VGPU10_OPCODE_ATOMIC_UMIN = 177, + VGPU10_OPCODE_IMM_ATOMIC_ALLOC = 178, + VGPU10_OPCODE_IMM_ATOMIC_CONSUME = 179, + VGPU10_OPCODE_IMM_ATOMIC_IADD = 180, + VGPU10_OPCODE_IMM_ATOMIC_AND = 181, + VGPU10_OPCODE_IMM_ATOMIC_OR = 182, + VGPU10_OPCODE_IMM_ATOMIC_XOR = 183, + VGPU10_OPCODE_IMM_ATOMIC_EXCH = 184, + VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH = 185, + VGPU10_OPCODE_IMM_ATOMIC_IMAX = 186, + VGPU10_OPCODE_IMM_ATOMIC_IMIN = 187, + VGPU10_OPCODE_IMM_ATOMIC_UMAX = 188, + VGPU10_OPCODE_IMM_ATOMIC_UMIN = 189, + VGPU10_OPCODE_SYNC = 190, + VGPU10_OPCODE_DADD = 191, + VGPU10_OPCODE_DMAX = 192, + VGPU10_OPCODE_DMIN = 193, + VGPU10_OPCODE_DMUL = 194, + VGPU10_OPCODE_DEQ = 195, + VGPU10_OPCODE_DGE = 196, + VGPU10_OPCODE_DLT = 197, + VGPU10_OPCODE_DNE = 198, + VGPU10_OPCODE_DMOV = 199, + VGPU10_OPCODE_DMOVC = 200, + VGPU10_OPCODE_DTOF = 201, + VGPU10_OPCODE_FTOD = 202, + VGPU10_OPCODE_EVAL_SNAPPED = 203, + VGPU10_OPCODE_EVAL_SAMPLE_INDEX = 204, + VGPU10_OPCODE_EVAL_CENTROID = 205, + VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT = 206, + VGPU10_OPCODE_ABORT = 207, + VGPU10_OPCODE_DEBUG_BREAK = 208, - VGPU10_OPCODE_LOD = 108, - VGPU10_OPCODE_GATHER4 = 109, - VGPU10_OPCODE_SAMPLE_POS = 110, - VGPU10_OPCODE_SAMPLE_INFO = 111, - - - VGPU10_OPCODE_RESERVED1 = 112, - VGPU10_OPCODE_HS_DECLS = 113, - VGPU10_OPCODE_HS_CONTROL_POINT_PHASE = 114, - VGPU10_OPCODE_HS_FORK_PHASE = 115, - VGPU10_OPCODE_HS_JOIN_PHASE = 116, - VGPU10_OPCODE_EMIT_STREAM = 117, - VGPU10_OPCODE_CUT_STREAM = 118, - VGPU10_OPCODE_EMITTHENCUT_STREAM = 119, - VGPU10_OPCODE_INTERFACE_CALL = 120, - VGPU10_OPCODE_BUFINFO = 121, - VGPU10_OPCODE_DERIV_RTX_COARSE = 122, - VGPU10_OPCODE_DERIV_RTX_FINE = 123, - VGPU10_OPCODE_DERIV_RTY_COARSE = 124, - VGPU10_OPCODE_DERIV_RTY_FINE = 125, - VGPU10_OPCODE_GATHER4_C = 126, - VGPU10_OPCODE_GATHER4_PO = 127, - VGPU10_OPCODE_GATHER4_PO_C = 128, - VGPU10_OPCODE_RCP = 129, - VGPU10_OPCODE_F32TOF16 = 130, - VGPU10_OPCODE_F16TOF32 = 131, - VGPU10_OPCODE_UADDC = 132, - VGPU10_OPCODE_USUBB = 133, - VGPU10_OPCODE_COUNTBITS = 134, - VGPU10_OPCODE_FIRSTBIT_HI = 135, - VGPU10_OPCODE_FIRSTBIT_LO = 136, - VGPU10_OPCODE_FIRSTBIT_SHI = 137, - VGPU10_OPCODE_UBFE = 138, - VGPU10_OPCODE_IBFE = 139, - VGPU10_OPCODE_BFI = 140, - VGPU10_OPCODE_BFREV = 141, - VGPU10_OPCODE_SWAPC = 142, - VGPU10_OPCODE_DCL_STREAM = 143, - VGPU10_OPCODE_DCL_FUNCTION_BODY = 144, - VGPU10_OPCODE_DCL_FUNCTION_TABLE = 145, - VGPU10_OPCODE_DCL_INTERFACE = 146, - VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT = 147, - VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT = 148, - VGPU10_OPCODE_DCL_TESS_DOMAIN = 149, - VGPU10_OPCODE_DCL_TESS_PARTITIONING = 150, - VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE = 151, - VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR = 152, - VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT = 153, - VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT = 154, - VGPU10_OPCODE_DCL_THREAD_GROUP = 155, - VGPU10_OPCODE_DCL_UAV_TYPED = 156, - VGPU10_OPCODE_DCL_UAV_RAW = 157, - VGPU10_OPCODE_DCL_UAV_STRUCTURED = 158, - VGPU10_OPCODE_DCL_TGSM_RAW = 159, - VGPU10_OPCODE_DCL_TGSM_STRUCTURED = 160, - VGPU10_OPCODE_DCL_RESOURCE_RAW = 161, - VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED = 162, - VGPU10_OPCODE_LD_UAV_TYPED = 163, - VGPU10_OPCODE_STORE_UAV_TYPED = 164, - VGPU10_OPCODE_LD_RAW = 165, - VGPU10_OPCODE_STORE_RAW = 166, - VGPU10_OPCODE_LD_STRUCTURED = 167, - VGPU10_OPCODE_STORE_STRUCTURED = 168, - VGPU10_OPCODE_ATOMIC_AND = 169, - VGPU10_OPCODE_ATOMIC_OR = 170, - VGPU10_OPCODE_ATOMIC_XOR = 171, - VGPU10_OPCODE_ATOMIC_CMP_STORE = 172, - VGPU10_OPCODE_ATOMIC_IADD = 173, - VGPU10_OPCODE_ATOMIC_IMAX = 174, - VGPU10_OPCODE_ATOMIC_IMIN = 175, - VGPU10_OPCODE_ATOMIC_UMAX = 176, - VGPU10_OPCODE_ATOMIC_UMIN = 177, - VGPU10_OPCODE_IMM_ATOMIC_ALLOC = 178, - VGPU10_OPCODE_IMM_ATOMIC_CONSUME = 179, - VGPU10_OPCODE_IMM_ATOMIC_IADD = 180, - VGPU10_OPCODE_IMM_ATOMIC_AND = 181, - VGPU10_OPCODE_IMM_ATOMIC_OR = 182, - VGPU10_OPCODE_IMM_ATOMIC_XOR = 183, - VGPU10_OPCODE_IMM_ATOMIC_EXCH = 184, - VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH = 185, - VGPU10_OPCODE_IMM_ATOMIC_IMAX = 186, - VGPU10_OPCODE_IMM_ATOMIC_IMIN = 187, - VGPU10_OPCODE_IMM_ATOMIC_UMAX = 188, - VGPU10_OPCODE_IMM_ATOMIC_UMIN = 189, - VGPU10_OPCODE_SYNC = 190, - VGPU10_OPCODE_DADD = 191, - VGPU10_OPCODE_DMAX = 192, - VGPU10_OPCODE_DMIN = 193, - VGPU10_OPCODE_DMUL = 194, - VGPU10_OPCODE_DEQ = 195, - VGPU10_OPCODE_DGE = 196, - VGPU10_OPCODE_DLT = 197, - VGPU10_OPCODE_DNE = 198, - VGPU10_OPCODE_DMOV = 199, - VGPU10_OPCODE_DMOVC = 200, - VGPU10_OPCODE_DTOF = 201, - VGPU10_OPCODE_FTOD = 202, - VGPU10_OPCODE_EVAL_SNAPPED = 203, - VGPU10_OPCODE_EVAL_SAMPLE_INDEX = 204, - VGPU10_OPCODE_EVAL_CENTROID = 205, - VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT = 206, - VGPU10_OPCODE_ABORT = 207, - VGPU10_OPCODE_DEBUG_BREAK = 208, - - - VGPU10_OPCODE_RESERVED0 = 209, - VGPU10_OPCODE_DDIV = 210, - VGPU10_OPCODE_DFMA = 211, - VGPU10_OPCODE_DRCP = 212, - VGPU10_OPCODE_MSAD = 213, - VGPU10_OPCODE_DTOI = 214, - VGPU10_OPCODE_DTOU = 215, - VGPU10_OPCODE_ITOD = 216, - VGPU10_OPCODE_UTOD = 217, + VGPU10_OPCODE_RESERVED0 = 209, + VGPU10_OPCODE_DDIV = 210, + VGPU10_OPCODE_DFMA = 211, + VGPU10_OPCODE_DRCP = 212, + VGPU10_OPCODE_MSAD = 213, + VGPU10_OPCODE_DTOI = 214, + VGPU10_OPCODE_DTOU = 215, + VGPU10_OPCODE_ITOD = 216, + VGPU10_OPCODE_UTOD = 217, VGPU10_NUM_OPCODES } VGPU10_OPCODE_TYPE; - typedef enum { - VGPU10_VMWARE_OPCODE_IDIV = 0, - VGPU10_VMWARE_OPCODE_DFRC = 1, - VGPU10_VMWARE_OPCODE_DRSQ = 2, + VGPU10_VMWARE_OPCODE_IDIV = 0, + VGPU10_VMWARE_OPCODE_DFRC = 1, + VGPU10_VMWARE_OPCODE_DRSQ = 2, VGPU10_VMWARE_NUM_OPCODES } VGPU10_VMWARE_OPCODE_TYPE; @@ -331,22 +342,21 @@ typedef enum { } VGPU10_INTERPOLATION_MODE; typedef enum { - VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0, - VGPU10_RESOURCE_DIMENSION_BUFFER = 1, - VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2, - VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3, - VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4, - VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5, - VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6, - VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7, - VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8, - VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9, - VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10, + VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0, + VGPU10_RESOURCE_DIMENSION_BUFFER = 1, + VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2, + VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3, + VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4, + VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5, + VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6, + VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7, + VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8, + VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9, + VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10, - - VGPU10_RESOURCE_DIMENSION_RAW_BUFFER = 11, - VGPU10_RESOURCE_DIMENSION_STRUCTURED_BUFFER = 12, - VGPU10_RESOURCE_DIMENSION_MAX = 12 + VGPU10_RESOURCE_DIMENSION_RAW_BUFFER = 11, + VGPU10_RESOURCE_DIMENSION_STRUCTURED_BUFFER = 12, + VGPU10_RESOURCE_DIMENSION_MAX = 12 } VGPU10_RESOURCE_DIMENSION; typedef enum { @@ -356,227 +366,218 @@ typedef enum { } VGPU10_SAMPLER_MODE; typedef enum { - VGPU10_INSTRUCTION_TEST_ZERO = 0, - VGPU10_INSTRUCTION_TEST_NONZERO = 1 + VGPU10_INSTRUCTION_TEST_ZERO = 0, + VGPU10_INSTRUCTION_TEST_NONZERO = 1 } VGPU10_INSTRUCTION_TEST_BOOLEAN; typedef enum { - VGPU10_CB_IMMEDIATE_INDEXED = 0, - VGPU10_CB_DYNAMIC_INDEXED = 1 + VGPU10_CB_IMMEDIATE_INDEXED = 0, + VGPU10_CB_DYNAMIC_INDEXED = 1 } VGPU10_CB_ACCESS_PATTERN; typedef enum { - VGPU10_PRIMITIVE_UNDEFINED = 0, - VGPU10_PRIMITIVE_POINT = 1, - VGPU10_PRIMITIVE_LINE = 2, - VGPU10_PRIMITIVE_TRIANGLE = 3, - VGPU10_PRIMITIVE_LINE_ADJ = 6, + VGPU10_PRIMITIVE_UNDEFINED = 0, + VGPU10_PRIMITIVE_POINT = 1, + VGPU10_PRIMITIVE_LINE = 2, + VGPU10_PRIMITIVE_TRIANGLE = 3, + VGPU10_PRIMITIVE_LINE_ADJ = 6, VGPU10_PRIMITIVE_TRIANGLE_ADJ = 7, - VGPU10_PRIMITIVE_SM40_MAX = 7, + VGPU10_PRIMITIVE_SM40_MAX = 7, - - VGPU10_PRIMITIVE_1_CONTROL_POINT_PATCH = 8, - VGPU10_PRIMITIVE_2_CONTROL_POINT_PATCH = 9, - VGPU10_PRIMITIVE_3_CONTROL_POINT_PATCH = 10, - VGPU10_PRIMITIVE_4_CONTROL_POINT_PATCH = 11, - VGPU10_PRIMITIVE_5_CONTROL_POINT_PATCH = 12, - VGPU10_PRIMITIVE_6_CONTROL_POINT_PATCH = 13, - VGPU10_PRIMITIVE_7_CONTROL_POINT_PATCH = 14, - VGPU10_PRIMITIVE_8_CONTROL_POINT_PATCH = 15, - VGPU10_PRIMITIVE_9_CONTROL_POINT_PATCH = 16, - VGPU10_PRIMITIVE_10_CONTROL_POINT_PATCH = 17, - VGPU10_PRIMITIVE_11_CONTROL_POINT_PATCH = 18, - VGPU10_PRIMITIVE_12_CONTROL_POINT_PATCH = 19, - VGPU10_PRIMITIVE_13_CONTROL_POINT_PATCH = 20, - VGPU10_PRIMITIVE_14_CONTROL_POINT_PATCH = 21, - VGPU10_PRIMITIVE_15_CONTROL_POINT_PATCH = 22, - VGPU10_PRIMITIVE_16_CONTROL_POINT_PATCH = 23, - VGPU10_PRIMITIVE_17_CONTROL_POINT_PATCH = 24, - VGPU10_PRIMITIVE_18_CONTROL_POINT_PATCH = 25, - VGPU10_PRIMITIVE_19_CONTROL_POINT_PATCH = 26, - VGPU10_PRIMITIVE_20_CONTROL_POINT_PATCH = 27, - VGPU10_PRIMITIVE_21_CONTROL_POINT_PATCH = 28, - VGPU10_PRIMITIVE_22_CONTROL_POINT_PATCH = 29, - VGPU10_PRIMITIVE_23_CONTROL_POINT_PATCH = 30, - VGPU10_PRIMITIVE_24_CONTROL_POINT_PATCH = 31, - VGPU10_PRIMITIVE_25_CONTROL_POINT_PATCH = 32, - VGPU10_PRIMITIVE_26_CONTROL_POINT_PATCH = 33, - VGPU10_PRIMITIVE_27_CONTROL_POINT_PATCH = 34, - VGPU10_PRIMITIVE_28_CONTROL_POINT_PATCH = 35, - VGPU10_PRIMITIVE_29_CONTROL_POINT_PATCH = 36, - VGPU10_PRIMITIVE_30_CONTROL_POINT_PATCH = 37, - VGPU10_PRIMITIVE_31_CONTROL_POINT_PATCH = 38, - VGPU10_PRIMITIVE_32_CONTROL_POINT_PATCH = 39, - VGPU10_PRIMITIVE_MAX = 39 + VGPU10_PRIMITIVE_1_CONTROL_POINT_PATCH = 8, + VGPU10_PRIMITIVE_2_CONTROL_POINT_PATCH = 9, + VGPU10_PRIMITIVE_3_CONTROL_POINT_PATCH = 10, + VGPU10_PRIMITIVE_4_CONTROL_POINT_PATCH = 11, + VGPU10_PRIMITIVE_5_CONTROL_POINT_PATCH = 12, + VGPU10_PRIMITIVE_6_CONTROL_POINT_PATCH = 13, + VGPU10_PRIMITIVE_7_CONTROL_POINT_PATCH = 14, + VGPU10_PRIMITIVE_8_CONTROL_POINT_PATCH = 15, + VGPU10_PRIMITIVE_9_CONTROL_POINT_PATCH = 16, + VGPU10_PRIMITIVE_10_CONTROL_POINT_PATCH = 17, + VGPU10_PRIMITIVE_11_CONTROL_POINT_PATCH = 18, + VGPU10_PRIMITIVE_12_CONTROL_POINT_PATCH = 19, + VGPU10_PRIMITIVE_13_CONTROL_POINT_PATCH = 20, + VGPU10_PRIMITIVE_14_CONTROL_POINT_PATCH = 21, + VGPU10_PRIMITIVE_15_CONTROL_POINT_PATCH = 22, + VGPU10_PRIMITIVE_16_CONTROL_POINT_PATCH = 23, + VGPU10_PRIMITIVE_17_CONTROL_POINT_PATCH = 24, + VGPU10_PRIMITIVE_18_CONTROL_POINT_PATCH = 25, + VGPU10_PRIMITIVE_19_CONTROL_POINT_PATCH = 26, + VGPU10_PRIMITIVE_20_CONTROL_POINT_PATCH = 27, + VGPU10_PRIMITIVE_21_CONTROL_POINT_PATCH = 28, + VGPU10_PRIMITIVE_22_CONTROL_POINT_PATCH = 29, + VGPU10_PRIMITIVE_23_CONTROL_POINT_PATCH = 30, + VGPU10_PRIMITIVE_24_CONTROL_POINT_PATCH = 31, + VGPU10_PRIMITIVE_25_CONTROL_POINT_PATCH = 32, + VGPU10_PRIMITIVE_26_CONTROL_POINT_PATCH = 33, + VGPU10_PRIMITIVE_27_CONTROL_POINT_PATCH = 34, + VGPU10_PRIMITIVE_28_CONTROL_POINT_PATCH = 35, + VGPU10_PRIMITIVE_29_CONTROL_POINT_PATCH = 36, + VGPU10_PRIMITIVE_30_CONTROL_POINT_PATCH = 37, + VGPU10_PRIMITIVE_31_CONTROL_POINT_PATCH = 38, + VGPU10_PRIMITIVE_32_CONTROL_POINT_PATCH = 39, + VGPU10_PRIMITIVE_MAX = 39 } VGPU10_PRIMITIVE; typedef enum { - VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED = 0, - VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST = 1, - VGPU10_PRIMITIVE_TOPOLOGY_LINELIST = 2, - VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP = 3, - VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST = 4, - VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP = 5, - VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ = 10, - VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP_ADJ = 11, - VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ = 12, - VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ = 13 + VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED = 0, + VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST = 1, + VGPU10_PRIMITIVE_TOPOLOGY_LINELIST = 2, + VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP = 3, + VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST = 4, + VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP = 5, + VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ = 10, + VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP_ADJ = 11, + VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ = 12, + VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ = 13 } VGPU10_PRIMITIVE_TOPOLOGY; typedef enum { - VGPU10_CUSTOMDATA_COMMENT = 0, - VGPU10_CUSTOMDATA_DEBUGINFO = 1, - VGPU10_CUSTOMDATA_OPAQUE = 2, + VGPU10_CUSTOMDATA_COMMENT = 0, + VGPU10_CUSTOMDATA_DEBUGINFO = 1, + VGPU10_CUSTOMDATA_OPAQUE = 2, VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER = 3 } VGPU10_CUSTOMDATA_CLASS; typedef enum { - VGPU10_RESINFO_RETURN_FLOAT = 0, - VGPU10_RESINFO_RETURN_RCPFLOAT = 1, - VGPU10_RESINFO_RETURN_UINT = 2 + VGPU10_RESINFO_RETURN_FLOAT = 0, + VGPU10_RESINFO_RETURN_RCPFLOAT = 1, + VGPU10_RESINFO_RETURN_UINT = 2 } VGPU10_RESINFO_RETURN_TYPE; - typedef enum { - VGPU10_INSTRUCTION_RETURN_FLOAT = 0, - VGPU10_INSTRUCTION_RETURN_UINT = 1 + VGPU10_INSTRUCTION_RETURN_FLOAT = 0, + VGPU10_INSTRUCTION_RETURN_UINT = 1 } VGPU10_INSTRUCTION_RETURN_TYPE; - typedef enum { - VGPU10_TESSELLATOR_DOMAIN_UNDEFINED = 0, - VGPU10_TESSELLATOR_DOMAIN_ISOLINE = 1, - VGPU10_TESSELLATOR_DOMAIN_TRI = 2, - VGPU10_TESSELLATOR_DOMAIN_QUAD = 3, - VGPU10_TESSELLATOR_DOMAIN_MAX = 3 + VGPU10_TESSELLATOR_DOMAIN_UNDEFINED = 0, + VGPU10_TESSELLATOR_DOMAIN_ISOLINE = 1, + VGPU10_TESSELLATOR_DOMAIN_TRI = 2, + VGPU10_TESSELLATOR_DOMAIN_QUAD = 3, + VGPU10_TESSELLATOR_DOMAIN_MAX = 3 } VGPU10_TESSELLATOR_DOMAIN; - typedef enum { - VGPU10_TESSELLATOR_PARTITIONING_UNDEFINED = 0, - VGPU10_TESSELLATOR_PARTITIONING_INTEGER = 1, - VGPU10_TESSELLATOR_PARTITIONING_POW2 = 2, - VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_ODD = 3, - VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_EVEN = 4, - VGPU10_TESSELLATOR_PARTITIONING_MAX = 4 + VGPU10_TESSELLATOR_PARTITIONING_UNDEFINED = 0, + VGPU10_TESSELLATOR_PARTITIONING_INTEGER = 1, + VGPU10_TESSELLATOR_PARTITIONING_POW2 = 2, + VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_ODD = 3, + VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_EVEN = 4, + VGPU10_TESSELLATOR_PARTITIONING_MAX = 4 } VGPU10_TESSELLATOR_PARTITIONING; - typedef enum { - VGPU10_TESSELLATOR_OUTPUT_UNDEFINED = 0, - VGPU10_TESSELLATOR_OUTPUT_POINT = 1, - VGPU10_TESSELLATOR_OUTPUT_LINE = 2, - VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CW = 3, - VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CCW = 4, - VGPU10_TESSELLATOR_OUTPUT_MAX = 4 + VGPU10_TESSELLATOR_OUTPUT_UNDEFINED = 0, + VGPU10_TESSELLATOR_OUTPUT_POINT = 1, + VGPU10_TESSELLATOR_OUTPUT_LINE = 2, + VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CW = 3, + VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CCW = 4, + VGPU10_TESSELLATOR_OUTPUT_MAX = 4 } VGPU10_TESSELLATOR_OUTPUT_PRIMITIVE; typedef union { struct { - unsigned int opcodeType : 11; - unsigned int interpolationMode : 4; - unsigned int : 3; - unsigned int testBoolean : 1; - unsigned int preciseValues : 4; - unsigned int : 1; - unsigned int instructionLength : 7; - unsigned int extended : 1; + unsigned int opcodeType : 11; + unsigned int interpolationMode : 4; + unsigned int : 3; + unsigned int testBoolean : 1; + unsigned int preciseValues : 4; + unsigned int : 1; + unsigned int instructionLength : 7; + unsigned int extended : 1; }; struct { - unsigned int : 11; - unsigned int vmwareOpcodeType : 4; + unsigned int : 11; + unsigned int vmwareOpcodeType : 4; }; struct { - unsigned int : 11; - unsigned int resourceDimension : 5; - unsigned int sampleCount : 7; + unsigned int : 11; + unsigned int resourceDimension : 5; + unsigned int sampleCount : 7; }; struct { - unsigned int : 11; - unsigned int samplerMode : 4; + unsigned int : 11; + unsigned int samplerMode : 4; }; struct { - unsigned int : 11; - unsigned int accessPattern : 1; + unsigned int : 11; + unsigned int accessPattern : 1; }; struct { - unsigned int : 11; - unsigned int primitive : 6; + unsigned int : 11; + unsigned int primitive : 6; }; struct { - unsigned int : 11; - unsigned int primitiveTopology : 7; + unsigned int : 11; + unsigned int primitiveTopology : 7; }; struct { - unsigned int : 11; - unsigned int customDataClass : 21; + unsigned int : 11; + unsigned int customDataClass : 21; }; struct { - unsigned int : 11; - unsigned int resinfoReturnType : 2; - unsigned int saturate : 1; + unsigned int : 11; + unsigned int resinfoReturnType : 2; + unsigned int saturate : 1; }; struct { - unsigned int : 11; - unsigned int refactoringAllowed : 1; + unsigned int : 11; + unsigned int refactoringAllowed : 1; - - unsigned int enableDoublePrecisionFloatOps : 1; - unsigned int forceEarlyDepthStencil : 1; - unsigned int enableRawAndStructuredBuffers : 1; + unsigned int enableDoublePrecisionFloatOps : 1; + unsigned int forceEarlyDepthStencil : 1; + unsigned int enableRawAndStructuredBuffers : 1; }; struct { - unsigned int : 11; - unsigned int instReturnType : 2; + unsigned int : 11; + unsigned int instReturnType : 2; }; - struct { - unsigned int : 11; - unsigned int syncThreadsInGroup : 1; - unsigned int syncThreadGroupShared : 1; - unsigned int syncUAVMemoryGroup : 1; - unsigned int syncUAVMemoryGlobal : 1; + unsigned int : 11; + unsigned int syncThreadsInGroup : 1; + unsigned int syncThreadGroupShared : 1; + unsigned int syncUAVMemoryGroup : 1; + unsigned int syncUAVMemoryGlobal : 1; }; struct { - unsigned int : 11; - unsigned int controlPointCount : 6; + unsigned int : 11; + unsigned int controlPointCount : 6; }; struct { - unsigned int : 11; - unsigned int tessDomain : 2; + unsigned int : 11; + unsigned int tessDomain : 2; }; struct { - unsigned int : 11; - unsigned int tessPartitioning : 3; + unsigned int : 11; + unsigned int tessPartitioning : 3; }; struct { unsigned int : 11; unsigned int tessOutputPrimitive : 3; }; struct { - unsigned int : 11; - unsigned int interfaceIndexedDynamically : 1; + unsigned int : 11; + unsigned int interfaceIndexedDynamically : 1; }; struct { - unsigned int : 11; - unsigned int uavResourceDimension : 5; - unsigned int globallyCoherent : 1; - unsigned int : 6; - unsigned int uavHasCounter : 1; + unsigned int : 11; + unsigned int uavResourceDimension : 5; + unsigned int globallyCoherent : 1; + unsigned int : 6; + unsigned int uavHasCounter : 1; }; uint32 value; } VGPU10OpcodeToken0; - typedef enum { - VGPU10_EXTENDED_OPCODE_EMPTY = 0, - VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS = 1, + VGPU10_EXTENDED_OPCODE_EMPTY = 0, + VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS = 1, - - VGPU10_EXTENDED_OPCODE_RESOURCE_DIM = 2, - VGPU10_EXTENDED_OPCODE_RESOURCE_RETURN_TYPE = 3 + VGPU10_EXTENDED_OPCODE_RESOURCE_DIM = 2, + VGPU10_EXTENDED_OPCODE_RESOURCE_RETURN_TYPE = 3 } VGPU10_EXTENDED_OPCODE_TYPE; typedef union { @@ -590,10 +591,9 @@ typedef union { unsigned int extended : 1; }; - struct { - unsigned int : 6; - unsigned int resourceDimension : 5; + unsigned int : 6; + unsigned int resourceDimension : 5; }; struct { unsigned int : 6; @@ -605,7 +605,6 @@ typedef union { uint32 value; } VGPU10OpcodeToken1; - typedef enum { VGPU10_OPERAND_0_COMPONENT = 0, VGPU10_OPERAND_1_COMPONENT = 1, @@ -619,25 +618,36 @@ typedef enum { VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE = 2 } VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE; -#define VGPU10_OPERAND_4_COMPONENT_MASK_X 0x1 -#define VGPU10_OPERAND_4_COMPONENT_MASK_Y 0x2 -#define VGPU10_OPERAND_4_COMPONENT_MASK_Z 0x4 -#define VGPU10_OPERAND_4_COMPONENT_MASK_W 0x8 +#define VGPU10_OPERAND_4_COMPONENT_MASK_X 0x1 +#define VGPU10_OPERAND_4_COMPONENT_MASK_Y 0x2 +#define VGPU10_OPERAND_4_COMPONENT_MASK_Z 0x4 +#define VGPU10_OPERAND_4_COMPONENT_MASK_W 0x8 -#define VGPU10_OPERAND_4_COMPONENT_MASK_XY (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Y) -#define VGPU10_OPERAND_4_COMPONENT_MASK_XZ (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Z) -#define VGPU10_OPERAND_4_COMPONENT_MASK_XW (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_W) -#define VGPU10_OPERAND_4_COMPONENT_MASK_YZ (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_Z) -#define VGPU10_OPERAND_4_COMPONENT_MASK_YW (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_W) -#define VGPU10_OPERAND_4_COMPONENT_MASK_ZW (VGPU10_OPERAND_4_COMPONENT_MASK_Z | VGPU10_OPERAND_4_COMPONENT_MASK_W) -#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZ (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_Z) -#define VGPU10_OPERAND_4_COMPONENT_MASK_XYW (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_W) -#define VGPU10_OPERAND_4_COMPONENT_MASK_XZW (VGPU10_OPERAND_4_COMPONENT_MASK_XZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) -#define VGPU10_OPERAND_4_COMPONENT_MASK_YZW (VGPU10_OPERAND_4_COMPONENT_MASK_YZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) -#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZW (VGPU10_OPERAND_4_COMPONENT_MASK_XYZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) -#define VGPU10_OPERAND_4_COMPONENT_MASK_ALL VGPU10_OPERAND_4_COMPONENT_MASK_XYZW +#define VGPU10_OPERAND_4_COMPONENT_MASK_XY \ + (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Y) +#define VGPU10_OPERAND_4_COMPONENT_MASK_XZ \ + (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Z) +#define VGPU10_OPERAND_4_COMPONENT_MASK_XW \ + (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_W) +#define VGPU10_OPERAND_4_COMPONENT_MASK_YZ \ + (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_Z) +#define VGPU10_OPERAND_4_COMPONENT_MASK_YW \ + (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_W) +#define VGPU10_OPERAND_4_COMPONENT_MASK_ZW \ + (VGPU10_OPERAND_4_COMPONENT_MASK_Z | VGPU10_OPERAND_4_COMPONENT_MASK_W) +#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZ \ + (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_Z) +#define VGPU10_OPERAND_4_COMPONENT_MASK_XYW \ + (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_W) +#define VGPU10_OPERAND_4_COMPONENT_MASK_XZW \ + (VGPU10_OPERAND_4_COMPONENT_MASK_XZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) +#define VGPU10_OPERAND_4_COMPONENT_MASK_YZW \ + (VGPU10_OPERAND_4_COMPONENT_MASK_YZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) +#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZW \ + (VGPU10_OPERAND_4_COMPONENT_MASK_XYZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) +#define VGPU10_OPERAND_4_COMPONENT_MASK_ALL VGPU10_OPERAND_4_COMPONENT_MASK_XYZW -#define VGPU10_REGISTER_INDEX_FROM_SEMANTIC 0xffffffff +#define VGPU10_REGISTER_INDEX_FROM_SEMANTIC 0xffffffff typedef enum { VGPU10_COMPONENT_X = 0, @@ -647,54 +657,52 @@ typedef enum { } VGPU10_COMPONENT_NAME; typedef enum { - VGPU10_OPERAND_TYPE_TEMP = 0, - VGPU10_OPERAND_TYPE_INPUT = 1, - VGPU10_OPERAND_TYPE_OUTPUT = 2, - VGPU10_OPERAND_TYPE_INDEXABLE_TEMP = 3, - VGPU10_OPERAND_TYPE_IMMEDIATE32 = 4, - VGPU10_OPERAND_TYPE_IMMEDIATE64 = 5, - VGPU10_OPERAND_TYPE_SAMPLER = 6, - VGPU10_OPERAND_TYPE_RESOURCE = 7, - VGPU10_OPERAND_TYPE_CONSTANT_BUFFER = 8, - VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER = 9, - VGPU10_OPERAND_TYPE_LABEL = 10, - VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID = 11, - VGPU10_OPERAND_TYPE_OUTPUT_DEPTH = 12, - VGPU10_OPERAND_TYPE_NULL = 13, - VGPU10_OPERAND_TYPE_SM40_MAX = 13, + VGPU10_OPERAND_TYPE_TEMP = 0, + VGPU10_OPERAND_TYPE_INPUT = 1, + VGPU10_OPERAND_TYPE_OUTPUT = 2, + VGPU10_OPERAND_TYPE_INDEXABLE_TEMP = 3, + VGPU10_OPERAND_TYPE_IMMEDIATE32 = 4, + VGPU10_OPERAND_TYPE_IMMEDIATE64 = 5, + VGPU10_OPERAND_TYPE_SAMPLER = 6, + VGPU10_OPERAND_TYPE_RESOURCE = 7, + VGPU10_OPERAND_TYPE_CONSTANT_BUFFER = 8, + VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER = 9, + VGPU10_OPERAND_TYPE_LABEL = 10, + VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID = 11, + VGPU10_OPERAND_TYPE_OUTPUT_DEPTH = 12, + VGPU10_OPERAND_TYPE_NULL = 13, + VGPU10_OPERAND_TYPE_SM40_MAX = 13, + VGPU10_OPERAND_TYPE_RASTERIZER = 14, + VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15, + VGPU10_OPERAND_TYPE_SM41_MAX = 15, - VGPU10_OPERAND_TYPE_RASTERIZER = 14, - VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15, - VGPU10_OPERAND_TYPE_SM41_MAX = 15, - - - VGPU10_OPERAND_TYPE_STREAM = 16, - VGPU10_OPERAND_TYPE_FUNCTION_BODY = 17, - VGPU10_OPERAND_TYPE_FUNCTION_TABLE = 18, - VGPU10_OPERAND_TYPE_INTERFACE = 19, - VGPU10_OPERAND_TYPE_FUNCTION_INPUT = 20, - VGPU10_OPERAND_TYPE_FUNCTION_OUTPUT = 21, - VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID = 22, - VGPU10_OPERAND_TYPE_INPUT_FORK_INSTANCE_ID = 23, - VGPU10_OPERAND_TYPE_INPUT_JOIN_INSTANCE_ID = 24, - VGPU10_OPERAND_TYPE_INPUT_CONTROL_POINT = 25, - VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT = 26, - VGPU10_OPERAND_TYPE_INPUT_PATCH_CONSTANT = 27, - VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT = 28, - VGPU10_OPERAND_TYPE_THIS_POINTER = 29, - VGPU10_OPERAND_TYPE_UAV = 30, - VGPU10_OPERAND_TYPE_THREAD_GROUP_SHARED_MEMORY = 31, - VGPU10_OPERAND_TYPE_INPUT_THREAD_ID = 32, - VGPU10_OPERAND_TYPE_INPUT_THREAD_GROUP_ID = 33, - VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP = 34, - VGPU10_OPERAND_TYPE_INPUT_COVERAGE_MASK = 35, - VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP_FLATTENED = 36, - VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID = 37, - VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_GREATER_EQUAL = 38, - VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_LESS_EQUAL = 39, - VGPU10_OPERAND_TYPE_CYCLE_COUNTER = 40, - VGPU10_OPERAND_TYPE_SM50_MAX = 40, + VGPU10_OPERAND_TYPE_STREAM = 16, + VGPU10_OPERAND_TYPE_FUNCTION_BODY = 17, + VGPU10_OPERAND_TYPE_FUNCTION_TABLE = 18, + VGPU10_OPERAND_TYPE_INTERFACE = 19, + VGPU10_OPERAND_TYPE_FUNCTION_INPUT = 20, + VGPU10_OPERAND_TYPE_FUNCTION_OUTPUT = 21, + VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID = 22, + VGPU10_OPERAND_TYPE_INPUT_FORK_INSTANCE_ID = 23, + VGPU10_OPERAND_TYPE_INPUT_JOIN_INSTANCE_ID = 24, + VGPU10_OPERAND_TYPE_INPUT_CONTROL_POINT = 25, + VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT = 26, + VGPU10_OPERAND_TYPE_INPUT_PATCH_CONSTANT = 27, + VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT = 28, + VGPU10_OPERAND_TYPE_THIS_POINTER = 29, + VGPU10_OPERAND_TYPE_UAV = 30, + VGPU10_OPERAND_TYPE_THREAD_GROUP_SHARED_MEMORY = 31, + VGPU10_OPERAND_TYPE_INPUT_THREAD_ID = 32, + VGPU10_OPERAND_TYPE_INPUT_THREAD_GROUP_ID = 33, + VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP = 34, + VGPU10_OPERAND_TYPE_INPUT_COVERAGE_MASK = 35, + VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP_FLATTENED = 36, + VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID = 37, + VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_GREATER_EQUAL = 38, + VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_LESS_EQUAL = 39, + VGPU10_OPERAND_TYPE_CYCLE_COUNTER = 40, + VGPU10_OPERAND_TYPE_SM50_MAX = 40, VGPU10_NUM_OPERANDS } VGPU10_OPERAND_TYPE; @@ -716,32 +724,31 @@ typedef enum { typedef union { struct { - unsigned int numComponents : 2; - unsigned int selectionMode : 2; - unsigned int mask : 4; - unsigned int : 4; - unsigned int operandType : 8; - unsigned int indexDimension : 2; - unsigned int index0Representation : 3; - unsigned int index1Representation : 3; - unsigned int : 3; - unsigned int extended : 1; + unsigned int numComponents : 2; + unsigned int selectionMode : 2; + unsigned int mask : 4; + unsigned int : 4; + unsigned int operandType : 8; + unsigned int indexDimension : 2; + unsigned int index0Representation : 3; + unsigned int index1Representation : 3; + unsigned int : 3; + unsigned int extended : 1; }; struct { - unsigned int : 4; - unsigned int swizzleX : 2; - unsigned int swizzleY : 2; - unsigned int swizzleZ : 2; - unsigned int swizzleW : 2; + unsigned int : 4; + unsigned int swizzleX : 2; + unsigned int swizzleY : 2; + unsigned int swizzleZ : 2; + unsigned int swizzleW : 2; }; struct { - unsigned int : 4; - unsigned int selectMask : 2; + unsigned int : 4; + unsigned int selectMask : 2; }; uint32 value; } VGPU10OperandToken0; - typedef enum { VGPU10_EXTENDED_OPERAND_EMPTY = 0, VGPU10_EXTENDED_OPERAND_MODIFIER = 1 @@ -764,24 +771,22 @@ typedef union { uint32 value; } VGPU10OperandToken1; - typedef enum { - VGPU10_RETURN_TYPE_MIN = 1, + VGPU10_RETURN_TYPE_MIN = 1, - VGPU10_RETURN_TYPE_UNORM = 1, - VGPU10_RETURN_TYPE_SNORM = 2, - VGPU10_RETURN_TYPE_SINT = 3, - VGPU10_RETURN_TYPE_UINT = 4, - VGPU10_RETURN_TYPE_FLOAT = 5, - VGPU10_RETURN_TYPE_MIXED = 6, + VGPU10_RETURN_TYPE_UNORM = 1, + VGPU10_RETURN_TYPE_SNORM = 2, + VGPU10_RETURN_TYPE_SINT = 3, + VGPU10_RETURN_TYPE_UINT = 4, + VGPU10_RETURN_TYPE_FLOAT = 5, + VGPU10_RETURN_TYPE_MIXED = 6, VGPU10_RETURN_TYPE_SM40_MAX = 6, + VGPU10_RETURN_TYPE_DOUBLE = 7, + VGPU10_RETURN_TYPE_CONTINUED = 8, + VGPU10_RETURN_TYPE_UNUSED = 9, - VGPU10_RETURN_TYPE_DOUBLE = 7, - VGPU10_RETURN_TYPE_CONTINUED = 8, - VGPU10_RETURN_TYPE_UNUSED = 9, - - VGPU10_RETURN_TYPE_MAX = 9 + VGPU10_RETURN_TYPE_MAX = 9 } VGPU10_RESOURCE_RETURN_TYPE; typedef union { @@ -794,38 +799,36 @@ typedef union { uint32 value; } VGPU10ResourceReturnTypeToken; - typedef enum { - VGPU10_NAME_MIN = 0, + VGPU10_NAME_MIN = 0, - VGPU10_NAME_UNDEFINED = 0, - VGPU10_NAME_POSITION = 1, - VGPU10_NAME_CLIP_DISTANCE = 2, - VGPU10_NAME_CULL_DISTANCE = 3, - VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX = 4, - VGPU10_NAME_VIEWPORT_ARRAY_INDEX = 5, - VGPU10_NAME_VERTEX_ID = 6, - VGPU10_NAME_PRIMITIVE_ID = 7, - VGPU10_NAME_INSTANCE_ID = 8, - VGPU10_NAME_IS_FRONT_FACE = 9, - VGPU10_NAME_SAMPLE_INDEX = 10, - VGPU10_NAME_SM40_MAX = 10, + VGPU10_NAME_UNDEFINED = 0, + VGPU10_NAME_POSITION = 1, + VGPU10_NAME_CLIP_DISTANCE = 2, + VGPU10_NAME_CULL_DISTANCE = 3, + VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX = 4, + VGPU10_NAME_VIEWPORT_ARRAY_INDEX = 5, + VGPU10_NAME_VERTEX_ID = 6, + VGPU10_NAME_PRIMITIVE_ID = 7, + VGPU10_NAME_INSTANCE_ID = 8, + VGPU10_NAME_IS_FRONT_FACE = 9, + VGPU10_NAME_SAMPLE_INDEX = 10, + VGPU10_NAME_SM40_MAX = 10, + VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR = 11, + VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR = 12, + VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR = 13, + VGPU10_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR = 14, + VGPU10_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR = 15, + VGPU10_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR = 16, + VGPU10_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR = 17, + VGPU10_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR = 18, + VGPU10_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR = 19, + VGPU10_NAME_FINAL_TRI_INSIDE_TESSFACTOR = 20, + VGPU10_NAME_FINAL_LINE_DETAIL_TESSFACTOR = 21, + VGPU10_NAME_FINAL_LINE_DENSITY_TESSFACTOR = 22, - VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR = 11, - VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR = 12, - VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR = 13, - VGPU10_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR = 14, - VGPU10_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR = 15, - VGPU10_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR = 16, - VGPU10_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR = 17, - VGPU10_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR = 18, - VGPU10_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR = 19, - VGPU10_NAME_FINAL_TRI_INSIDE_TESSFACTOR = 20, - VGPU10_NAME_FINAL_LINE_DETAIL_TESSFACTOR = 21, - VGPU10_NAME_FINAL_LINE_DENSITY_TESSFACTOR = 22, - - VGPU10_NAME_MAX = 22 + VGPU10_NAME_MAX = 22 } VGPU10_SYSTEM_NAME; typedef union { @@ -835,4 +838,8 @@ typedef union { uint32 value; } VGPU10NameToken; +#ifdef __cplusplus +} +#endif + #endif diff --git a/src/gallium/drivers/svga/include/includeCheck.h b/src/gallium/drivers/svga/include/includeCheck.h deleted file mode 100644 index f1839f03c8e..00000000000 --- a/src/gallium/drivers/svga/include/includeCheck.h +++ /dev/null @@ -1 +0,0 @@ -/* dummy file */ diff --git a/src/gallium/drivers/svga/include/svga3d_caps.h b/src/gallium/drivers/svga/include/svga3d_caps.h deleted file mode 100644 index a02391917b3..00000000000 --- a/src/gallium/drivers/svga/include/svga3d_caps.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2007-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT - */ - -/* - * svga3d_caps.h -- - * - * Definitions for SVGA3D hardware capabilities. Capabilities - * are used to query for optional rendering features during - * driver initialization. The capability data is stored as very - * basic key/value dictionary within the "FIFO register" memory - * area at the beginning of BAR2. - * - * Note that these definitions are only for 3D capabilities. - * The SVGA device also has "device capabilities" and "FIFO - * capabilities", which are non-3D-specific and are stored as - * bitfields rather than key/value pairs. - */ - -#ifndef _SVGA3D_CAPS_H_ -#define _SVGA3D_CAPS_H_ - -#define INCLUDE_ALLOW_MODULE -#define INCLUDE_ALLOW_USERLEVEL - -#include "includeCheck.h" - -#include -#include "svga_reg.h" - -#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \ - SVGA_FIFO_3D_CAPS + 1) - - -/* - * SVGA3dCapsRecordType - * - * Record types that can be found in the caps block. - * Related record types are grouped together numerically so that - * SVGA3dCaps_FindRecord() can be applied on a range of record - * types. - */ - -typedef enum { - SVGA3DCAPS_RECORD_UNKNOWN = 0, - SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100, - SVGA3DCAPS_RECORD_DEVCAPS = 0x100, - SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff, -} SVGA3dCapsRecordType; - - -/* - * SVGA3dCapsRecordHeader - * - * Header field leading each caps block record. Contains the offset (in - * register words, NOT bytes) to the next caps block record (or the end - * of caps block records which will be a zero word) and the record type - * as defined above. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCapsRecordHeader { - uint32 length; - SVGA3dCapsRecordType type; -} -#include "vmware_pack_end.h" -SVGA3dCapsRecordHeader; - - -/* - * SVGA3dCapsRecord - * - * Caps block record; "data" is a placeholder for the actual data structure - * contained within the record; for example a record containing a FOOBAR - * structure would be of size "sizeof(SVGA3dCapsRecordHeader) + - * sizeof(FOOBAR)". - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCapsRecord { - SVGA3dCapsRecordHeader header; - uint32 data[1]; -} -#include "vmware_pack_end.h" -SVGA3dCapsRecord; - - -typedef uint32 SVGA3dCapPair[2]; - - -#endif diff --git a/src/gallium/drivers/svga/include/svga3d_cmd.h b/src/gallium/drivers/svga/include/svga3d_cmd.h index 6fa9a699c45..73d9a65af1d 100644 --- a/src/gallium/drivers/svga/include/svga3d_cmd.h +++ b/src/gallium/drivers/svga/include/svga3d_cmd.h @@ -1,1297 +1,884 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2012-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2012-2022 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* * svga3d_cmd.h -- * - * SVGA 3d hardware cmd definitions + * SVGA 3d hardware cmd definitions */ #ifndef _SVGA3D_CMD_H_ #define _SVGA3D_CMD_H_ -#define INCLUDE_ALLOW_MODULE -#define INCLUDE_ALLOW_USERLEVEL -#define INCLUDE_ALLOW_VMCORE - -#include "includeCheck.h" -#include "svga3d_types.h" #include "svga3d_limits.h" +#include "svga3d_types.h" #include "svga_reg.h" -/* - * Identifiers for commands in the command FIFO. - * - * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of - * the SVGA3D protocol and remain reserved; they should not be used in the - * future. - * - * IDs between 1040 and 2999 (inclusive) are available for use by the - * current SVGA3D protocol. - * - * FIFO clients other than SVGA3D should stay below 1000, or at 3000 - * and up. - */ +typedef enum SVGAFifo3dCmdId { + SVGA_3D_CMD_LEGACY_BASE = 1000, + SVGA_3D_CMD_BASE = 1040, -typedef enum { - SVGA_3D_CMD_LEGACY_BASE = 1000, - SVGA_3D_CMD_BASE = 1040, + SVGA_3D_CMD_SURFACE_DEFINE = 1040, + SVGA_3D_CMD_SURFACE_DESTROY = 1041, + SVGA_3D_CMD_SURFACE_COPY = 1042, + SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043, + SVGA_3D_CMD_SURFACE_DMA = 1044, + SVGA_3D_CMD_CONTEXT_DEFINE = 1045, + SVGA_3D_CMD_CONTEXT_DESTROY = 1046, + SVGA_3D_CMD_SETTRANSFORM = 1047, + SVGA_3D_CMD_SETZRANGE = 1048, + SVGA_3D_CMD_SETRENDERSTATE = 1049, + SVGA_3D_CMD_SETRENDERTARGET = 1050, + SVGA_3D_CMD_SETTEXTURESTATE = 1051, + SVGA_3D_CMD_SETMATERIAL = 1052, + SVGA_3D_CMD_SETLIGHTDATA = 1053, + SVGA_3D_CMD_SETLIGHTENABLED = 1054, + SVGA_3D_CMD_SETVIEWPORT = 1055, + SVGA_3D_CMD_SETCLIPPLANE = 1056, + SVGA_3D_CMD_CLEAR = 1057, + SVGA_3D_CMD_PRESENT = 1058, + SVGA_3D_CMD_SHADER_DEFINE = 1059, + SVGA_3D_CMD_SHADER_DESTROY = 1060, + SVGA_3D_CMD_SET_SHADER = 1061, + SVGA_3D_CMD_SET_SHADER_CONST = 1062, + SVGA_3D_CMD_DRAW_PRIMITIVES = 1063, + SVGA_3D_CMD_SETSCISSORRECT = 1064, + SVGA_3D_CMD_BEGIN_QUERY = 1065, + SVGA_3D_CMD_END_QUERY = 1066, + SVGA_3D_CMD_WAIT_FOR_QUERY = 1067, + SVGA_3D_CMD_PRESENT_READBACK = 1068, + SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069, + SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070, + SVGA_3D_CMD_GENERATE_MIPMAPS = 1071, + SVGA_3D_CMD_DEAD4 = 1072, + SVGA_3D_CMD_DEAD5 = 1073, + SVGA_3D_CMD_DEAD6 = 1074, + SVGA_3D_CMD_DEAD7 = 1075, + SVGA_3D_CMD_DEAD8 = 1076, + SVGA_3D_CMD_DEAD9 = 1077, + SVGA_3D_CMD_DEAD10 = 1078, + SVGA_3D_CMD_DEAD11 = 1079, + SVGA_3D_CMD_ACTIVATE_SURFACE = 1080, + SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081, + SVGA_3D_CMD_SCREEN_DMA = 1082, + SVGA_3D_CMD_DEAD1 = 1083, + SVGA_3D_CMD_DEAD2 = 1084, - SVGA_3D_CMD_SURFACE_DEFINE = 1040, - SVGA_3D_CMD_SURFACE_DESTROY = 1041, - SVGA_3D_CMD_SURFACE_COPY = 1042, - SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043, - SVGA_3D_CMD_SURFACE_DMA = 1044, - SVGA_3D_CMD_CONTEXT_DEFINE = 1045, - SVGA_3D_CMD_CONTEXT_DESTROY = 1046, - SVGA_3D_CMD_SETTRANSFORM = 1047, - SVGA_3D_CMD_SETZRANGE = 1048, - SVGA_3D_CMD_SETRENDERSTATE = 1049, - SVGA_3D_CMD_SETRENDERTARGET = 1050, - SVGA_3D_CMD_SETTEXTURESTATE = 1051, - SVGA_3D_CMD_SETMATERIAL = 1052, - SVGA_3D_CMD_SETLIGHTDATA = 1053, - SVGA_3D_CMD_SETLIGHTENABLED = 1054, - SVGA_3D_CMD_SETVIEWPORT = 1055, - SVGA_3D_CMD_SETCLIPPLANE = 1056, - SVGA_3D_CMD_CLEAR = 1057, - SVGA_3D_CMD_PRESENT = 1058, - SVGA_3D_CMD_SHADER_DEFINE = 1059, - SVGA_3D_CMD_SHADER_DESTROY = 1060, - SVGA_3D_CMD_SET_SHADER = 1061, - SVGA_3D_CMD_SET_SHADER_CONST = 1062, - SVGA_3D_CMD_DRAW_PRIMITIVES = 1063, - SVGA_3D_CMD_SETSCISSORRECT = 1064, - SVGA_3D_CMD_BEGIN_QUERY = 1065, - SVGA_3D_CMD_END_QUERY = 1066, - SVGA_3D_CMD_WAIT_FOR_QUERY = 1067, - SVGA_3D_CMD_PRESENT_READBACK = 1068, - SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069, - SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070, - SVGA_3D_CMD_GENERATE_MIPMAPS = 1071, - SVGA_3D_CMD_DEAD4 = 1072, - SVGA_3D_CMD_DEAD5 = 1073, - SVGA_3D_CMD_DEAD6 = 1074, - SVGA_3D_CMD_DEAD7 = 1075, - SVGA_3D_CMD_DEAD8 = 1076, - SVGA_3D_CMD_DEAD9 = 1077, - SVGA_3D_CMD_DEAD10 = 1078, - SVGA_3D_CMD_DEAD11 = 1079, - SVGA_3D_CMD_ACTIVATE_SURFACE = 1080, - SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081, - SVGA_3D_CMD_SCREEN_DMA = 1082, - SVGA_3D_CMD_DEAD1 = 1083, - SVGA_3D_CMD_DEAD2 = 1084, + SVGA_3D_CMD_DEAD12 = 1085, + SVGA_3D_CMD_DEAD13 = 1086, + SVGA_3D_CMD_DEAD14 = 1087, + SVGA_3D_CMD_DEAD15 = 1088, + SVGA_3D_CMD_DEAD16 = 1089, + SVGA_3D_CMD_DEAD17 = 1090, - SVGA_3D_CMD_DEAD12 = 1085, - SVGA_3D_CMD_DEAD13 = 1086, - SVGA_3D_CMD_DEAD14 = 1087, - SVGA_3D_CMD_DEAD15 = 1088, - SVGA_3D_CMD_DEAD16 = 1089, - SVGA_3D_CMD_DEAD17 = 1090, + SVGA_3D_CMD_SET_OTABLE_BASE = 1091, + SVGA_3D_CMD_READBACK_OTABLE = 1092, - SVGA_3D_CMD_SET_OTABLE_BASE = 1091, - SVGA_3D_CMD_READBACK_OTABLE = 1092, + SVGA_3D_CMD_DEFINE_GB_MOB = 1093, + SVGA_3D_CMD_DESTROY_GB_MOB = 1094, + SVGA_3D_CMD_DEAD3 = 1095, + SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096, - SVGA_3D_CMD_DEFINE_GB_MOB = 1093, - SVGA_3D_CMD_DESTROY_GB_MOB = 1094, - SVGA_3D_CMD_DEAD3 = 1095, - SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096, + SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097, + SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098, + SVGA_3D_CMD_BIND_GB_SURFACE = 1099, + SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100, + SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101, + SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102, + SVGA_3D_CMD_READBACK_GB_IMAGE = 1103, + SVGA_3D_CMD_READBACK_GB_SURFACE = 1104, + SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105, + SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106, - SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097, - SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098, - SVGA_3D_CMD_BIND_GB_SURFACE = 1099, - SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100, - SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101, - SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102, - SVGA_3D_CMD_READBACK_GB_IMAGE = 1103, - SVGA_3D_CMD_READBACK_GB_SURFACE = 1104, - SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105, - SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106, + SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107, + SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108, + SVGA_3D_CMD_BIND_GB_CONTEXT = 1109, + SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110, + SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111, - SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107, - SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108, - SVGA_3D_CMD_BIND_GB_CONTEXT = 1109, - SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110, - SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111, + SVGA_3D_CMD_DEFINE_GB_SHADER = 1112, + SVGA_3D_CMD_DESTROY_GB_SHADER = 1113, + SVGA_3D_CMD_BIND_GB_SHADER = 1114, - SVGA_3D_CMD_DEFINE_GB_SHADER = 1112, - SVGA_3D_CMD_DESTROY_GB_SHADER = 1113, - SVGA_3D_CMD_BIND_GB_SHADER = 1114, + SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115, - SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115, + SVGA_3D_CMD_BEGIN_GB_QUERY = 1116, + SVGA_3D_CMD_END_GB_QUERY = 1117, + SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118, - SVGA_3D_CMD_BEGIN_GB_QUERY = 1116, - SVGA_3D_CMD_END_GB_QUERY = 1117, - SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118, + SVGA_3D_CMD_NOP = 1119, - SVGA_3D_CMD_NOP = 1119, + SVGA_3D_CMD_ENABLE_GART = 1120, + SVGA_3D_CMD_DISABLE_GART = 1121, + SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122, + SVGA_3D_CMD_UNMAP_GART_RANGE = 1123, - SVGA_3D_CMD_ENABLE_GART = 1120, - SVGA_3D_CMD_DISABLE_GART = 1121, - SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122, - SVGA_3D_CMD_UNMAP_GART_RANGE = 1123, + SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124, + SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125, + SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126, + SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127, - SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124, - SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125, - SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126, - SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127, + SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128, + SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129, - SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128, - SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129, + SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130, - SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130, + SVGA_3D_CMD_GB_SCREEN_DMA = 1131, + SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132, + SVGA_3D_CMD_GB_MOB_FENCE = 1133, + SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134, + SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135, + SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136, + SVGA_3D_CMD_NOP_ERROR = 1137, - SVGA_3D_CMD_GB_SCREEN_DMA = 1131, - SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132, - SVGA_3D_CMD_GB_MOB_FENCE = 1133, - SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134, - SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135, - SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136, - SVGA_3D_CMD_NOP_ERROR = 1137, + SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138, + SVGA_3D_CMD_SET_VERTEX_DECLS = 1139, + SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140, + SVGA_3D_CMD_DRAW = 1141, + SVGA_3D_CMD_DRAW_INDEXED = 1142, - SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138, - SVGA_3D_CMD_SET_VERTEX_DECLS = 1139, - SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140, - SVGA_3D_CMD_DRAW = 1141, - SVGA_3D_CMD_DRAW_INDEXED = 1142, + SVGA_3D_CMD_DX_MIN = 1143, + SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143, + SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144, + SVGA_3D_CMD_DX_BIND_CONTEXT = 1145, + SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146, + SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147, + SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148, + SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149, + SVGA_3D_CMD_DX_SET_SHADER = 1150, + SVGA_3D_CMD_DX_SET_SAMPLERS = 1151, + SVGA_3D_CMD_DX_DRAW = 1152, + SVGA_3D_CMD_DX_DRAW_INDEXED = 1153, + SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154, + SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155, + SVGA_3D_CMD_DX_DRAW_AUTO = 1156, + SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157, + SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158, + SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159, + SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160, + SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161, + SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162, + SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163, + SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164, + SVGA_3D_CMD_DX_DEFINE_QUERY = 1165, + SVGA_3D_CMD_DX_DESTROY_QUERY = 1166, + SVGA_3D_CMD_DX_BIND_QUERY = 1167, + SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168, + SVGA_3D_CMD_DX_BEGIN_QUERY = 1169, + SVGA_3D_CMD_DX_END_QUERY = 1170, + SVGA_3D_CMD_DX_READBACK_QUERY = 1171, + SVGA_3D_CMD_DX_SET_PREDICATION = 1172, + SVGA_3D_CMD_DX_SET_SOTARGETS = 1173, + SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174, + SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175, + SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176, + SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177, + SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178, + SVGA_3D_CMD_DX_PRED_COPY = 1179, + SVGA_3D_CMD_DX_PRESENTBLT = 1180, + SVGA_3D_CMD_DX_GENMIPS = 1181, + SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182, + SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183, + SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184, + SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185, + SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186, + SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187, + SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188, + SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189, + SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190, + SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191, + SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192, + SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193, + SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194, + SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195, + SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196, + SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197, + SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198, + SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199, + SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200, + SVGA_3D_CMD_DX_DEFINE_SHADER = 1201, + SVGA_3D_CMD_DX_DESTROY_SHADER = 1202, + SVGA_3D_CMD_DX_BIND_SHADER = 1203, + SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204, + SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205, + SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206, + SVGA_3D_CMD_DX_SET_COTABLE = 1207, + SVGA_3D_CMD_DX_READBACK_COTABLE = 1208, + SVGA_3D_CMD_DX_BUFFER_COPY = 1209, + SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210, + SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211, + SVGA_3D_CMD_DX_MOVE_QUERY = 1212, + SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213, + SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214, + SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215, + SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216, + SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217, + SVGA_3D_CMD_DX_HINT = 1218, + SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219, + SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220, + SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221, + SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222, + SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223, + SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224, + SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225, - /* - * DX10 Commands - */ - SVGA_3D_CMD_DX_MIN = 1143, - SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143, - SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144, - SVGA_3D_CMD_DX_BIND_CONTEXT = 1145, - SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146, - SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147, - SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148, - SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149, - SVGA_3D_CMD_DX_SET_SHADER = 1150, - SVGA_3D_CMD_DX_SET_SAMPLERS = 1151, - SVGA_3D_CMD_DX_DRAW = 1152, - SVGA_3D_CMD_DX_DRAW_INDEXED = 1153, - SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154, - SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155, - SVGA_3D_CMD_DX_DRAW_AUTO = 1156, - SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157, - SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158, - SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159, - SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160, - SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161, - SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162, - SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163, - SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164, - SVGA_3D_CMD_DX_DEFINE_QUERY = 1165, - SVGA_3D_CMD_DX_DESTROY_QUERY = 1166, - SVGA_3D_CMD_DX_BIND_QUERY = 1167, - SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168, - SVGA_3D_CMD_DX_BEGIN_QUERY = 1169, - SVGA_3D_CMD_DX_END_QUERY = 1170, - SVGA_3D_CMD_DX_READBACK_QUERY = 1171, - SVGA_3D_CMD_DX_SET_PREDICATION = 1172, - SVGA_3D_CMD_DX_SET_SOTARGETS = 1173, - SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174, - SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175, - SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176, - SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177, - SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178, - SVGA_3D_CMD_DX_PRED_COPY = 1179, - SVGA_3D_CMD_DX_PRESENTBLT = 1180, - SVGA_3D_CMD_DX_GENMIPS = 1181, - SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182, - SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183, - SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184, - SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185, - SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186, - SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187, - SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188, - SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189, - SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190, - SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191, - SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192, - SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193, - SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194, - SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195, - SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196, - SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197, - SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198, - SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199, - SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200, - SVGA_3D_CMD_DX_DEFINE_SHADER = 1201, - SVGA_3D_CMD_DX_DESTROY_SHADER = 1202, - SVGA_3D_CMD_DX_BIND_SHADER = 1203, - SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204, - SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205, - SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206, - SVGA_3D_CMD_DX_SET_COTABLE = 1207, - SVGA_3D_CMD_DX_READBACK_COTABLE = 1208, - SVGA_3D_CMD_DX_BUFFER_COPY = 1209, - SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210, - SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211, - SVGA_3D_CMD_DX_MOVE_QUERY = 1212, - SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213, - SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214, - SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215, - SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216, - SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217, - SVGA_3D_CMD_DX_HINT = 1218, - SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219, - SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220, - SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221, - SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222, - SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223, - SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224, - SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225, + SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226, + SVGA_3D_CMD_DX_MAX = 1227, - SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226, - SVGA_3D_CMD_DX_MAX = 1227, + SVGA_3D_CMD_SCREEN_COPY = 1227, - SVGA_3D_CMD_SCREEN_COPY = 1227, + SVGA_3D_CMD_RESERVED1 = 1228, + SVGA_3D_CMD_RESERVED2 = 1229, + SVGA_3D_CMD_RESERVED3 = 1230, + SVGA_3D_CMD_RESERVED4 = 1231, + SVGA_3D_CMD_RESERVED5 = 1232, + SVGA_3D_CMD_RESERVED6 = 1233, + SVGA_3D_CMD_RESERVED7 = 1234, + SVGA_3D_CMD_RESERVED8 = 1235, - SVGA_3D_CMD_VIDEO_DEFINE_DECODER = 1228, - SVGA_3D_CMD_VIDEO_DESTROY_DECODER = 1229, - SVGA_3D_CMD_VIDEO_DEFINE_PROCESSOR = 1230, - SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR = 1231, - SVGA_3D_CMD_VIDEO_DECODE_FRAME = 1232, - SVGA_3D_CMD_VIDEO_PROCESS_FRAME = 1233, - SVGA_3D_CMD_VIDEO_BIND_DECODER_MOB = 1234, - SVGA_3D_CMD_VIDEO_READBACK_DECODER_MOB = 1235, + SVGA_3D_CMD_GROW_OTABLE = 1236, + SVGA_3D_CMD_DX_GROW_COTABLE = 1237, + SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238, - SVGA_3D_CMD_GROW_OTABLE = 1236, - SVGA_3D_CMD_DX_GROW_COTABLE = 1237, - SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238, + SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239, - SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239, + SVGA_3D_CMD_DX_RESOLVE_COPY = 1240, + SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241, + SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242, + SVGA_3D_CMD_DX_PRED_CONVERT = 1243, + SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244, - SVGA_3D_CMD_DX_RESOLVE_COPY = 1240, - SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241, - SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242, - SVGA_3D_CMD_DX_PRED_CONVERT = 1243, - SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244, + SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245, + SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246, + SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247, + SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248, + SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249, + SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250, - SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245, - SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246, - SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247, - SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248, - SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249, - SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250, + SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251, + SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252, + SVGA_3D_CMD_DX_DISPATCH = 1253, + SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254, - SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251, - SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252, - SVGA_3D_CMD_DX_DISPATCH = 1253, - SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254, + SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255, + SVGA_3D_CMD_UPDATE_ZERO_SURFACE = 1256, + SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257, + SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258, - SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255, - SVGA_3D_CMD_UPDATE_ZERO_SURFACE = 1256, - SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257, - SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258, + SVGA_3D_CMD_LOGICOPS_BITBLT = 1259, + SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260, + SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261, + SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262, + SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263, + SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264, - SVGA_3D_CMD_LOGICOPS_BITBLT = 1259, - SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260, - SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261, - SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262, - SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263, - SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264, + SVGA_3D_CMD_DX_COPY_COTABLE_INTO_MOB = 1265, - SVGA_3D_CMD_DX_COPY_COTABLE_INTO_MOB = 1265, + SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_V2 = 1266, - SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_V2 = 1266, - SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267, - SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268, - SVGA_3D_CMD_DX_SET_MIN_LOD = 1269, + SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267, + SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268, + SVGA_3D_CMD_DX_SET_MIN_LOD = 1269, + SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272, + SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273, + SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274, + SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275, + SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276, + SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277, + SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_MOVE = 1278, - SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272, - SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273, - SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274, - SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275, - SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276, - SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277, + SVGA_3D_CMD_DX_PRED_STAGING_COPY = 1281, + SVGA_3D_CMD_DX_STAGING_COPY = 1282, + SVGA_3D_CMD_DX_PRED_STAGING_COPY_REGION = 1283, + SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_V2 = 1284, + SVGA_3D_CMD_DX_SET_INDEX_BUFFER_V2 = 1285, + SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_OFFSET_AND_SIZE = 1286, + SVGA_3D_CMD_DX_SET_INDEX_BUFFER_OFFSET_AND_SIZE = 1287, + SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE_V2 = 1288, + SVGA_3D_CMD_DX_PRED_STAGING_CONVERT_REGION = 1289, + SVGA_3D_CMD_DX_PRED_STAGING_CONVERT = 1290, + SVGA_3D_CMD_DX_STAGING_BUFFER_COPY = 1291, - SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_MOVE = 1278, - - - - SVGA_3D_CMD_DX_PRED_STAGING_COPY = 1281, - SVGA_3D_CMD_DX_STAGING_COPY = 1282, - SVGA_3D_CMD_DX_PRED_STAGING_COPY_REGION = 1283, - SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_V2 = 1284, - SVGA_3D_CMD_DX_SET_INDEX_BUFFER_V2 = 1285, - SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_OFFSET_AND_SIZE = 1286, - SVGA_3D_CMD_DX_SET_INDEX_BUFFER_OFFSET_AND_SIZE = 1287, - SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE_V2 = 1288, - SVGA_3D_CMD_DX_PRED_STAGING_CONVERT_REGION = 1289, - SVGA_3D_CMD_DX_PRED_STAGING_CONVERT = 1290, - SVGA_3D_CMD_DX_STAGING_BUFFER_COPY = 1291, - - - - - - SVGA_3D_CMD_MAX = 1303, - SVGA_3D_CMD_FUTURE_MAX = 3000 + SVGA_3D_CMD_MAX = 1304, + SVGA_3D_CMD_FUTURE_MAX = 3000 } SVGAFifo3dCmdId; #define SVGA_NUM_3D_CMD (SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE) +#pragma pack(push, 1) +typedef struct { + uint32 id; + uint32 size; +} SVGA3dCmdHeader; +#pragma pack(pop) +#pragma pack(push, 1) +typedef struct { + uint32 numMipLevels; +} SVGA3dSurfaceFace; +#pragma pack(pop) -/* - * The data size header following cmdNum for every 3d command - */ -typedef -#include "vmware_pack_begin.h" -struct { - uint32 id; - uint32 size; -} -#include "vmware_pack_end.h" -SVGA3dCmdHeader; +#pragma pack(push, 1) +typedef struct { + uint32 sid; + SVGA3dSurface1Flags surfaceFlags; + SVGA3dSurfaceFormat format; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 numMipLevels; -} -#include "vmware_pack_end.h" -SVGA3dSurfaceFace; + SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES]; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 sid; - SVGA3dSurface1Flags surfaceFlags; - SVGA3dSurfaceFormat format; +} SVGA3dCmdDefineSurface; +#pragma pack(pop) - /* - * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace - * structures must have the same value of numMipLevels field. - * Otherwise, all but the first SVGA3dSurfaceFace structures must have the - * numMipLevels set to 0. - */ - SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES]; +#pragma pack(push, 1) +typedef struct { + uint32 sid; + SVGA3dSurface1Flags surfaceFlags; + SVGA3dSurfaceFormat format; - /* - * Followed by an SVGA3dSize structure for each mip level in each face. - * - * A note on surface sizes: Sizes are always specified in pixels, - * even if the true surface size is not a multiple of the minimum - * block size of the surface's format. For example, a 3x3x1 DXT1 - * compressed texture would actually be stored as a 4x4x1 image in - * memory. - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */ + SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES]; + uint32 multisampleCount; + SVGA3dTextureFilter autogenFilter; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 sid; - SVGA3dSurface1Flags surfaceFlags; - SVGA3dSurfaceFormat format; +} SVGA3dCmdDefineSurface_v2; +#pragma pack(pop) - /* - * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace - * structures must have the same value of numMipLevels field. - * Otherwise, all but the first SVGA3dSurfaceFace structures must have the - * numMipLevels set to 0. - */ - SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES]; - uint32 multisampleCount; - SVGA3dTextureFilter autogenFilter; +#pragma pack(push, 1) +typedef struct { + uint32 sid; +} SVGA3dCmdDestroySurface; +#pragma pack(pop) - /* - * Followed by an SVGA3dSize structure for each mip level in each face. - * - * A note on surface sizes: Sizes are always specified in pixels, - * even if the true surface size is not a multiple of the minimum - * block size of the surface's format. For example, a 3x3x1 DXT1 - * compressed texture would actually be stored as a 4x4x1 image in - * memory. - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; +} SVGA3dCmdDefineContext; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; +} SVGA3dCmdDestroyContext; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dClearFlag clearFlag; + uint32 color; + float depth; + uint32 stencil; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */ +} SVGA3dCmdClear; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dClearFlag clearFlag; - uint32 color; - float depth; - uint32 stencil; - /* Followed by variable number of SVGA3dRect structures */ -} -#include "vmware_pack_end.h" -SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */ +#pragma pack(push, 1) +typedef struct { + SVGA3dLightType type; + SVGA3dBool inWorldSpace; + float diffuse[4]; + float specular[4]; + float ambient[4]; + float position[4]; + float direction[4]; + float range; + float falloff; + float attenuation0; + float attenuation1; + float attenuation2; + float theta; + float phi; +} SVGA3dLightData; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - SVGA3dLightType type; - SVGA3dBool inWorldSpace; - float diffuse[4]; - float specular[4]; - float ambient[4]; - float position[4]; - float direction[4]; - float range; - float falloff; - float attenuation0; - float attenuation1; - float attenuation2; - float theta; - float phi; -} -#include "vmware_pack_end.h" -SVGA3dLightData; +#pragma pack(push, 1) +typedef struct { + uint32 sid; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 sid; - /* Followed by variable number of SVGA3dCopyRect structures */ -} -#include "vmware_pack_end.h" -SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */ +} SVGA3dCmdPresent; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - SVGA3dRenderStateName state; +#pragma pack(push, 1) +typedef struct { + SVGA3dRenderStateName state; union { - uint32 uintValue; - float floatValue; + uint32 uintValue; + float floatValue; }; -} -#include "vmware_pack_end.h" -SVGA3dRenderState; +} SVGA3dRenderState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - /* Followed by variable number of SVGA3dRenderState structures */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; +} SVGA3dCmdSetRenderState; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { + uint32 cid; SVGA3dRenderTargetType type; - SVGA3dSurfaceImageId target; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */ + SVGA3dSurfaceImageId target; +} SVGA3dCmdSetRenderTarget; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - SVGA3dSurfaceImageId src; - SVGA3dSurfaceImageId dest; - /* Followed by variable number of SVGA3dCopyBox structures */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */ +#pragma pack(push, 1) +typedef struct { + SVGA3dSurfaceImageId src; + SVGA3dSurfaceImageId dest; -/* - * Perform a surface copy within the same image. - * The src/dest boxes are allowed to overlap. - */ -typedef -#include "vmware_pack_begin.h" -struct { - SVGA3dSurfaceImageId surface; +} SVGA3dCmdSurfaceCopy; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { + SVGA3dSurfaceImageId surface; SVGA3dCopyBox box; -} -#include "vmware_pack_end.h" -SVGA3dCmdIntraSurfaceCopy; /* SVGA_3D_CMD_INTRA_SURFACE_COPY */ +} SVGA3dCmdIntraSurfaceCopy; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 srcSid; uint32 destSid; -} -#include "vmware_pack_end.h" -SVGA3dCmdWholeSurfaceCopy; /* SVGA_3D_CMD_WHOLE_SURFACE_COPY */ +} SVGA3dCmdWholeSurfaceCopy; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - SVGA3dSurfaceImageId src; - SVGA3dSurfaceImageId dest; +#pragma pack(push, 1) +typedef struct { + SVGA3dSurfaceImageId src; + SVGA3dSurfaceImageId dest; SVGA3dBox boxSrc; SVGA3dBox boxDest; -} -#include "vmware_pack_end.h" -SVGA3dCmdSurfaceStretchBltNonMSToMS; /* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS */ +} SVGA3dCmdSurfaceStretchBltNonMSToMS; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - SVGA3dSurfaceImageId src; - SVGA3dSurfaceImageId dest; - SVGA3dBox boxSrc; - SVGA3dBox boxDest; - SVGA3dStretchBltMode mode; -} -#include "vmware_pack_end.h" -SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */ +#pragma pack(push, 1) +typedef struct { + SVGA3dSurfaceImageId src; + SVGA3dSurfaceImageId dest; + SVGA3dBox boxSrc; + SVGA3dBox boxDest; + SVGA3dStretchBltMode mode; +} SVGA3dCmdSurfaceStretchBlt; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { -typedef -#include "vmware_pack_begin.h" -struct { - /* - * If the discard flag is present in a surface DMA operation, the host may - * discard the contents of the current mipmap level and face of the target - * surface before applying the surface DMA contents. - */ uint32 discard : 1; - /* - * If the unsynchronized flag is present, the host may perform this upload - * without syncing to pending reads on this surface. - */ uint32 unsynchronized : 1; - /* - * Guests *MUST* set the reserved bits to 0 before submitting the command - * suffix as future flags may occupy these bits. - */ uint32 reserved : 30; -} -#include "vmware_pack_end.h" -SVGA3dSurfaceDMAFlags; +} SVGA3dSurfaceDMAFlags; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAGuestImage guest; SVGA3dSurfaceImageId host; SVGA3dTransferType transfer; - /* - * Followed by variable number of SVGA3dCopyBox structures. For consistency - * in all clipping logic and coordinate translation, we define the - * "source" in each copyBox as the guest image and the - * "destination" as the host image, regardless of transfer - * direction. - * - * For efficiency, the SVGA3D device is free to copy more data than - * specified. For example, it may round copy boxes outwards such - * that they lie on particular alignment boundaries. - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */ +} SVGA3dCmdSurfaceDMA; +#pragma pack(pop) -/* - * SVGA3dCmdSurfaceDMASuffix -- - * - * This is a command suffix that will appear after a SurfaceDMA command in - * the FIFO. It contains some extra information that hosts may use to - * optimize performance or protect the guest. This suffix exists to preserve - * backwards compatibility while also allowing for new functionality to be - * implemented. - */ - -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 suffixSize; - /* - * The maximum offset is used to determine the maximum offset from the - * guestPtr base address that will be accessed or written to during this - * surfaceDMA. If the suffix is supported, the host will respect this - * boundary while performing surface DMAs. - * - * Defaults to MAX_UINT32 - */ uint32 maximumOffset; - /* - * A set of flags that describes optimizations that the host may perform - * while performing this surface DMA operation. The guest should never rely - * on behaviour that is different when these flags are set for correctness. - * - * Defaults to 0 - */ SVGA3dSurfaceDMAFlags flags; -} -#include "vmware_pack_end.h" -SVGA3dCmdSurfaceDMASuffix; +} SVGA3dCmdSurfaceDMASuffix; +#pragma pack(pop) -/* - * SVGA_3D_CMD_DRAW_PRIMITIVES -- - * - * This command is the SVGA3D device's generic drawing entry point. - * It can draw multiple ranges of primitives, optionally using an - * index buffer, using an arbitrary collection of vertex buffers. - * - * Each SVGA3dVertexDecl defines a distinct vertex array to bind - * during this draw call. The declarations specify which surface - * the vertex data lives in, what that vertex data is used for, - * and how to interpret it. - * - * Each SVGA3dPrimitiveRange defines a collection of primitives - * to render using the same vertex arrays. An index buffer is - * optional. - */ +#pragma pack(push, 1) +typedef struct { -typedef -#include "vmware_pack_begin.h" -struct { - /* - * A range hint is an optional specification for the range of indices - * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed - * that the entire array will be used. - * - * These are only hints. The SVGA3D device may use them for - * performance optimization if possible, but it's also allowed to - * ignore these values. - */ - uint32 first; - uint32 last; -} -#include "vmware_pack_end.h" -SVGA3dArrayRangeHint; + uint32 first; + uint32 last; +} SVGA3dArrayRangeHint; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - /* - * Define the origin and shape of a vertex or index array. Both - * 'offset' and 'stride' are in bytes. The provided surface will be - * reinterpreted as a flat array of bytes in the same format used - * by surface DMA operations. To avoid unnecessary conversions, the - * surface should be created with the SVGA3D_BUFFER format. - * - * Index 0 in the array starts 'offset' bytes into the surface. - * Index 1 begins at byte 'offset + stride', etc. Array indices may - * not be negative. - */ - uint32 surfaceId; - uint32 offset; - uint32 stride; -} -#include "vmware_pack_end.h" -SVGA3dArray; +#pragma pack(push, 1) +typedef struct { -typedef -#include "vmware_pack_begin.h" -struct { - /* - * Describe a vertex array's data type, and define how it is to be - * used by the fixed function pipeline or the vertex shader. It - * isn't useful to have two VertexDecls with the same - * VertexArrayIdentity in one draw call. - */ - SVGA3dDeclType type; - SVGA3dDeclMethod method; - SVGA3dDeclUsage usage; - uint32 usageIndex; -} -#include "vmware_pack_end.h" -SVGA3dVertexArrayIdentity; + uint32 surfaceId; + uint32 offset; + uint32 stride; +} SVGA3dArray; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dVertexDecl { - SVGA3dVertexArrayIdentity identity; - SVGA3dArray array; - SVGA3dArrayRangeHint rangeHint; -} -#include "vmware_pack_end.h" -SVGA3dVertexDecl; +#pragma pack(push, 1) +typedef struct { -typedef -#include "vmware_pack_begin.h" -struct SVGA3dPrimitiveRange { - /* - * Define a group of primitives to render, from sequential indices. - * - * The value of 'primitiveType' and 'primitiveCount' imply the - * total number of vertices that will be rendered. - */ - SVGA3dPrimitiveType primType; - uint32 primitiveCount; + SVGA3dDeclType type; + SVGA3dDeclMethod method; + SVGA3dDeclUsage usage; + uint32 usageIndex; +} SVGA3dVertexArrayIdentity; +#pragma pack(pop) - /* - * Optional index buffer. If indexArray.surfaceId is - * SVGA3D_INVALID_ID, we render without an index buffer. Rendering - * without an index buffer is identical to rendering with an index - * buffer containing the sequence [0, 1, 2, 3, ...]. - * - * If an index buffer is in use, indexWidth specifies the width in - * bytes of each index value. It must be less than or equal to - * indexArray.stride. - * - * (Currently, the SVGA3D device requires index buffers to be tightly - * packed. In other words, indexWidth == indexArray.stride) - */ - SVGA3dArray indexArray; - uint32 indexWidth; +#pragma pack(push, 1) +typedef struct SVGA3dVertexDecl { + SVGA3dVertexArrayIdentity identity; + SVGA3dArray array; + SVGA3dArrayRangeHint rangeHint; +} SVGA3dVertexDecl; +#pragma pack(pop) - /* - * Optional index bias. This number is added to all indices from - * indexArray before they are used as vertex array indices. This - * can be used in multiple ways: - * - * - When not using an indexArray, this bias can be used to - * specify where in the vertex arrays to begin rendering. - * - * - A positive number here is equivalent to increasing the - * offset in each vertex array. - * - * - A negative number can be used to render using a small - * vertex array and an index buffer that contains large - * values. This may be used by some applications that - * crop a vertex buffer without modifying their index - * buffer. - * - * Note that rendering with a negative bias value may be slower and - * use more memory than rendering with a positive or zero bias. - */ - int32 indexBias; -} -#include "vmware_pack_end.h" -SVGA3dPrimitiveRange; +#pragma pack(push, 1) +typedef struct SVGA3dPrimitiveRange { -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 numVertexDecls; - uint32 numRanges; + SVGA3dPrimitiveType primType; + uint32 primitiveCount; - /* - * There are two variable size arrays after the - * SVGA3dCmdDrawPrimitives structure. In order, - * they are: - * - * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than - * SVGA3D_MAX_VERTEX_ARRAYS; - * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than - * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES; - * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains - * the frequency divisor for the corresponding vertex decl). - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */ + SVGA3dArray indexArray; + uint32 indexWidth; -typedef -#include "vmware_pack_begin.h" -struct { + int32 indexBias; +} SVGA3dPrimitiveRange; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 numVertexDecls; + uint32 numRanges; + +} SVGA3dCmdDrawPrimitives; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { uint32 cid; - uint32 primitiveCount; // How many primitives to render - uint32 startVertexLocation; // Which vertex do we start rendering at. + uint32 primitiveCount; + uint32 startVertexLocation; - uint8 primitiveType; // SVGA3dPrimitiveType + uint8 primitiveType; uint8 padding[3]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDraw; +} SVGA3dCmdDraw; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 cid; - uint8 primitiveType; // SVGA3dPrimitiveType + uint8 primitiveType; - uint32 indexBufferSid; // Valid index buffer sid. - uint32 indexBufferOffset; // Byte offset into the vertex buffer, almost - // always 0 for DX9 guests, non-zero for OpenGL - // guests. We can't represent non-multiple of - // stride offsets in D3D9Renderer... - uint8 indexBufferStride; // Allowable values = 1, 2, or 4 + uint32 indexBufferSid; + uint32 indexBufferOffset; - int32 baseVertexLocation; // Bias applied to the index when selecting a - // vertex from the streams, may be negative + uint8 indexBufferStride; - uint32 primitiveCount; // How many primitives to render + int32 baseVertexLocation; + + uint32 primitiveCount; uint32 pad0; uint16 pad1; -} -#include "vmware_pack_end.h" -SVGA3dCmdDrawIndexed; +} SVGA3dCmdDrawIndexed; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { -typedef -#include "vmware_pack_begin.h" -struct { - /* - * Describe a vertex array's data type, and define how it is to be - * used by the fixed function pipeline or the vertex shader. It - * isn't useful to have two VertexDecls with the same - * VertexArrayIdentity in one draw call. - */ uint16 streamOffset; uint8 stream; - uint8 type; // SVGA3dDeclType - uint8 method; // SVGA3dDeclMethod - uint8 usage; // SVGA3dDeclUsage + uint8 type; + uint8 method; + uint8 usage; uint8 usageIndex; uint8 padding; -} -#include "vmware_pack_end.h" -SVGA3dVertexElement; +} SVGA3dVertexElement; +#pragma pack(pop) -/* - * Should the vertex element respect the stream value? The high bit of the - * stream should be set to indicate that the stream should be respected. If - * the high bit is not set, the stream will be ignored and replaced by the index - * of the position of the currently considered vertex element. - * - * All guests should set this bit and correctly specify the stream going - * forward. - */ #define SVGA3D_VERTEX_ELEMENT_RESPECT_STREAM (1 << 7) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 cid; uint32 numElements; - /* - * Followed by numElements SVGA3dVertexElement structures. - * - * If numElements < SVGA3D_MAX_VERTEX_ARRAYS, the remaining elements - * are cleared and will not be used by following draws. - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSetVertexDecls; +} SVGA3dCmdSetVertexDecls; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 sid; uint32 stride; uint32 offset; -} -#include "vmware_pack_end.h" -SVGA3dVertexStream; +} SVGA3dVertexStream; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 cid; uint32 numStreams; - /* - * Followed by numStream SVGA3dVertexStream structures. - * - * If numStreams < SVGA3D_MAX_VERTEX_ARRAYS, the remaining streams - * are cleared and will not be used by following draws. - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSetVertexStreams; -typedef -#include "vmware_pack_begin.h" -struct { +} SVGA3dCmdSetVertexStreams; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { uint32 cid; uint32 numDivisors; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetVertexDivisors; +} SVGA3dCmdSetVertexDivisors; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 stage; - SVGA3dTextureStateName name; +#pragma pack(push, 1) +typedef struct { + uint32 stage; + SVGA3dTextureStateName name; union { - uint32 value; - float floatValue; + uint32 value; + float floatValue; }; -} -#include "vmware_pack_end.h" -SVGA3dTextureState; +} SVGA3dTextureState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - /* Followed by variable number of SVGA3dTextureState structures */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dTransformType type; - float matrix[16]; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */ +} SVGA3dCmdSetTextureState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - float min; - float max; -} -#include "vmware_pack_end.h" -SVGA3dZRange; +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dTransformType type; + float matrix[16]; +} SVGA3dCmdSetTransform; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dZRange zRange; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */ +#pragma pack(push, 1) +typedef struct { + float min; + float max; +} SVGA3dZRange; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - float diffuse[4]; - float ambient[4]; - float specular[4]; - float emissive[4]; - float shininess; -} -#include "vmware_pack_end.h" -SVGA3dMaterial; +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dZRange zRange; +} SVGA3dCmdSetZRange; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dFace face; - SVGA3dMaterial material; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */ +#pragma pack(push, 1) +typedef struct { + float diffuse[4]; + float ambient[4]; + float specular[4]; + float emissive[4]; + float shininess; +} SVGA3dMaterial; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 index; - SVGA3dLightData data; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dFace face; + SVGA3dMaterial material; +} SVGA3dCmdSetMaterial; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 index; - uint32 enabled; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 index; + SVGA3dLightData data; +} SVGA3dCmdSetLightData; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dRect rect; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 index; + uint32 enabled; +} SVGA3dCmdSetLightEnabled; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dRect rect; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dRect rect; +} SVGA3dCmdSetViewport; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 index; - float plane[4]; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dRect rect; +} SVGA3dCmdSetScissorRect; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 shid; - SVGA3dShaderType type; - /* Followed by variable number of DWORDs for shader bycode */ -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 index; + float plane[4]; +} SVGA3dCmdSetClipPlane; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 shid; - SVGA3dShaderType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 shid; + SVGA3dShaderType type; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 reg; /* register number */ - SVGA3dShaderType type; - SVGA3dShaderConstType ctype; - uint32 values[4]; +} SVGA3dCmdDefineShader; +#pragma pack(pop) - /* - * Followed by a variable number of additional values. - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 shid; + SVGA3dShaderType type; +} SVGA3dCmdDestroyShader; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dShaderType type; - uint32 shid; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 reg; + SVGA3dShaderType type; + SVGA3dShaderConstType ctype; + uint32 values[4]; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dQueryType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */ +} SVGA3dCmdSetShaderConst; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dQueryType type; - SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */ -} -#include "vmware_pack_end.h" -SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dShaderType type; + uint32 shid; +} SVGA3dCmdSetShader; +#pragma pack(pop) +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dQueryType type; +} SVGA3dCmdBeginQuery; +#pragma pack(pop) -/* - * SVGA3D_CMD_WAIT_FOR_QUERY -- - * - * Will read the SVGA3dQueryResult structure pointed to by guestResult, - * and if the state member is set to anything else than - * SVGA3D_QUERYSTATE_PENDING, this command will always be a no-op. - * - * Otherwise, in addition to the query explicitly waited for, - * All queries with the same type and issued with the same cid, for which - * an SVGA_3D_CMD_END_QUERY command has previously been sent, will - * be finished after execution of this command. - * - * A query will be identified by the gmrId and offset of the guestResult - * member. If the device can't find an SVGA_3D_CMD_END_QUERY that has - * been sent previously with an identical gmrId and offset, it will - * effectively end all queries with an identical type issued with the - * same cid, and the SVGA3dQueryResult structure pointed to by - * guestResult will not be written to. This property can be used to - * implement a query barrier for a given cid and query type. - */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dQueryType type; + SVGAGuestPtr guestResult; +} SVGA3dCmdEndQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; /* Same parameters passed to END_QUERY */ - SVGA3dQueryType type; - SVGAGuestPtr guestResult; -} -#include "vmware_pack_end.h" -SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dQueryType type; + SVGAGuestPtr guestResult; +} SVGA3dCmdWaitForQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 totalSize; /* Set by guest before query is ended. */ - SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */ - union { /* Set by host on exit from PENDING state */ - uint32 result32; - uint32 queryCookie; /* May be used to identify which QueryGetData this - result corresponds to. */ +#pragma pack(push, 1) +typedef struct { + uint32 totalSize; + SVGA3dQueryState state; + union { + uint32 result32; + uint32 queryCookie; }; -} -#include "vmware_pack_end.h" -SVGA3dQueryResult; +} SVGA3dQueryResult; +#pragma pack(pop) - -/* - * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN -- - * - * This is a blit from an SVGA3D surface to a Screen Object. - * This blit must be directed at a specific screen. - * - * The blit copies from a rectangular region of an SVGA3D surface - * image to a rectangular region of a screen. - * - * This command takes an optional variable-length list of clipping - * rectangles after the body of the command. If no rectangles are - * specified, there is no clipping region. The entire destRect is - * drawn to. If one or more rectangles are included, they describe - * a clipping region. The clip rectangle coordinates are measured - * relative to the top-left corner of destRect. - * - * The srcImage must be from mip=0 face=0. - * - * This supports scaling if the src and dest are of different sizes. - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT - */ - -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceImageId srcImage; - SVGASignedRect srcRect; - uint32 destScreenId; /* Screen Object ID */ - SVGASignedRect destRect; - /* Clipping: zero or more SVGASignedRects follow */ -} -#include "vmware_pack_end.h" -SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */ + SVGASignedRect srcRect; + uint32 destScreenId; + SVGASignedRect destRect; -typedef -#include "vmware_pack_begin.h" -struct { - uint32 sid; - SVGA3dTextureFilter filter; -} -#include "vmware_pack_end.h" -SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */ +} SVGA3dCmdBlitSurfaceToScreen; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdActivateSurface; /* SVGA_3D_CMD_ACTIVATE_SURFACE */ + SVGA3dTextureFilter filter; +} SVGA3dCmdGenerateMipmaps; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDeactivateSurface; /* SVGA_3D_CMD_DEACTIVATE_SURFACE */ +} SVGA3dCmdActivateSurface; +#pragma pack(pop) -/* - * Screen DMA command - * - * Available with SVGA_FIFO_CAP_SCREEN_OBJECT_2. The SVGA_CAP_3D device - * cap bit is not required. - * - * - refBuffer and destBuffer are 32bit BGRX; refBuffer and destBuffer could - * be different, but it is required that guest makes sure refBuffer has - * exactly the same contents that were written to when last time screen DMA - * command is received by host. - * - * - changemap is generated by lib/blit, and it has the changes from last - * received screen DMA or more. - */ +#pragma pack(push, 1) +typedef struct { + uint32 sid; +} SVGA3dCmdDeactivateSurface; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdScreenDMA { +#pragma pack(push, 1) +typedef struct SVGA3dCmdScreenDMA { uint32 screenId; SVGAGuestImage refBuffer; SVGAGuestImage destBuffer; SVGAGuestImage changeMap; -} -#include "vmware_pack_end.h" -SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */ +} SVGA3dCmdScreenDMA; +#pragma pack(pop) -/* - * Logic ops - */ +#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01) +#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01) +#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02) +#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01) -#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01) -#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01) -#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02) -#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01) +#pragma pack(push, 1) +typedef struct SVGA3dCmdLogicOpsBitBlt { -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdLogicOpsBitBlt { - /* - * All LogicOps surfaces are one-level - * surfaces so mipmap & face should always - * be zero. - */ SVGA3dSurfaceImageId src; SVGA3dSurfaceImageId dst; SVGA3dLogicOp logicOp; - /* Followed by variable number of SVGA3dCopyBox structures */ -} -#include "vmware_pack_end.h" -SVGA3dCmdLogicOpsBitBlt; /* SVGA_3D_CMD_LOGICOPS_BITBLT */ + SVGA3dLogicOpRop3 logicOpRop3; +} SVGA3dCmdLogicOpsBitBlt; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdLogicOpsTransBlt { -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdLogicOpsTransBlt { - /* - * All LogicOps surfaces are one-level - * surfaces so mipmap & face should always - * be zero. - */ SVGA3dSurfaceImageId src; SVGA3dSurfaceImageId dst; uint32 color; @@ -1299,19 +886,12 @@ struct SVGA3dCmdLogicOpsTransBlt { SVGA3dBox srcBox; SVGA3dSignedBox dstBox; SVGA3dBox clipBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */ +} SVGA3dCmdLogicOpsTransBlt; +#pragma pack(pop) +#pragma pack(push, 1) +typedef struct SVGA3dCmdLogicOpsStretchBlt { -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdLogicOpsStretchBlt { - /* - * All LogicOps surfaces are one-level - * surfaces so mipmap & face should always - * be zero. - */ SVGA3dSurfaceImageId src; SVGA3dSurfaceImageId dst; uint16 mode; @@ -1319,36 +899,23 @@ struct SVGA3dCmdLogicOpsStretchBlt { SVGA3dBox srcBox; SVGA3dSignedBox dstBox; SVGA3dBox clipBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */ +} SVGA3dCmdLogicOpsStretchBlt; +#pragma pack(pop) +#pragma pack(push, 1) +typedef struct SVGA3dCmdLogicOpsColorFill { -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdLogicOpsColorFill { - /* - * All LogicOps surfaces are one-level - * surfaces so mipmap & face should always - * be zero. - */ SVGA3dSurfaceImageId dst; uint32 color; SVGA3dLogicOp logicOp; - /* Followed by variable number of SVGA3dRect structures. */ -} -#include "vmware_pack_end.h" -SVGA3dCmdLogicOpsColorFill; /* SVGA_3D_CMD_LOGICOPS_COLORFILL */ + SVGA3dLogicOpRop3 logicOpRop3; +} SVGA3dCmdLogicOpsColorFill; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdLogicOpsAlphaBlend { -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdLogicOpsAlphaBlend { - /* - * All LogicOps surfaces are one-level - * surfaces so mipmap & face should always - * be zero. - */ SVGA3dSurfaceImageId src; SVGA3dSurfaceImageId dst; uint32 alphaVal; @@ -1356,23 +923,17 @@ struct SVGA3dCmdLogicOpsAlphaBlend { SVGA3dBox srcBox; SVGA3dSignedBox dstBox; SVGA3dBox clipBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */ +} SVGA3dCmdLogicOpsAlphaBlend; +#pragma pack(pop) #define SVGA3D_CLEARTYPE_INVALID_GAMMA_INDEX 0xFFFFFFFF #define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512 #define SVGA3D_CLEARTYPE_GAMMA_HEIGHT 16 -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdLogicOpsClearTypeBlend { - /* - * All LogicOps surfaces are one-level - * surfaces so mipmap & face should always - * be zero. - */ +#pragma pack(push, 1) +typedef struct SVGA3dCmdLogicOpsClearTypeBlend { + SVGA3dSurfaceImageId tmp; SVGA3dSurfaceImageId dst; SVGA3dSurfaceImageId gammaSurf; @@ -1382,29 +943,20 @@ struct SVGA3dCmdLogicOpsClearTypeBlend { uint32 color2; int32 alphaOffsetX; int32 alphaOffsetY; - /* Followed by variable number of SVGA3dBox structures */ -} -#include "vmware_pack_end.h" -SVGA3dCmdLogicOpsClearTypeBlend; /* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */ +} SVGA3dCmdLogicOpsClearTypeBlend; +#pragma pack(pop) -/* - * Guest-backed objects definitions. - */ - -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAMobFormat ptDepth; uint32 sizeInBytes; PPN64 base; -} -#include "vmware_pack_end.h" -SVGAOTableMobEntry; +} SVGAOTableMobEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceFormat format; SVGA3dSurface1Flags surface1Flags; uint32 numMipLevels; @@ -1420,37 +972,31 @@ struct { uint16 bufferByteStride; float minLOD; uint32 pad0[2]; -} -#include "vmware_pack_end.h" -SVGAOTableSurfaceEntry; +} SVGAOTableSurfaceEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 cid; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGAOTableContextEntry; +} SVGAOTableContextEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dShaderType type; uint32 sizeInBytes; uint32 offsetInBytes; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGAOTableShaderEntry; +} SVGAOTableShaderEntry; +#pragma pack(pop) #define SVGA_STFLAG_PRIMARY (1 << 0) -#define SVGA_STFLAG_RESERVED (1 << 1) /* Added with cap SVGA_CAP_HP_CMD_QUEUE */ +#define SVGA_STFLAG_RESERVED (1 << 1) typedef uint32 SVGAScreenTargetFlags; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceImageId image; uint32 width; uint32 height; @@ -1459,59 +1005,46 @@ struct { SVGAScreenTargetFlags flags; uint32 dpi; uint32 pad[7]; -} -#include "vmware_pack_end.h" -SVGAOTableScreenTargetEntry; +} SVGAOTableScreenTargetEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { float value[4]; -} -#include "vmware_pack_end.h" -SVGA3dShaderConstFloat; +} SVGA3dShaderConstFloat; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { int32 value[4]; -} -#include "vmware_pack_end.h" -SVGA3dShaderConstInt; +} SVGA3dShaderConstInt; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 value; -} -#include "vmware_pack_end.h" -SVGA3dShaderConstBool; +} SVGA3dShaderConstBool; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint16 streamOffset; uint8 stream; uint8 type; uint8 methodUsage; uint8 usageIndex; -} -#include "vmware_pack_end.h" -SVGAGBVertexElement; +} SVGAGBVertexElement; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 sid; uint16 stride; uint32 offset; -} -#include "vmware_pack_end.h" -SVGAGBVertexStream; - -typedef -#include "vmware_pack_begin.h" -struct { +} SVGAGBVertexStream; +#pragma pack(pop) +#pragma pack(push, 1) +typedef struct { SVGA3dRect viewport; SVGA3dRect scissorRect; SVGA3dZRange zRange; @@ -1534,9 +1067,6 @@ struct { SVGA3dBool lightEnabled[SVGA3D_NUM_LIGHTS]; SVGA3dLightData lightData[SVGA3D_NUM_LIGHTS]; - /* - * Shaders currently bound - */ uint32 shaders[SVGA3D_NUM_SHADERTYPE_PREDX]; SVGAGBVertexElement decl3[10]; uint32 pad1[3]; @@ -1544,15 +1074,11 @@ struct { uint32 occQueryActive; uint32 occQueryValue; - /* - * Int/Bool Shader constants - */ SVGA3dShaderConstInt pShaderIValues[SVGA3D_CONSTINTREG_MAX]; SVGA3dShaderConstInt vShaderIValues[SVGA3D_CONSTINTREG_MAX]; uint16 pShaderBValues; uint16 vShaderBValues; - SVGAGBVertexStream streams[SVGA3D_MAX_VERTEX_ARRAYS]; SVGA3dVertexDivisor divisors[SVGA3D_MAX_VERTEX_ARRAYS]; uint32 numVertexDecls; @@ -1560,161 +1086,92 @@ struct { uint32 numVertexDivisors; uint32 pad2[30]; - /* - * Texture Stages - * - * SVGA3D_TS_INVALID through SVGA3D_TS_CONSTANT are in the - * textureStages array. - * SVGA3D_TS_COLOR_KEY is in tsColorKey. - */ uint32 tsColorKey[SVGA3D_NUM_TEXTURE_UNITS]; uint32 textureStages[SVGA3D_NUM_TEXTURE_UNITS][SVGA3D_TS_CONSTANT + 1]; uint32 tsColorKeyEnable[SVGA3D_NUM_TEXTURE_UNITS]; - /* - * Float Shader constants. - */ SVGA3dShaderConstFloat pShaderFValues[SVGA3D_CONSTREG_MAX]; SVGA3dShaderConstFloat vShaderFValues[SVGA3D_CONSTREG_MAX]; -} -#include "vmware_pack_end.h" -SVGAGBContextData; +} SVGAGBContextData; +#pragma pack(pop) -/* - * SVGA3dCmdSetOTableBase -- - * - * This command allows the guest to specify the base PPN of the - * specified object table. - */ - -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAOTableType type; - PPN baseAddress; + PPN32 baseAddress; uint32 sizeInBytes; uint32 validSizeInBytes; SVGAMobFormat ptDepth; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */ +} SVGA3dCmdSetOTableBase; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAOTableType type; PPN64 baseAddress; uint32 sizeInBytes; uint32 validSizeInBytes; SVGAMobFormat ptDepth; -} -#include "vmware_pack_end.h" -SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */ +} SVGA3dCmdSetOTableBase64; +#pragma pack(pop) -/* - * Guests using SVGA_3D_CMD_GROW_OTABLE are promising that - * the new OTable contains the same contents as the old one, except possibly - * for some new invalid entries at the end. - * - * (Otherwise, guests should use one of the SetOTableBase commands.) - */ -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAOTableType type; PPN64 baseAddress; uint32 sizeInBytes; uint32 validSizeInBytes; SVGAMobFormat ptDepth; -} -#include "vmware_pack_end.h" -SVGA3dCmdGrowOTable; /* SVGA_3D_CMD_GROW_OTABLE */ +} SVGA3dCmdGrowOTable; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAOTableType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */ +} SVGA3dCmdReadbackOTable; +#pragma pack(pop) -/* - * Define a memory object (Mob) in the OTable. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBMob { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBMob { SVGAMobId mobid; SVGAMobFormat ptDepth; - PPN base; + PPN32 base; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */ +} SVGA3dCmdDefineGBMob; +#pragma pack(pop) - -/* - * Destroys an object in the OTable. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDestroyGBMob { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDestroyGBMob { SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */ +} SVGA3dCmdDestroyGBMob; +#pragma pack(pop) -/* - * Define a memory object (Mob) in the OTable with a PPN64 base. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBMob64 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBMob64 { SVGAMobId mobid; SVGAMobFormat ptDepth; PPN64 base; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */ +} SVGA3dCmdDefineGBMob64; +#pragma pack(pop) -/* - * Redefine an object in the OTable with PPN64 base. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdRedefineGBMob64 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdRedefineGBMob64 { SVGAMobId mobid; SVGAMobFormat ptDepth; PPN64 base; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */ +} SVGA3dCmdRedefineGBMob64; +#pragma pack(pop) -/* - * Notification that the page tables have been modified. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdUpdateGBMobMapping { +#pragma pack(push, 1) +typedef struct SVGA3dCmdUpdateGBMobMapping { SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */ +} SVGA3dCmdUpdateGBMobMapping; +#pragma pack(pop) -/* - * Define a guest-backed surface. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBSurface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBSurface { uint32 sid; SVGA3dSurface1Flags surfaceFlags; SVGA3dSurfaceFormat format; @@ -1722,19 +1179,11 @@ struct SVGA3dCmdDefineGBSurface { uint32 multisampleCount; SVGA3dTextureFilter autogenFilter; SVGA3dSize size; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */ +} SVGA3dCmdDefineGBSurface; +#pragma pack(pop) -/* - * Defines a guest-backed surface, adding the arraySize field. - * - * See also: - * http://msdn.microsoft.com/en-us/library/ff541697%28v=VS.85%29.aspx - */ -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBSurface_v2 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBSurface_v2 { uint32 sid; SVGA3dSurface1Flags surfaceFlags; SVGA3dSurfaceFormat format; @@ -1744,35 +1193,26 @@ struct SVGA3dCmdDefineGBSurface_v2 { SVGA3dSize size; uint32 arraySize; uint32 pad; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */ +} SVGA3dCmdDefineGBSurface_v2; +#pragma pack(pop) -/* - * Defines a guest-backed surface, adding the larger flags. - */ -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBSurface_v3 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBSurface_v3 { uint32 sid; SVGA3dSurfaceAllFlags surfaceFlags; SVGA3dSurfaceFormat format; uint32 numMipLevels; uint32 multisampleCount; SVGA3dMSPattern multisamplePattern; + SVGA3dMSQualityLevel qualityLevel; SVGA3dTextureFilter autogenFilter; SVGA3dSize size; uint32 arraySize; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBSurface_v3; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 */ +} SVGA3dCmdDefineGBSurface_v3; +#pragma pack(pop) -/* - * Defines a guest-backed surface, adding buffer byte stride. - */ -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBSurface_v4 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBSurface_v4 { uint32 sid; SVGA3dSurfaceAllFlags surfaceFlags; SVGA3dSurfaceFormat format; @@ -1784,381 +1224,208 @@ struct SVGA3dCmdDefineGBSurface_v4 { SVGA3dSize size; uint32 arraySize; uint32 bufferByteStride; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBSurface_v4; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 */ +} SVGA3dCmdDefineGBSurface_v4; +#pragma pack(pop) -/* - * Destroy a guest-backed surface. - */ -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDestroyGBSurface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDestroyGBSurface { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */ +} SVGA3dCmdDestroyGBSurface; +#pragma pack(pop) -/* - * Bind a guest-backed surface to a mob. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdBindGBSurface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdBindGBSurface { uint32 sid; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */ +} SVGA3dCmdBindGBSurface; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdBindGBSurfaceWithPitch { +#pragma pack(push, 1) +typedef struct SVGA3dCmdBindGBSurfaceWithPitch { uint32 sid; SVGAMobId mobid; uint32 baseLevelPitch; -} -#include "vmware_pack_end.h" -SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */ - -/* - * Conditionally bind a mob to a guest-backed surface if testMobid - * matches the currently bound mob. Optionally issue a - * readback/update on the surface while it is still bound to the old - * mobid if the mobid is changed by this command. - */ +} SVGA3dCmdBindGBSurfaceWithPitch; +#pragma pack(pop) #define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0) #define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdCondBindGBSurface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdCondBindGBSurface { uint32 sid; SVGAMobId testMobid; SVGAMobId mobid; uint32 flags; -} -#include "vmware_pack_end.h" -SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */ +} SVGA3dCmdCondBindGBSurface; +#pragma pack(pop) -/* - * Update an image in a guest-backed surface. - * (Inform the device that the guest-contents have been updated.) - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdUpdateGBImage { +#pragma pack(push, 1) +typedef struct SVGA3dCmdUpdateGBImage { SVGA3dSurfaceImageId image; SVGA3dBox box; -} -#include "vmware_pack_end.h" -SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */ +} SVGA3dCmdUpdateGBImage; +#pragma pack(pop) -/* - * Update an entire guest-backed surface. - * (Inform the device that the guest-contents have been updated.) - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdUpdateGBSurface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdUpdateGBSurface { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */ +} SVGA3dCmdUpdateGBSurface; +#pragma pack(pop) -/* - * Readback an image in a guest-backed surface. - * (Request the device to flush the dirty contents into the guest.) - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdReadbackGBImage { +#pragma pack(push, 1) +typedef struct SVGA3dCmdReadbackGBImage { SVGA3dSurfaceImageId image; -} -#include "vmware_pack_end.h" -SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE */ +} SVGA3dCmdReadbackGBImage; +#pragma pack(pop) -/* - * Readback an entire guest-backed surface. - * (Request the device to flush the dirty contents into the guest.) - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdReadbackGBSurface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdReadbackGBSurface { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */ +} SVGA3dCmdReadbackGBSurface; +#pragma pack(pop) -/* - * Readback a sub rect of an image in a guest-backed surface. After - * issuing this command the driver is required to issue an update call - * of the same region before issuing any other commands that reference - * this surface or rendering is not guaranteed. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdReadbackGBImagePartial { +#pragma pack(push, 1) +typedef struct SVGA3dCmdReadbackGBImagePartial { SVGA3dSurfaceImageId image; SVGA3dBox box; uint32 invertBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */ +} SVGA3dCmdReadbackGBImagePartial; +#pragma pack(pop) -/* - * Invalidate an image in a guest-backed surface. - * (Notify the device that the contents can be lost.) - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdInvalidateGBImage { +#pragma pack(push, 1) +typedef struct SVGA3dCmdInvalidateGBImage { SVGA3dSurfaceImageId image; -} -#include "vmware_pack_end.h" -SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */ +} SVGA3dCmdInvalidateGBImage; +#pragma pack(pop) -/* - * Invalidate an entire guest-backed surface. - * (Notify the device that the contents if all images can be lost.) - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdInvalidateGBSurface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdInvalidateGBSurface { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */ +} SVGA3dCmdInvalidateGBSurface; +#pragma pack(pop) -/* - * Invalidate a sub rect of an image in a guest-backed surface. After - * issuing this command the driver is required to issue an update call - * of the same region before issuing any other commands that reference - * this surface or rendering is not guaranteed. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdInvalidateGBImagePartial { +#pragma pack(push, 1) +typedef struct SVGA3dCmdInvalidateGBImagePartial { SVGA3dSurfaceImageId image; SVGA3dBox box; uint32 invertBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */ +} SVGA3dCmdInvalidateGBImagePartial; +#pragma pack(pop) -/* - * Define a guest-backed context. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */ +} SVGA3dCmdDefineGBContext; +#pragma pack(pop) -/* - * Destroy a guest-backed context. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDestroyGBContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDestroyGBContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */ +} SVGA3dCmdDestroyGBContext; +#pragma pack(pop) -/* - * Bind a guest-backed context. - * - * validContents should be set to 0 for new contexts, - * and 1 if this is an old context which is getting paged - * back on to the device. - * - * For new contexts, it is recommended that the driver - * issue commands to initialize all interesting state - * prior to rendering. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdBindGBContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdBindGBContext { uint32 cid; SVGAMobId mobid; uint32 validContents; -} -#include "vmware_pack_end.h" -SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */ +} SVGA3dCmdBindGBContext; +#pragma pack(pop) -/* - * Readback a guest-backed context. - * (Request that the device flush the contents back into guest memory.) - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdReadbackGBContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdReadbackGBContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */ +} SVGA3dCmdReadbackGBContext; +#pragma pack(pop) -/* - * Invalidate a guest-backed context. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdInvalidateGBContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdInvalidateGBContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */ +} SVGA3dCmdInvalidateGBContext; +#pragma pack(pop) -/* - * Define a guest-backed shader. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDefineGBShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDefineGBShader { uint32 shid; SVGA3dShaderType type; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */ +} SVGA3dCmdDefineGBShader; +#pragma pack(pop) -/* - * Bind a guest-backed shader. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdBindGBShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdBindGBShader { uint32 shid; SVGAMobId mobid; uint32 offsetInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */ +} SVGA3dCmdBindGBShader; +#pragma pack(pop) -/* - * Destroy a guest-backed shader. - */ - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDestroyGBShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDestroyGBShader { uint32 shid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */ +} SVGA3dCmdDestroyGBShader; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - uint32 regStart; - SVGA3dShaderType shaderType; - SVGA3dShaderConstType constType; +#pragma pack(push, 1) +typedef struct { + uint32 cid; + uint32 regStart; + SVGA3dShaderType shaderType; + SVGA3dShaderConstType constType; - /* - * Followed by a variable number of shader constants. - * - * Note that FLOAT and INT constants are 4-dwords in length, while - * BOOL constants are 1-dword in length. - */ -} -#include "vmware_pack_end.h" -SVGA3dCmdSetGBShaderConstInline; /* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */ +} SVGA3dCmdSetGBShaderConstInline; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dQueryType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */ +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dQueryType type; +} SVGA3dCmdBeginGBQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dQueryType type; +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dQueryType type; SVGAMobId mobid; uint32 offset; -} -#include "vmware_pack_end.h" -SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */ +} SVGA3dCmdEndGBQuery; +#pragma pack(pop) -/* - * SVGA_3D_CMD_WAIT_FOR_GB_QUERY -- - * - * The semantics of this command are identical to the - * SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written - * to a Mob instead of a GMR. - */ - -typedef -#include "vmware_pack_begin.h" -struct { - uint32 cid; - SVGA3dQueryType type; +#pragma pack(push, 1) +typedef struct { + uint32 cid; + SVGA3dQueryType type; SVGAMobId mobid; uint32 offset; -} -#include "vmware_pack_end.h" -SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */ +} SVGA3dCmdWaitForGBQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAMobId mobid; uint32 mustBeZero; uint32 initialized; -} -#include "vmware_pack_end.h" -SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */ +} SVGA3dCmdEnableGart; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGAMobId mobid; uint32 gartOffset; -} -#include "vmware_pack_end.h" -SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */ +} SVGA3dCmdMapMobIntoGart; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 gartOffset; uint32 numPages; -} -#include "vmware_pack_end.h" -SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */ +} SVGA3dCmdUnmapGartRange; +#pragma pack(pop) -/* - * Screen Targets - */ - -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 stid; uint32 width; uint32 height; @@ -2166,119 +1433,92 @@ struct { int32 yRoot; SVGAScreenTargetFlags flags; - /* - * The physical DPI that the guest expects this screen displayed at. - * - * Guests which are not DPI-aware should set this to zero. - */ uint32 dpi; -} -#include "vmware_pack_end.h" -SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */ +} SVGA3dCmdDefineGBScreenTarget; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 stid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */ +} SVGA3dCmdDestroyGBScreenTarget; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 stid; SVGA3dSurfaceImageId image; -} -#include "vmware_pack_end.h" -SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */ +} SVGA3dCmdBindGBScreenTarget; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 stid; SVGA3dRect rect; -} -#include "vmware_pack_end.h" -SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */ +} SVGA3dCmdUpdateGBScreenTarget; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 stid; SVGA3dRect rect; SVGA3dFrameUpdateType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdUpdateGBScreenTarget_v2; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_V2 */ +} SVGA3dCmdUpdateGBScreenTarget_v2; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 stid; SVGA3dRect rect; SVGA3dFrameUpdateType type; SVGAUnsignedPoint srcPoint; -} -#include "vmware_pack_end.h" -SVGA3dCmdUpdateGBScreenTargetMove; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_MOVE */ +} SVGA3dCmdUpdateGBScreenTargetMove; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdGBScreenDMA { +#pragma pack(push, 1) +typedef struct SVGA3dCmdGBScreenDMA { uint32 screenId; uint32 dead; SVGAMobId destMobID; uint32 destPitch; SVGAMobId changeMapMobID; -} -#include "vmware_pack_end.h" -SVGA3dCmdGBScreenDMA; /* SVGA_3D_CMD_GB_SCREEN_DMA */ +} SVGA3dCmdGBScreenDMA; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 value; uint32 mobId; uint32 mobOffset; -} -#include "vmware_pack_end.h" -SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE */ +} SVGA3dCmdGBMobFence; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 stid; SVGA3dSurfaceImageId dest; uint32 statusMobId; uint32 statusMobOffset; - /* Reserved fields */ uint32 mustBeInvalidId; uint32 mustBeZero; -} -#include "vmware_pack_end.h" -SVGA3dCmdScreenCopy; /* SVGA_3D_CMD_SCREEN_COPY */ +} SVGA3dCmdScreenCopy; +#pragma pack(pop) #define SVGA_SCREEN_COPY_STATUS_FAILURE 0x00 #define SVGA_SCREEN_COPY_STATUS_SUCCESS 0x01 #define SVGA_SCREEN_COPY_STATUS_INVALID 0xFFFFFFFF -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdWriteZeroSurface; /* SVGA_3D_CMD_WRITE_ZERO_SURFACE */ +} SVGA3dCmdWriteZeroSurface; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 sid; -} -#include "vmware_pack_end.h" -SVGA3dCmdUpdateZeroSurface; /* SVGA_3D_CMD_UPDATE_ZERO_SURFACE */ +} SVGA3dCmdUpdateZeroSurface; +#pragma pack(pop) -#endif // _SVGA3D_CMD_H_ +#endif diff --git a/src/gallium/drivers/svga/include/svga3d_devcaps.h b/src/gallium/drivers/svga/include/svga3d_devcaps.h index cd38f7b57be..8b8dd5d9c6a 100644 --- a/src/gallium/drivers/svga/include/svga3d_devcaps.h +++ b/src/gallium/drivers/svga/include/svga3d_devcaps.h @@ -1,463 +1,368 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 1998-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-3.0 OR MIT + * Copyright (c) 1998-2021 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* * svga3d_devcaps.h -- * - * SVGA 3d caps definitions + * SVGA 3d caps definitions */ #ifndef _SVGA3D_DEVCAPS_H_ #define _SVGA3D_DEVCAPS_H_ -#define INCLUDE_ALLOW_MODULE -#define INCLUDE_ALLOW_USERLEVEL -#define INCLUDE_ALLOW_VMCORE +#include "svga3d_types.h" -#include "includeCheck.h" - -/* - * 3D Hardware Version - * - * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo - * register. Is set by the host and read by the guest. This lets - * us make new guest drivers which are backwards-compatible with old - * SVGA hardware revisions. It does not let us support old guest - * drivers. Good enough for now. - * - */ - -#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) -#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16) -#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF) +#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) +#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16) +#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF) typedef enum { - SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1), - SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2), - SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3), - SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1), + SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1), + SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2), + SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3), + SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1), SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4), - SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0), - SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1), - SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1, + SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0), + SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1), + SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1, } SVGA3dHardwareVersion; -/* - * DevCap indexes. - */ +typedef uint32 SVGA3dDevCapIndex; -typedef enum { - SVGA3D_DEVCAP_INVALID = ((uint32)-1), - SVGA3D_DEVCAP_3D = 0, - SVGA3D_DEVCAP_MAX_LIGHTS = 1, +#define SVGA3D_DEVCAP_INVALID ((uint32) - 1) +#define SVGA3D_DEVCAP_3D 0 +#define SVGA3D_DEVCAP_MAX_LIGHTS 1 - /* - * SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of - * fixed-function texture units available. Each of these units - * work in both FFP and Shader modes, and they support texture - * transforms and texture coordinates. The host may have additional - * texture image units that are only usable with shaders. - */ - SVGA3D_DEVCAP_MAX_TEXTURES = 2, - SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3, - SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4, - SVGA3D_DEVCAP_VERTEX_SHADER = 5, - SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6, - SVGA3D_DEVCAP_FRAGMENT_SHADER = 7, - SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8, - SVGA3D_DEVCAP_S23E8_TEXTURES = 9, - SVGA3D_DEVCAP_S10E5_TEXTURES = 10, - SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11, - SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, - SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, - SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, - SVGA3D_DEVCAP_QUERY_TYPES = 15, - SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16, - SVGA3D_DEVCAP_MAX_POINT_SIZE = 17, - SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18, - SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19, - SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20, - SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21, - SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22, - SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23, - SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24, - SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25, - SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26, - SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27, - SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28, - SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29, - SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30, - SVGA3D_DEVCAP_TEXTURE_OPS = 31, - SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32, - SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33, - SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34, - SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35, - SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36, - SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37, - SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38, - SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39, - SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40, - SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41, - SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42, - SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43, - SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44, - SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45, - SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46, - SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47, - SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48, - SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49, - SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50, - SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51, - SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52, - SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53, - SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54, - SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55, - SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56, - SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57, - SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58, - SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59, - SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60, - SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61, +#define SVGA3D_DEVCAP_MAX_TEXTURES 2 +#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3 +#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4 +#define SVGA3D_DEVCAP_VERTEX_SHADER 5 +#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6 +#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7 +#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8 +#define SVGA3D_DEVCAP_S23E8_TEXTURES 9 +#define SVGA3D_DEVCAP_S10E5_TEXTURES 10 +#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11 +#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12 +#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13 +#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14 +#define SVGA3D_DEVCAP_QUERY_TYPES 15 +#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16 +#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17 +#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18 +#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19 +#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20 +#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21 +#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22 +#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23 +#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24 +#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25 +#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26 +#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27 +#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28 +#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29 +#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30 +#define SVGA3D_DEVCAP_TEXTURE_OPS 31 +#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32 +#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33 +#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34 +#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35 +#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36 +#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37 +#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38 +#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39 +#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40 +#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41 +#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42 +#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43 +#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44 +#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45 +#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46 +#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47 +#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48 +#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49 +#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50 +#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51 +#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52 +#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53 +#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54 +#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55 +#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56 +#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57 +#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58 +#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59 +#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60 +#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61 - /* - * There is a hole in our devcap definitions for - * historical reasons. - * - * Define a constant just for completeness. - */ - SVGA3D_DEVCAP_MISSING62 = 62, +#define SVGA3D_DEVCAP_MISSING62 62 - SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63, +#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63 - /* - * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color - * render targets. This does not include the depth or stencil targets. - */ - SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64, +#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64 - SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65, - SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66, - SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67, - SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68, - SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69, +#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65 +#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66 +#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67 +#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68 +#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69 - /* - * Deprecated. - */ - SVGA3D_DEVCAP_DEAD4 = 70, - SVGA3D_DEVCAP_DEAD5 = 71, - SVGA3D_DEVCAP_DEAD7 = 72, - SVGA3D_DEVCAP_DEAD6 = 73, +#define SVGA3D_DEVCAP_DEAD4 70 +#define SVGA3D_DEVCAP_DEAD5 71 +#define SVGA3D_DEVCAP_DEAD7 72 +#define SVGA3D_DEVCAP_DEAD6 73 - SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74, - SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75, - SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76, +#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74 +#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75 +#define SVGA3D_DEVCAP_DEAD10 76 - /* - * This is the maximum number of SVGA context IDs that the guest - * can define using SVGA_3D_CMD_CONTEXT_DEFINE. - */ - SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77, +#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77 - /* - * This is the maximum number of SVGA surface IDs that the guest - * can define using SVGA_3D_CMD_SURFACE_DEFINE*. - */ - SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78, +#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78 - SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79, - SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80, - SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81, +#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79 +#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80 +#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81 - SVGA3D_DEVCAP_SURFACEFMT_ATI1 = 82, - SVGA3D_DEVCAP_SURFACEFMT_ATI2 = 83, +#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82 +#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83 - /* - * Deprecated. - */ - SVGA3D_DEVCAP_DEAD1 = 84, - SVGA3D_DEVCAP_DEAD8 = 85, - SVGA3D_DEVCAP_DEAD9 = 86, +#define SVGA3D_DEVCAP_DEAD1 84 +#define SVGA3D_DEVCAP_DEAD8 85 +#define SVGA3D_DEVCAP_DEAD9 86 - SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */ - SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */ - SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */ - SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */ +#define SVGA3D_DEVCAP_LINE_AA 87 +#define SVGA3D_DEVCAP_LINE_STIPPLE 88 +#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89 +#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90 - SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91, +#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91 - /* - * Deprecated. - */ - SVGA3D_DEVCAP_DEAD3 = 92, +#define SVGA3D_DEVCAP_DEAD3 92 - /* - * Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported? - */ - SVGA3D_DEVCAP_TS_COLOR_KEY = 93, /* boolean */ +#define SVGA3D_DEVCAP_TS_COLOR_KEY 93 - /* - * Deprecated. - */ - SVGA3D_DEVCAP_DEAD2 = 94, +#define SVGA3D_DEVCAP_DEAD2 94 - /* - * Does the device support DXContexts? (ie DX10 era rendering) - */ - SVGA3D_DEVCAP_DXCONTEXT = 95, +#define SVGA3D_DEVCAP_DXCONTEXT 95 - /* - * What is the maximum size of a texture array? - * - * (Even if this cap is zero, cubemaps are still allowed.) - */ - SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96, +#define SVGA3D_DEVCAP_DEAD11 96 - /* - * What is the maximum number of vertex buffers or vertex input registers - * that can be expected to work correctly with a DXContext? - * - * The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but - * anything in excess of this cap is not guaranteed to render correctly. - * - * Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS - * input registers without the SVGA3D_DEVCAP_SM4_1 cap, or - * SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1, - * but only the registers up to this cap value are guaranteed to render - * correctly. - * - * If guest-drivers are able to expose a lower-limit, it's recommended - * that they clamp to this value. Otherwise, the host will make a - * best-effort on case-by-case basis if guests exceed this. - */ - SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97, +#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97 - /* - * What is the maximum number of constant buffers that can be expected to - * work correctly with a DX context? - * - * The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but - * anything in excess of this cap is not guaranteed to render correctly. - * - * If guest-drivers are able to expose a lower-limit, it's recommended - * that they clamp to this value. Otherwise, the host will make a - * best-effort on case-by-case basis if guests exceed this. - */ - SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98, +#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98 - /* - * Does the device support provoking vertex control? - * - * If this cap is present, the provokingVertexLast field in the - * rasterizer state is enabled. (Guests can then set it to FALSE, - * meaning that the first vertex is the provoking vertex, or TRUE, - * meaning that the last vertex is the provoking vertex.) - * - * If this cap is FALSE, then guests should set the provokingVertexLast - * to FALSE, otherwise rendering behavior is undefined. - */ - SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99, +#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99 - SVGA3D_DEVCAP_DXFMT_X8R8G8B8 = 100, - SVGA3D_DEVCAP_DXFMT_A8R8G8B8 = 101, - SVGA3D_DEVCAP_DXFMT_R5G6B5 = 102, - SVGA3D_DEVCAP_DXFMT_X1R5G5B5 = 103, - SVGA3D_DEVCAP_DXFMT_A1R5G5B5 = 104, - SVGA3D_DEVCAP_DXFMT_A4R4G4B4 = 105, - SVGA3D_DEVCAP_DXFMT_Z_D32 = 106, - SVGA3D_DEVCAP_DXFMT_Z_D16 = 107, - SVGA3D_DEVCAP_DXFMT_Z_D24S8 = 108, - SVGA3D_DEVCAP_DXFMT_Z_D15S1 = 109, - SVGA3D_DEVCAP_DXFMT_LUMINANCE8 = 110, - SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 = 111, - SVGA3D_DEVCAP_DXFMT_LUMINANCE16 = 112, - SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 = 113, - SVGA3D_DEVCAP_DXFMT_DXT1 = 114, - SVGA3D_DEVCAP_DXFMT_DXT2 = 115, - SVGA3D_DEVCAP_DXFMT_DXT3 = 116, - SVGA3D_DEVCAP_DXFMT_DXT4 = 117, - SVGA3D_DEVCAP_DXFMT_DXT5 = 118, - SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119, - SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120, - SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121, - SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 = 122, - SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123, - SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124, - SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125, - SVGA3D_DEVCAP_DXFMT_V8U8 = 126, - SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 = 127, - SVGA3D_DEVCAP_DXFMT_CxV8U8 = 128, - SVGA3D_DEVCAP_DXFMT_X8L8V8U8 = 129, - SVGA3D_DEVCAP_DXFMT_A2W10V10U10 = 130, - SVGA3D_DEVCAP_DXFMT_ALPHA8 = 131, - SVGA3D_DEVCAP_DXFMT_R_S10E5 = 132, - SVGA3D_DEVCAP_DXFMT_R_S23E8 = 133, - SVGA3D_DEVCAP_DXFMT_RG_S10E5 = 134, - SVGA3D_DEVCAP_DXFMT_RG_S23E8 = 135, - SVGA3D_DEVCAP_DXFMT_BUFFER = 136, - SVGA3D_DEVCAP_DXFMT_Z_D24X8 = 137, - SVGA3D_DEVCAP_DXFMT_V16U16 = 138, - SVGA3D_DEVCAP_DXFMT_G16R16 = 139, - SVGA3D_DEVCAP_DXFMT_A16B16G16R16 = 140, - SVGA3D_DEVCAP_DXFMT_UYVY = 141, - SVGA3D_DEVCAP_DXFMT_YUY2 = 142, - SVGA3D_DEVCAP_DXFMT_NV12 = 143, - SVGA3D_DEVCAP_FORMAT_DEAD2 = 144, - SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS = 145, - SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT = 146, - SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT = 147, - SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS = 148, - SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT = 149, - SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT = 150, - SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT = 151, - SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS = 152, - SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT = 153, - SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM = 154, - SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT = 155, - SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS = 156, - SVGA3D_DEVCAP_DXFMT_R32G32_UINT = 157, - SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158, - SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159, - SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160, - SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 = 161, - SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT = 162, - SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163, - SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164, - SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165, - SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS = 166, - SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM = 167, - SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB = 168, - SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT = 169, - SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT = 170, - SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS = 171, - SVGA3D_DEVCAP_DXFMT_R16G16_UINT = 172, - SVGA3D_DEVCAP_DXFMT_R16G16_SINT = 173, - SVGA3D_DEVCAP_DXFMT_R32_TYPELESS = 174, - SVGA3D_DEVCAP_DXFMT_D32_FLOAT = 175, - SVGA3D_DEVCAP_DXFMT_R32_UINT = 176, - SVGA3D_DEVCAP_DXFMT_R32_SINT = 177, - SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178, - SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179, - SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 = 180, - SVGA3D_DEVCAP_DXFMT_X24_G8_UINT = 181, - SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182, - SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183, - SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184, - SVGA3D_DEVCAP_DXFMT_R8G8_SINT = 185, - SVGA3D_DEVCAP_DXFMT_R16_TYPELESS = 186, - SVGA3D_DEVCAP_DXFMT_R16_UNORM = 187, - SVGA3D_DEVCAP_DXFMT_R16_UINT = 188, - SVGA3D_DEVCAP_DXFMT_R16_SNORM = 189, - SVGA3D_DEVCAP_DXFMT_R16_SINT = 190, - SVGA3D_DEVCAP_DXFMT_R8_TYPELESS = 191, - SVGA3D_DEVCAP_DXFMT_R8_UNORM = 192, - SVGA3D_DEVCAP_DXFMT_R8_UINT = 193, - SVGA3D_DEVCAP_DXFMT_R8_SNORM = 194, - SVGA3D_DEVCAP_DXFMT_R8_SINT = 195, - SVGA3D_DEVCAP_DXFMT_P8 = 196, - SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP = 197, - SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM = 198, - SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM = 199, - SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS = 200, - SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB = 201, - SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS = 202, - SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB = 203, - SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS = 204, - SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB = 205, - SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS = 206, - SVGA3D_DEVCAP_DXFMT_ATI1 = 207, - SVGA3D_DEVCAP_DXFMT_BC4_SNORM = 208, - SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS = 209, - SVGA3D_DEVCAP_DXFMT_ATI2 = 210, - SVGA3D_DEVCAP_DXFMT_BC5_SNORM = 211, - SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM = 212, - SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS = 213, - SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB = 214, - SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS = 215, - SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB = 216, - SVGA3D_DEVCAP_DXFMT_Z_DF16 = 217, - SVGA3D_DEVCAP_DXFMT_Z_DF24 = 218, - SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT = 219, - SVGA3D_DEVCAP_DXFMT_YV12 = 220, - SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT = 221, - SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT = 222, - SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM = 223, - SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT = 224, - SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM = 225, - SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM = 226, - SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT = 227, - SVGA3D_DEVCAP_DXFMT_R16G16_UNORM = 228, - SVGA3D_DEVCAP_DXFMT_R16G16_SNORM = 229, - SVGA3D_DEVCAP_DXFMT_R32_FLOAT = 230, - SVGA3D_DEVCAP_DXFMT_R8G8_SNORM = 231, - SVGA3D_DEVCAP_DXFMT_R16_FLOAT = 232, - SVGA3D_DEVCAP_DXFMT_D16_UNORM = 233, - SVGA3D_DEVCAP_DXFMT_A8_UNORM = 234, - SVGA3D_DEVCAP_DXFMT_BC1_UNORM = 235, - SVGA3D_DEVCAP_DXFMT_BC2_UNORM = 236, - SVGA3D_DEVCAP_DXFMT_BC3_UNORM = 237, - SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM = 238, - SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM = 239, - SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM = 240, - SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM = 241, - SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242, - SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243, +#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100 +#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101 +#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102 +#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103 +#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104 +#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105 +#define SVGA3D_DEVCAP_DXFMT_Z_D32 106 +#define SVGA3D_DEVCAP_DXFMT_Z_D16 107 +#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108 +#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109 +#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110 +#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111 +#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112 +#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113 +#define SVGA3D_DEVCAP_DXFMT_DXT1 114 +#define SVGA3D_DEVCAP_DXFMT_DXT2 115 +#define SVGA3D_DEVCAP_DXFMT_DXT3 116 +#define SVGA3D_DEVCAP_DXFMT_DXT4 117 +#define SVGA3D_DEVCAP_DXFMT_DXT5 118 +#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119 +#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120 +#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121 +#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122 +#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123 +#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124 +#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125 +#define SVGA3D_DEVCAP_DXFMT_V8U8 126 +#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127 +#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128 +#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129 +#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130 +#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131 +#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132 +#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133 +#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134 +#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135 +#define SVGA3D_DEVCAP_DXFMT_BUFFER 136 +#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137 +#define SVGA3D_DEVCAP_DXFMT_V16U16 138 +#define SVGA3D_DEVCAP_DXFMT_G16R16 139 +#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140 +#define SVGA3D_DEVCAP_DXFMT_UYVY 141 +#define SVGA3D_DEVCAP_DXFMT_YUY2 142 +#define SVGA3D_DEVCAP_DXFMT_NV12 143 +#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151 +#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152 +#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153 +#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154 +#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155 +#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156 +#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157 +#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158 +#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159 +#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160 +#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161 +#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162 +#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163 +#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164 +#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165 +#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166 +#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167 +#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168 +#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169 +#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170 +#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171 +#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172 +#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173 +#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174 +#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175 +#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176 +#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177 +#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178 +#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179 +#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180 +#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181 +#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182 +#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183 +#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184 +#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185 +#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186 +#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187 +#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188 +#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189 +#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190 +#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191 +#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192 +#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193 +#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194 +#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195 +#define SVGA3D_DEVCAP_DXFMT_P8 196 +#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197 +#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198 +#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199 +#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200 +#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201 +#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202 +#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203 +#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204 +#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205 +#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206 +#define SVGA3D_DEVCAP_DXFMT_ATI1 207 +#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208 +#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209 +#define SVGA3D_DEVCAP_DXFMT_ATI2 210 +#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211 +#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212 +#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213 +#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214 +#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215 +#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216 +#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217 +#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218 +#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219 +#define SVGA3D_DEVCAP_DXFMT_YV12 220 +#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221 +#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222 +#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223 +#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224 +#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225 +#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226 +#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227 +#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228 +#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229 +#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230 +#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231 +#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232 +#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233 +#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234 +#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235 +#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236 +#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237 +#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238 +#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239 +#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240 +#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241 +#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242 +#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243 - SVGA3D_DEVCAP_SM41 = 244, - SVGA3D_DEVCAP_MULTISAMPLE_2X = 245, - SVGA3D_DEVCAP_MULTISAMPLE_4X = 246, - SVGA3D_DEVCAP_MS_FULL_QUALITY = 247, - SVGA3D_DEVCAP_LOGICOPS = 248, - SVGA3D_DEVCAP_LOGIC_BLENDOPS = 249, +#define SVGA3D_DEVCAP_SM41 244 +#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245 +#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246 - SVGA3D_DEVCAP_DEAD12 = 250, +#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247 - SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS = 251, - SVGA3D_DEVCAP_DXFMT_BC6H_UF16 = 252, - SVGA3D_DEVCAP_DXFMT_BC6H_SF16 = 253, - SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS = 254, - SVGA3D_DEVCAP_DXFMT_BC7_UNORM = 255, - SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB = 256, - SVGA3D_DEVCAP_DEAD13 = 257, - SVGA3D_DEVCAP_SM5 = 258, - SVGA3D_DEVCAP_MULTISAMPLE_8X = 259, - SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT = 260, - SVGA3D_DEVCAP_GL43 = 261, - SVGA3D_DEVCAP_MAX = 262, +#define SVGA3D_DEVCAP_LOGICOPS 248 -} SVGA3dDevCapIndex; +#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249 -/* - * Bit definitions for DXFMT devcaps - * - * See also: - * http://msdn.microsoft.com/en-gb/library/windows/hardware/ff539390.aspx - * - * SUPPORTED: Can the format be defined? - * SHADER_SAMPLE: Can the format be sampled from a shader? - * COLOR_RENDERTARGET: Can the format be a color render target? - * DEPTH_RENDERTARGET: Can the format be a depth render target? - * BLENDABLE: Is the format blendable? - * MIPS: Does the format support mip levels? - * ARRAY: Does the format support texture arrays? - * VOLUME: Does the format support having volume? - * MULTISAMPLE: Does the format support multisample? - */ -#define SVGA3D_DXFMT_SUPPORTED (1 << 0) -#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1) -#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2) -#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3) -#define SVGA3D_DXFMT_BLENDABLE (1 << 4) -#define SVGA3D_DXFMT_MIPS (1 << 5) -#define SVGA3D_DXFMT_ARRAY (1 << 6) -#define SVGA3D_DXFMT_VOLUME (1 << 7) -#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8) -#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9) -#define SVGA3D_DXFMT_MAX (1 << 10) +#define SVGA3D_DEVCAP_DEAD12 250 + +#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251 +#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252 +#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253 +#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254 +#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255 +#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256 + +#define SVGA3D_DEVCAP_DEAD13 257 + +#define SVGA3D_DEVCAP_SM5 258 +#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259 + +#define SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT 260 + +#define SVGA3D_DEVCAP_GL43 261 + +#define SVGA3D_DEVCAP_MAX 262 + +#define SVGA3D_DXFMT_SUPPORTED (1 << 0) +#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1) +#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2) +#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3) +#define SVGA3D_DXFMT_BLENDABLE (1 << 4) +#define SVGA3D_DXFMT_MIPS (1 << 5) +#define SVGA3D_DXFMT_ARRAY (1 << 6) +#define SVGA3D_DXFMT_VOLUME (1 << 7) +#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8) +#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9) +#define SVGA3D_DXFMT_MAX (1 << 10) typedef union { SVGA3dBool b; @@ -466,4 +371,4 @@ typedef union { float f; } SVGA3dDevCapResult; -#endif /* _SVGA3D_DEVCAPS_H_ */ +#endif diff --git a/src/gallium/drivers/svga/include/svga3d_dx.h b/src/gallium/drivers/svga/include/svga3d_dx.h index 43ad96f3693..2031aa67dec 100644 --- a/src/gallium/drivers/svga/include/svga3d_dx.h +++ b/src/gallium/drivers/svga/include/svga3d_dx.h @@ -1,8 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2012-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2012-2023 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* @@ -11,22 +31,12 @@ * SVGA 3d hardware definitions for DX10 support. */ - - - - #ifndef _SVGA3D_DX_H_ #define _SVGA3D_DX_H_ - - - - - -#include "svga_reg.h" #include "svga3d_limits.h" #include "svga3d_types.h" - +#include "svga_reg.h" #define SVGA3D_INPUT_MIN 0 #define SVGA3D_INPUT_PER_VERTEX_DATA 0 @@ -34,22 +44,19 @@ #define SVGA3D_INPUT_MAX 2 typedef uint32 SVGA3dInputClassification; -#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0) -#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1) -#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2) -#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3) -#define SVGA3D_COLOR_WRITE_ENABLE_ALL (SVGA3D_COLOR_WRITE_ENABLE_RED | \ - SVGA3D_COLOR_WRITE_ENABLE_GREEN | \ - SVGA3D_COLOR_WRITE_ENABLE_BLUE | \ - SVGA3D_COLOR_WRITE_ENABLE_ALPHA) +#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0) +#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1) +#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2) +#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3) +#define SVGA3D_COLOR_WRITE_ENABLE_ALL \ + (SVGA3D_COLOR_WRITE_ENABLE_RED | SVGA3D_COLOR_WRITE_ENABLE_GREEN | \ + SVGA3D_COLOR_WRITE_ENABLE_BLUE | SVGA3D_COLOR_WRITE_ENABLE_ALPHA) typedef uint8 SVGA3dColorWriteEnable; - -#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0 -#define SVGA3D_DEPTH_WRITE_MASK_ALL 1 +#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0 +#define SVGA3D_DEPTH_WRITE_MASK_ALL 1 typedef uint8 SVGA3dDepthWriteMask; - #define SVGA3D_FILTER_MIP_LINEAR (1 << 0) #define SVGA3D_FILTER_MAG_LINEAR (1 << 2) #define SVGA3D_FILTER_MIN_LINEAR (1 << 4) @@ -57,7 +64,6 @@ typedef uint8 SVGA3dDepthWriteMask; #define SVGA3D_FILTER_COMPARE (1 << 7) typedef uint32 SVGA3dFilter; - #define SVGA3D_CULL_INVALID 0 #define SVGA3D_CULL_MIN 1 #define SVGA3D_CULL_NONE 1 @@ -66,36 +72,34 @@ typedef uint32 SVGA3dFilter; #define SVGA3D_CULL_MAX 4 typedef uint8 SVGA3dCullMode; - -#define SVGA3D_COMPARISON_INVALID 0 -#define SVGA3D_COMPARISON_MIN 1 -#define SVGA3D_COMPARISON_NEVER 1 -#define SVGA3D_COMPARISON_LESS 2 -#define SVGA3D_COMPARISON_EQUAL 3 -#define SVGA3D_COMPARISON_LESS_EQUAL 4 -#define SVGA3D_COMPARISON_GREATER 5 -#define SVGA3D_COMPARISON_NOT_EQUAL 6 -#define SVGA3D_COMPARISON_GREATER_EQUAL 7 -#define SVGA3D_COMPARISON_ALWAYS 8 -#define SVGA3D_COMPARISON_MAX 9 +#define SVGA3D_COMPARISON_INVALID 0 +#define SVGA3D_COMPARISON_MIN 1 +#define SVGA3D_COMPARISON_NEVER 1 +#define SVGA3D_COMPARISON_LESS 2 +#define SVGA3D_COMPARISON_EQUAL 3 +#define SVGA3D_COMPARISON_LESS_EQUAL 4 +#define SVGA3D_COMPARISON_GREATER 5 +#define SVGA3D_COMPARISON_NOT_EQUAL 6 +#define SVGA3D_COMPARISON_GREATER_EQUAL 7 +#define SVGA3D_COMPARISON_ALWAYS 8 +#define SVGA3D_COMPARISON_MAX 9 typedef uint8 SVGA3dComparisonFunc; - -#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0 -#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1 -#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1 -#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2 -#define SVGA3D_MULTISAMPLE_RAST_MAX 2 +#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0 +#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1 +#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1 +#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2 +#define SVGA3D_MULTISAMPLE_RAST_MAX 2 typedef uint8 SVGA3dMultisampleRastEnable; -#define SVGA3D_DX_MAX_VERTEXBUFFERS 32 -#define SVGA3D_DX_MAX_VERTEXINPUTREGISTERS 16 +#define SVGA3D_DX_MAX_VERTEXBUFFERS 32 +#define SVGA3D_DX_MAX_VERTEXINPUTREGISTERS 16 #define SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS 32 -#define SVGA3D_DX_MAX_SOTARGETS 4 -#define SVGA3D_DX_MAX_SRVIEWS 128 -#define SVGA3D_DX_MAX_CONSTBUFFERS 16 -#define SVGA3D_DX_MAX_SAMPLERS 16 -#define SVGA3D_DX_MAX_CLASS_INSTANCES 253 +#define SVGA3D_DX_MAX_SOTARGETS 4 +#define SVGA3D_DX_MAX_SRVIEWS 128 +#define SVGA3D_DX_MAX_CONSTBUFFERS 16 +#define SVGA3D_DX_MAX_SAMPLERS 16 +#define SVGA3D_DX_MAX_CLASS_INSTANCES 253 #define SVGA3D_DX_MAX_CONSTBUF_BINDING_SIZE (4096 * 4 * (uint32)sizeof(uint32)) @@ -124,86 +128,69 @@ typedef union { uint32 value[4]; } SVGA3dRGBAUint32; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 cid; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGAOTableDXContextEntry; +} SVGAOTableDXContextEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineContext; +} SVGA3dCmdDXDefineContext; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyContext; +} SVGA3dCmdDXDestroyContext; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBindContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBindContext { uint32 cid; SVGAMobId mobid; uint32 validContents; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBindContext; +} SVGA3dCmdDXBindContext; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXReadbackContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXReadbackContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXReadbackContext; +} SVGA3dCmdDXReadbackContext; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXInvalidateContext { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXInvalidateContext { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXInvalidateContext; +} SVGA3dCmdDXInvalidateContext; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetSingleConstantBuffer { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetSingleConstantBuffer { uint32 slot; SVGA3dShaderType type; SVGA3dSurfaceId sid; uint32 offsetInBytes; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetSingleConstantBuffer; +} SVGA3dCmdDXSetSingleConstantBuffer; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetShaderResources { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetShaderResources { uint32 startView; SVGA3dShaderType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetShaderResources; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetShader { +} SVGA3dCmdDXSetShaderResources; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetShader { SVGA3dShaderId shaderId; SVGA3dShaderType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetShader; +} SVGA3dCmdDXSetShader; +#pragma pack(pop) typedef union { struct { @@ -216,484 +203,392 @@ typedef union { uint32 value; } SVGA3dIfaceData; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetShaderIface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetShaderIface { SVGA3dShaderType type; uint32 numClassInstances; uint32 index; uint32 iface; SVGA3dIfaceData data; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetShaderIface; +} SVGA3dCmdDXSetShaderIface; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBindShaderIface { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBindShaderIface { uint32 cid; SVGAMobId mobid; uint32 offsetInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBindShaderIface; +} SVGA3dCmdDXBindShaderIface; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetSamplers { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetSamplers { uint32 startSampler; SVGA3dShaderType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetSamplers; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDraw { +} SVGA3dCmdDXSetSamplers; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDraw { uint32 vertexCount; uint32 startVertexLocation; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDraw; +} SVGA3dCmdDXDraw; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDrawIndexed { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDrawIndexed { uint32 indexCount; uint32 startIndexLocation; - int32 baseVertexLocation; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDrawIndexed; + int32 baseVertexLocation; +} SVGA3dCmdDXDrawIndexed; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDrawInstanced { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDrawInstanced { uint32 vertexCountPerInstance; uint32 instanceCount; uint32 startVertexLocation; uint32 startInstanceLocation; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDrawInstanced; +} SVGA3dCmdDXDrawInstanced; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDrawIndexedInstanced { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDrawIndexedInstanced { uint32 indexCountPerInstance; uint32 instanceCount; uint32 startIndexLocation; - int32 baseVertexLocation; + int32 baseVertexLocation; uint32 startInstanceLocation; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDrawIndexedInstanced; +} SVGA3dCmdDXDrawIndexedInstanced; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDrawIndexedInstancedIndirect { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDrawIndexedInstancedIndirect { SVGA3dSurfaceId argsBufferSid; uint32 byteOffsetForArgs; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDrawIndexedInstancedIndirect; +} SVGA3dCmdDXDrawIndexedInstancedIndirect; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDrawInstancedIndirect { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDrawInstancedIndirect { SVGA3dSurfaceId argsBufferSid; uint32 byteOffsetForArgs; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDrawInstancedIndirect; +} SVGA3dCmdDXDrawInstancedIndirect; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDrawAuto { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDrawAuto { uint32 pad0; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDrawAuto; +} SVGA3dCmdDXDrawAuto; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDispatch { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDispatch { uint32 threadGroupCountX; uint32 threadGroupCountY; uint32 threadGroupCountZ; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDispatch; +} SVGA3dCmdDXDispatch; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDispatchIndirect { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDispatchIndirect { SVGA3dSurfaceId argsBufferSid; uint32 byteOffsetForArgs; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDispatchIndirect; +} SVGA3dCmdDXDispatchIndirect; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetInputLayout { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetInputLayout { SVGA3dElementLayoutId elementLayoutId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetInputLayout; +} SVGA3dCmdDXSetInputLayout; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dVertexBuffer { +#pragma pack(push, 1) +typedef struct SVGA3dVertexBuffer { SVGA3dSurfaceId sid; uint32 stride; uint32 offset; -} -#include "vmware_pack_end.h" -SVGA3dVertexBuffer; +} SVGA3dVertexBuffer; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetVertexBuffers { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetVertexBuffers { uint32 startBuffer; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetVertexBuffers; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dVertexBuffer_v2 { +} SVGA3dCmdDXSetVertexBuffers; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dVertexBuffer_v2 { SVGA3dSurfaceId sid; uint32 stride; uint32 offset; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dVertexBuffer_v2; +} SVGA3dVertexBuffer_v2; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetVertexBuffers_v2 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetVertexBuffers_v2 { uint32 startBuffer; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetVertexBuffers_v2; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dVertexBufferOffsetAndSize { +} SVGA3dCmdDXSetVertexBuffers_v2; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dVertexBufferOffsetAndSize { uint32 stride; uint32 offset; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dVertexBufferOffsetAndSize; +} SVGA3dVertexBufferOffsetAndSize; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetVertexBuffersOffsetAndSize { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetVertexBuffersOffsetAndSize { uint32 startBuffer; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetVertexBuffersOffsetAndSize; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetIndexBuffer { +} SVGA3dCmdDXSetVertexBuffersOffsetAndSize; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetIndexBuffer { SVGA3dSurfaceId sid; SVGA3dSurfaceFormat format; uint32 offset; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetIndexBuffer; +} SVGA3dCmdDXSetIndexBuffer; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetIndexBuffer_v2 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetIndexBuffer_v2 { SVGA3dSurfaceId sid; SVGA3dSurfaceFormat format; uint32 offset; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetIndexBuffer_v2; +} SVGA3dCmdDXSetIndexBuffer_v2; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetIndexBufferOffsetAndSize { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetIndexBufferOffsetAndSize { SVGA3dSurfaceFormat format; uint32 offset; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetIndexBufferOffsetAndSize; +} SVGA3dCmdDXSetIndexBufferOffsetAndSize; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetTopology { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetTopology { SVGA3dPrimitiveType topology; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetTopology; +} SVGA3dCmdDXSetTopology; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetRenderTargets { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetRenderTargets { SVGA3dDepthStencilViewId depthStencilViewId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetRenderTargets; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetBlendState { +} SVGA3dCmdDXSetRenderTargets; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetBlendState { SVGA3dBlendStateId blendId; float blendFactor[4]; uint32 sampleMask; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetBlendState; +} SVGA3dCmdDXSetBlendState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetDepthStencilState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetDepthStencilState { SVGA3dDepthStencilStateId depthStencilId; uint32 stencilRef; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetDepthStencilState; +} SVGA3dCmdDXSetDepthStencilState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetRasterizerState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetRasterizerState { SVGA3dRasterizerStateId rasterizerId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetRasterizerState; +} SVGA3dCmdDXSetRasterizerState; +#pragma pack(pop) #define SVGA3D_DXQUERY_FLAG_PREDICATEHINT (1 << 0) typedef uint32 SVGA3dDXQueryFlags; - -#define SVGADX_QDSTATE_INVALID ((uint8)-1) -#define SVGADX_QDSTATE_MIN 0 -#define SVGADX_QDSTATE_IDLE 0 -#define SVGADX_QDSTATE_ACTIVE 1 -#define SVGADX_QDSTATE_PENDING 2 -#define SVGADX_QDSTATE_FINISHED 3 -#define SVGADX_QDSTATE_MAX 4 +#define SVGADX_QDSTATE_INVALID ((uint8) - 1) +#define SVGADX_QDSTATE_MIN 0 +#define SVGADX_QDSTATE_IDLE 0 +#define SVGADX_QDSTATE_ACTIVE 1 +#define SVGADX_QDSTATE_PENDING 2 +#define SVGADX_QDSTATE_FINISHED 3 +#define SVGADX_QDSTATE_MAX 4 typedef uint8 SVGADXQueryDeviceState; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dQueryTypeUint8 type; uint16 pad0; SVGADXQueryDeviceState state; SVGA3dDXQueryFlags flags; SVGAMobId mobid; uint32 offset; -} -#include "vmware_pack_end.h" -SVGACOTableDXQueryEntry; +} SVGACOTableDXQueryEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineQuery { SVGA3dQueryId queryId; SVGA3dQueryType type; SVGA3dDXQueryFlags flags; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineQuery; +} SVGA3dCmdDXDefineQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyQuery { SVGA3dQueryId queryId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyQuery; +} SVGA3dCmdDXDestroyQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBindQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBindQuery { SVGA3dQueryId queryId; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBindQuery; +} SVGA3dCmdDXBindQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetQueryOffset { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetQueryOffset { SVGA3dQueryId queryId; uint32 mobOffset; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetQueryOffset; +} SVGA3dCmdDXSetQueryOffset; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBeginQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBeginQuery { SVGA3dQueryId queryId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBeginQuery; +} SVGA3dCmdDXBeginQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXEndQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXEndQuery { SVGA3dQueryId queryId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXEndQuery; +} SVGA3dCmdDXEndQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXReadbackQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXReadbackQuery { SVGA3dQueryId queryId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXReadbackQuery; +} SVGA3dCmdDXReadbackQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXMoveQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXMoveQuery { SVGA3dQueryId queryId; SVGAMobId mobid; uint32 mobOffset; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXMoveQuery; +} SVGA3dCmdDXMoveQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBindAllQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBindAllQuery { uint32 cid; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBindAllQuery; +} SVGA3dCmdDXBindAllQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXReadbackAllQuery { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXReadbackAllQuery { uint32 cid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXReadbackAllQuery; +} SVGA3dCmdDXReadbackAllQuery; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetPredication { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetPredication { SVGA3dQueryId queryId; uint32 predicateValue; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetPredication; +} SVGA3dCmdDXSetPredication; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dDXSOState { +#pragma pack(push, 1) +typedef struct SVGA3dDXSOState { uint32 offset; uint32 intOffset; uint32 dead1; uint32 dead2; -} -#include "vmware_pack_end.h" -SVGA3dDXSOState; +} SVGA3dDXSOState; +#pragma pack(pop) +#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32)~0u) -#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32) ~0u) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dSoTarget { +#pragma pack(push, 1) +typedef struct SVGA3dSoTarget { SVGA3dSurfaceId sid; uint32 offset; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dSoTarget; +} SVGA3dSoTarget; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetSOTargets { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetSOTargets { uint32 pad0; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetSOTargets; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dViewport -{ +} SVGA3dCmdDXSetSOTargets; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dViewport { float x; float y; float width; float height; float minDepth; float maxDepth; -} -#include "vmware_pack_end.h" -SVGA3dViewport; +} SVGA3dViewport; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetViewports { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetViewports { uint32 pad0; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetViewports; -#define SVGA3D_DX_MAX_VIEWPORTS 16 +} SVGA3dCmdDXSetViewports; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetScissorRects { +#define SVGA3D_DX_MAX_VIEWPORTS 16 + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetScissorRects { uint32 pad0; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetScissorRects; -#define SVGA3D_DX_MAX_SCISSORRECTS 16 +} SVGA3dCmdDXSetScissorRects; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXClearRenderTargetView { +#define SVGA3D_DX_MAX_SCISSORRECTS 16 + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXClearRenderTargetView { SVGA3dRenderTargetViewId renderTargetViewId; SVGA3dRGBAFloat rgba; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXClearRenderTargetView; +} SVGA3dCmdDXClearRenderTargetView; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXClearDepthStencilView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXClearDepthStencilView { uint16 flags; uint16 stencil; SVGA3dDepthStencilViewId depthStencilViewId; float depth; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXClearDepthStencilView; +} SVGA3dCmdDXClearDepthStencilView; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredCopyRegion { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredCopyRegion { SVGA3dSurfaceId dstSid; uint32 dstSubResource; SVGA3dSurfaceId srcSid; uint32 srcSubResource; SVGA3dCopyBox box; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredCopyRegion; +} SVGA3dCmdDXPredCopyRegion; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredStagingCopyRegion { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredStagingCopyRegion { SVGA3dSurfaceId dstSid; uint32 dstSubResource; SVGA3dSurfaceId srcSid; @@ -702,35 +597,29 @@ struct SVGA3dCmdDXPredStagingCopyRegion { uint8 readback; uint8 unsynchronized; uint8 mustBeZero[2]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredStagingCopyRegion; +} SVGA3dCmdDXPredStagingCopyRegion; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredCopy { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredCopy { SVGA3dSurfaceId dstSid; SVGA3dSurfaceId srcSid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredCopy; +} SVGA3dCmdDXPredCopy; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredConvertRegion { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredConvertRegion { SVGA3dSurfaceId dstSid; uint32 dstSubResource; SVGA3dBox destBox; SVGA3dSurfaceId srcSid; uint32 srcSubResource; SVGA3dBox srcBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredConvertRegion; +} SVGA3dCmdDXPredConvertRegion; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredStagingConvertRegion { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredStagingConvertRegion { SVGA3dSurfaceId dstSid; uint32 dstSubResource; SVGA3dBox destBox; @@ -740,46 +629,38 @@ struct SVGA3dCmdDXPredStagingConvertRegion { uint8 readback; uint8 unsynchronized; uint8 mustBeZero[2]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredStagingConvertRegion; +} SVGA3dCmdDXPredStagingConvertRegion; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredConvert { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredConvert { SVGA3dSurfaceId dstSid; SVGA3dSurfaceId srcSid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredConvert; +} SVGA3dCmdDXPredConvert; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredStagingConvert { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredStagingConvert { SVGA3dSurfaceId dstSid; SVGA3dSurfaceId srcSid; uint8 readback; uint8 unsynchronized; uint8 mustBeZero[2]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredStagingConvert; +} SVGA3dCmdDXPredStagingConvert; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBufferCopy { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBufferCopy { SVGA3dSurfaceId dest; SVGA3dSurfaceId src; uint32 destX; uint32 srcX; uint32 width; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBufferCopy; +} SVGA3dCmdDXBufferCopy; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXStagingBufferCopy { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXStagingBufferCopy { SVGA3dSurfaceId dest; SVGA3dSurfaceId src; uint32 destX; @@ -788,33 +669,28 @@ struct SVGA3dCmdDXStagingBufferCopy { uint8 readback; uint8 unsynchronized; uint8 mustBeZero[2]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXStagingBufferCopy; +} SVGA3dCmdDXStagingBufferCopy; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceId dstSid; uint32 dstSubResource; SVGA3dSurfaceId srcSid; uint32 srcSubResource; SVGA3dSurfaceFormat copyFormat; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXResolveCopy; +} SVGA3dCmdDXResolveCopy; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceId dstSid; uint32 dstSubResource; SVGA3dSurfaceId srcSid; uint32 srcSubResource; SVGA3dSurfaceFormat copyFormat; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredResolveCopy; +} SVGA3dCmdDXPredResolveCopy; +#pragma pack(pop) typedef uint32 SVGA3dDXPresentBltMode; #define SVGADX_PRESENTBLT_LINEAR (1 << 0) @@ -822,9 +698,8 @@ typedef uint32 SVGA3dDXPresentBltMode; #define SVGADX_PRESENTBLT_FORCE_SRC_XRBIAS (1 << 2) #define SVGADX_PRESENTBLT_MODE_MAX (1 << 3) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPresentBlt { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPresentBlt { SVGA3dSurfaceId srcSid; uint32 srcSubResource; SVGA3dSurfaceId dstSid; @@ -832,54 +707,39 @@ struct SVGA3dCmdDXPresentBlt { SVGA3dBox boxSrc; SVGA3dBox boxDest; SVGA3dDXPresentBltMode mode; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPresentBlt; +} SVGA3dCmdDXPresentBlt; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXGenMips { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXGenMips { SVGA3dShaderResourceViewId shaderResourceViewId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXGenMips; +} SVGA3dCmdDXGenMips; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXUpdateSubResource { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXUpdateSubResource { SVGA3dSurfaceId sid; uint32 subResource; SVGA3dBox box; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXUpdateSubResource; +} SVGA3dCmdDXUpdateSubResource; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXReadbackSubResource { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXReadbackSubResource { SVGA3dSurfaceId sid; uint32 subResource; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXReadbackSubResource; +} SVGA3dCmdDXReadbackSubResource; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXInvalidateSubResource { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXInvalidateSubResource { SVGA3dSurfaceId sid; uint32 subResource; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXInvalidateSubResource; +} SVGA3dCmdDXInvalidateSubResource; +#pragma pack(pop) - - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXTransferFromBuffer { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXTransferFromBuffer { SVGA3dSurfaceId srcSid; uint32 srcOffset; uint32 srcPitch; @@ -887,19 +747,15 @@ struct SVGA3dCmdDXTransferFromBuffer { SVGA3dSurfaceId destSid; uint32 destSubResource; SVGA3dBox destBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXTransferFromBuffer; - +} SVGA3dCmdDXTransferFromBuffer; +#pragma pack(pop) #define SVGA3D_TRANSFER_TO_BUFFER_READBACK (1 << 0) #define SVGA3D_TRANSFER_TO_BUFFER_FLAGS_MASK (1 << 0) typedef uint32 SVGA3dTransferToBufferFlags; - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXTransferToBuffer { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXTransferToBuffer { SVGA3dSurfaceId srcSid; uint32 srcSubResource; SVGA3dBox srcBox; @@ -908,15 +764,11 @@ struct SVGA3dCmdDXTransferToBuffer { uint32 destPitch; uint32 destSlicePitch; SVGA3dTransferToBufferFlags flags; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXTransferToBuffer; +} SVGA3dCmdDXTransferToBuffer; +#pragma pack(pop) - - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredTransferFromBuffer { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredTransferFromBuffer { SVGA3dSurfaceId srcSid; uint32 srcOffset; uint32 srcPitch; @@ -924,107 +776,81 @@ struct SVGA3dCmdDXPredTransferFromBuffer { SVGA3dSurfaceId destSid; uint32 destSubResource; SVGA3dBox destBox; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredTransferFromBuffer; +} SVGA3dCmdDXPredTransferFromBuffer; +#pragma pack(pop) - - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSurfaceCopyAndReadback { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSurfaceCopyAndReadback { SVGA3dSurfaceId srcSid; SVGA3dSurfaceId destSid; SVGA3dCopyBox box; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSurfaceCopyAndReadback; - - +} SVGA3dCmdDXSurfaceCopyAndReadback; +#pragma pack(pop) typedef uint32 SVGADXHintId; -#define SVGA_DX_HINT_NONE 0 -#define SVGA_DX_HINT_PREFETCH_OBJECT 1 -#define SVGA_DX_HINT_PREEVICT_OBJECT 2 -#define SVGA_DX_HINT_PREFETCH_COBJECT 3 -#define SVGA_DX_HINT_PREEVICT_COBJECT 4 -#define SVGA_DX_HINT_MAX 5 +#define SVGA_DX_HINT_NONE 0 +#define SVGA_DX_HINT_PREFETCH_OBJECT 1 +#define SVGA_DX_HINT_PREEVICT_OBJECT 2 +#define SVGA_DX_HINT_PREFETCH_COBJECT 3 +#define SVGA_DX_HINT_PREEVICT_COBJECT 4 +#define SVGA_DX_HINT_MAX 5 -typedef -#include "vmware_pack_begin.h" -struct SVGAObjectRef { +#pragma pack(push, 1) +typedef struct SVGAObjectRef { SVGAOTableType type; uint32 id; -} -#include "vmware_pack_end.h" -SVGAObjectRef; +} SVGAObjectRef; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGACObjectRef { +#pragma pack(push, 1) +typedef struct SVGACObjectRef { SVGACOTableType type; uint32 cid; uint32 id; -} -#include "vmware_pack_end.h" -SVGACObjectRef; +} SVGACObjectRef; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXHint { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXHint { SVGADXHintId hintId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXHint; +} SVGA3dCmdDXHint; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBufferUpdate { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBufferUpdate { SVGA3dSurfaceId sid; uint32 x; uint32 width; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBufferUpdate; +} SVGA3dCmdDXBufferUpdate; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetConstantBufferOffset { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetConstantBufferOffset { uint32 slot; uint32 offsetInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetConstantBufferOffset; +} SVGA3dCmdDXSetConstantBufferOffset; +#pragma pack(pop) typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetVSConstantBufferOffset; - typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetPSConstantBufferOffset; - typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetGSConstantBufferOffset; - typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetHSConstantBufferOffset; - typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetDSConstantBufferOffset; - typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetCSConstantBufferOffset; - - #define SVGA3D_BUFFEREX_SRV_RAW (1 << 0) #define SVGA3D_BUFFEREX_SRV_FLAGS_MAX (1 << 1) #define SVGA3D_BUFFEREX_SRV_FLAGS_MASK (SVGA3D_BUFFEREX_SRV_FLAGS_MAX - 1) typedef uint32 SVGA3dBufferExFlags; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { union { struct { uint32 firstElement; @@ -1045,25 +871,21 @@ struct { uint32 pad0; } bufferex; }; -} -#include "vmware_pack_end.h" -SVGA3dShaderResourceViewDesc; +} SVGA3dShaderResourceViewDesc; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceId sid; SVGA3dSurfaceFormat format; SVGA3dResourceType resourceDimension; SVGA3dShaderResourceViewDesc desc; uint32 pad; -} -#include "vmware_pack_end.h" -SVGACOTableDXSRViewEntry; +} SVGACOTableDXSRViewEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineShaderResourceView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineShaderResourceView { SVGA3dShaderResourceViewId shaderResourceViewId; SVGA3dSurfaceId sid; @@ -1071,23 +893,17 @@ struct SVGA3dCmdDXDefineShaderResourceView { SVGA3dResourceType resourceDimension; SVGA3dShaderResourceViewDesc desc; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineShaderResourceView; +} SVGA3dCmdDXDefineShaderResourceView; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyShaderResourceView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyShaderResourceView { SVGA3dShaderResourceViewId shaderResourceViewId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyShaderResourceView; +} SVGA3dCmdDXDestroyShaderResourceView; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dRenderTargetViewDesc { +#pragma pack(push, 1) +typedef struct SVGA3dRenderTargetViewDesc { union { struct { uint32 firstElement; @@ -1105,25 +921,21 @@ struct SVGA3dRenderTargetViewDesc { uint32 wSize; } tex3D; }; -} -#include "vmware_pack_end.h" -SVGA3dRenderTargetViewDesc; +} SVGA3dRenderTargetViewDesc; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceId sid; SVGA3dSurfaceFormat format; SVGA3dResourceType resourceDimension; SVGA3dRenderTargetViewDesc desc; uint32 pad[2]; -} -#include "vmware_pack_end.h" -SVGACOTableDXRTViewEntry; +} SVGACOTableDXRTViewEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineRenderTargetView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineRenderTargetView { SVGA3dRenderTargetViewId renderTargetViewId; SVGA3dSurfaceId sid; @@ -1131,29 +943,22 @@ struct SVGA3dCmdDXDefineRenderTargetView { SVGA3dResourceType resourceDimension; SVGA3dRenderTargetViewDesc desc; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineRenderTargetView; +} SVGA3dCmdDXDefineRenderTargetView; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyRenderTargetView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyRenderTargetView { SVGA3dRenderTargetViewId renderTargetViewId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyRenderTargetView; - - +} SVGA3dCmdDXDestroyRenderTargetView; +#pragma pack(pop) #define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_DEPTH 0x01 #define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_STENCIL 0x02 #define SVGA3D_DXDSVIEW_CREATE_FLAG_MASK 0x03 typedef uint8 SVGA3DCreateDSViewFlags; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceId sid; SVGA3dSurfaceFormat format; SVGA3dResourceType resourceDimension; @@ -1164,13 +969,11 @@ struct { uint8 pad0; uint16 pad1; uint32 pad2; -} -#include "vmware_pack_end.h" -SVGACOTableDXDSViewEntry; +} SVGACOTableDXDSViewEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineDepthStencilView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineDepthStencilView { SVGA3dDepthStencilViewId depthStencilViewId; SVGA3dSurfaceId sid; @@ -1182,15 +985,11 @@ struct SVGA3dCmdDXDefineDepthStencilView { SVGA3DCreateDSViewFlags flags; uint8 pad0; uint16 pad1; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineDepthStencilView; +} SVGA3dCmdDXDefineDepthStencilView; +#pragma pack(pop) - - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineDepthStencilView_v2 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineDepthStencilView_v2 { SVGA3dDepthStencilViewId depthStencilViewId; SVGA3dSurfaceId sid; @@ -1202,29 +1001,22 @@ struct SVGA3dCmdDXDefineDepthStencilView_v2 { SVGA3DCreateDSViewFlags flags; uint8 pad0; uint16 pad1; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineDepthStencilView_v2; +} SVGA3dCmdDXDefineDepthStencilView_v2; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyDepthStencilView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyDepthStencilView { SVGA3dDepthStencilViewId depthStencilViewId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyDepthStencilView; - - +} SVGA3dCmdDXDestroyDepthStencilView; +#pragma pack(pop) #define SVGA3D_UABUFFER_RAW (1 << 0) #define SVGA3D_UABUFFER_APPEND (1 << 1) #define SVGA3D_UABUFFER_COUNTER (1 << 2) typedef uint32 SVGA3dUABufferFlags; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { union { struct { uint32 firstElement; @@ -1248,26 +1040,22 @@ struct { uint32 padding1; } tex3D; }; -} -#include "vmware_pack_end.h" -SVGA3dUAViewDesc; +} SVGA3dUAViewDesc; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dSurfaceId sid; SVGA3dSurfaceFormat format; SVGA3dResourceType resourceDimension; SVGA3dUAViewDesc desc; uint32 structureCount; uint32 pad[7]; -} -#include "vmware_pack_end.h" -SVGACOTableDXUAViewEntry; +} SVGACOTableDXUAViewEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineUAView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineUAView { SVGA3dUAViewId uaViewId; SVGA3dSurfaceId sid; @@ -1275,177 +1063,137 @@ struct SVGA3dCmdDXDefineUAView { SVGA3dResourceType resourceDimension; SVGA3dUAViewDesc desc; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineUAView; +} SVGA3dCmdDXDefineUAView; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyUAView { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyUAView { SVGA3dUAViewId uaViewId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyUAView; +} SVGA3dCmdDXDestroyUAView; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXClearUAViewUint { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXClearUAViewUint { SVGA3dUAViewId uaViewId; SVGA3dRGBAUint32 value; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXClearUAViewUint; +} SVGA3dCmdDXClearUAViewUint; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXClearUAViewFloat { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXClearUAViewFloat { SVGA3dUAViewId uaViewId; SVGA3dRGBAFloat value; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXClearUAViewFloat; +} SVGA3dCmdDXClearUAViewFloat; +#pragma pack(pop) - - - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXCopyStructureCount { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXCopyStructureCount { SVGA3dUAViewId srcUAViewId; SVGA3dSurfaceId destSid; uint32 destByteOffset; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXCopyStructureCount; +} SVGA3dCmdDXCopyStructureCount; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetStructureCount { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetStructureCount { SVGA3dUAViewId uaViewId; uint32 structureCount; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetStructureCount; +} SVGA3dCmdDXSetStructureCount; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetUAViews { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetUAViews { uint32 uavSpliceIndex; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetUAViews; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetCSUAViews { +} SVGA3dCmdDXSetUAViews; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetCSUAViews { uint32 startIndex; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetCSUAViews; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dInputElementDesc { +} SVGA3dCmdDXSetCSUAViews; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dInputElementDesc { uint32 inputSlot; uint32 alignedByteOffset; SVGA3dSurfaceFormat format; SVGA3dInputClassification inputSlotClass; uint32 instanceDataStepRate; uint32 inputRegister; -} -#include "vmware_pack_end.h" -SVGA3dInputElementDesc; +} SVGA3dInputElementDesc; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 elid; uint32 numDescs; SVGA3dInputElementDesc descs[32]; uint32 pad[62]; -} -#include "vmware_pack_end.h" -SVGACOTableDXElementLayoutEntry; +} SVGACOTableDXElementLayoutEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineElementLayout { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineElementLayout { SVGA3dElementLayoutId elementLayoutId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineElementLayout; +} SVGA3dCmdDXDefineElementLayout; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyElementLayout { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyElementLayout { SVGA3dElementLayoutId elementLayoutId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyElementLayout; - - +} SVGA3dCmdDXDestroyElementLayout; +#pragma pack(pop) #define SVGA3D_DX_MAX_RENDER_TARGETS 8 -typedef -#include "vmware_pack_begin.h" -struct SVGA3dDXBlendStatePerRT { - uint8 blendEnable; - uint8 srcBlend; - uint8 destBlend; - uint8 blendOp; - uint8 srcBlendAlpha; - uint8 destBlendAlpha; - uint8 blendOpAlpha; - SVGA3dColorWriteEnable renderTargetWriteMask; - uint8 logicOpEnable; - uint8 logicOp; - uint16 pad0; -} -#include "vmware_pack_end.h" -SVGA3dDXBlendStatePerRT; +#pragma pack(push, 1) +typedef struct SVGA3dDXBlendStatePerRT { + uint8 blendEnable; + uint8 srcBlend; + uint8 destBlend; + uint8 blendOp; + uint8 srcBlendAlpha; + uint8 destBlendAlpha; + uint8 blendOpAlpha; + SVGA3dColorWriteEnable renderTargetWriteMask; + uint8 logicOpEnable; + uint8 logicOp; + uint16 pad0; +} SVGA3dDXBlendStatePerRT; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint8 alphaToCoverageEnable; uint8 independentBlendEnable; uint16 pad0; SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS]; uint32 pad1[7]; -} -#include "vmware_pack_end.h" -SVGACOTableDXBlendStateEntry; +} SVGACOTableDXBlendStateEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineBlendState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineBlendState { SVGA3dBlendStateId blendId; uint8 alphaToCoverageEnable; uint8 independentBlendEnable; uint16 pad0; - SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineBlendState; + SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS]; +} SVGA3dCmdDXDefineBlendState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyBlendState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyBlendState { SVGA3dBlendStateId blendId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyBlendState; +} SVGA3dCmdDXDestroyBlendState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint8 depthEnable; SVGA3dDepthWriteMask depthWriteMask; SVGA3dComparisonFunc depthFunc; @@ -1464,13 +1212,11 @@ struct { uint8 backStencilDepthFailOp; uint8 backStencilPassOp; SVGA3dComparisonFunc backStencilFunc; -} -#include "vmware_pack_end.h" -SVGACOTableDXDepthStencilEntry; +} SVGACOTableDXDepthStencilEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineDepthStencilState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineDepthStencilState { SVGA3dDepthStencilStateId depthStencilId; uint8 depthEnable; @@ -1491,23 +1237,17 @@ struct SVGA3dCmdDXDefineDepthStencilState { uint8 backStencilDepthFailOp; uint8 backStencilPassOp; SVGA3dComparisonFunc backStencilFunc; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineDepthStencilState; +} SVGA3dCmdDXDefineDepthStencilState; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyDepthStencilState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyDepthStencilState { SVGA3dDepthStencilStateId depthStencilId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyDepthStencilState; +} SVGA3dCmdDXDestroyDepthStencilState; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint8 fillMode; SVGA3dCullMode cullMode; uint8 frontCounterClockwise; @@ -1525,13 +1265,11 @@ struct { uint16 lineStipplePattern; uint8 forcedSampleCount; uint8 mustBeZero[3]; -} -#include "vmware_pack_end.h" -SVGACOTableDXRasterizerStateEntry; +} SVGACOTableDXRasterizerStateEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineRasterizerState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineRasterizerState { SVGA3dRasterizerStateId rasterizerId; uint8 fillMode; @@ -1549,15 +1287,11 @@ struct SVGA3dCmdDXDefineRasterizerState { uint8 lineStippleEnable; uint8 lineStippleFactor; uint16 lineStipplePattern; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineRasterizerState; +} SVGA3dCmdDXDefineRasterizerState; +#pragma pack(pop) - - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineRasterizerState_v2 { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineRasterizerState_v2 { SVGA3dRasterizerStateId rasterizerId; uint8 fillMode; @@ -1576,23 +1310,17 @@ struct SVGA3dCmdDXDefineRasterizerState_v2 { uint8 lineStippleFactor; uint16 lineStipplePattern; uint32 forcedSampleCount; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineRasterizerState_v2; +} SVGA3dCmdDXDefineRasterizerState_v2; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyRasterizerState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyRasterizerState { SVGA3dRasterizerStateId rasterizerId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyRasterizerState; +} SVGA3dCmdDXDestroyRasterizerState; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { SVGA3dFilter filter; uint8 addressU; uint8 addressV; @@ -1606,14 +1334,11 @@ struct { float minLOD; float maxLOD; uint32 pad2[6]; -} -#include "vmware_pack_end.h" -SVGACOTableDXSamplerEntry; +} SVGACOTableDXSamplerEntry; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineSamplerState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineSamplerState { SVGA3dSamplerId samplerId; SVGA3dFilter filter; uint8 addressU; @@ -1627,157 +1352,135 @@ struct SVGA3dCmdDXDefineSamplerState { SVGA3dRGBAFloat borderColor; float minLOD; float maxLOD; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineSamplerState; +} SVGA3dCmdDXDefineSamplerState; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroySamplerState { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroySamplerState { SVGA3dSamplerId samplerId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroySamplerState; +} SVGA3dCmdDXDestroySamplerState; +#pragma pack(pop) - -#define SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22 -#define SVGADX_SIGNATURE_SEMANTIC_NAME_MAX 23 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22 +#define SVGADX_SIGNATURE_SEMANTIC_NAME_MAX 23 typedef uint32 SVGA3dDXSignatureSemanticName; #define SVGADX_SIGNATURE_REGISTER_COMPONENT_UNKNOWN 0 +#define SVGADX_SIGNATURE_REGISTER_COMPONENT_UINT32 1 +#define SVGADX_SIGNATURE_REGISTER_COMPONENT_INT32 2 +#define SVGADX_SIGNATURE_REGISTER_COMPONENT_FLOAT 3 typedef uint32 SVGA3dDXSignatureRegisterComponentType; #define SVGADX_SIGNATURE_MIN_PRECISION_DEFAULT 0 typedef uint32 SVGA3dDXSignatureMinPrecision; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dDXSignatureEntry { +#pragma pack(push, 1) +typedef struct SVGA3dDXSignatureEntry { uint32 registerIndex; SVGA3dDXSignatureSemanticName semanticName; uint32 mask; SVGA3dDXSignatureRegisterComponentType componentType; SVGA3dDXSignatureMinPrecision minPrecision; -} -#include "vmware_pack_end.h" -SVGA3dDXShaderSignatureEntry; +} SVGA3dDXShaderSignatureEntry; +#pragma pack(pop) #define SVGADX_SIGNATURE_HEADER_VERSION_0 0x08a92d12 - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dDXSignatureHeader { +#pragma pack(push, 1) +typedef struct SVGA3dDXSignatureHeader { uint32 headerVersion; uint32 numInputSignatures; uint32 numOutputSignatures; uint32 numPatchConstantSignatures; -} -#include "vmware_pack_end.h" -SVGA3dDXShaderSignatureHeader; +} SVGA3dDXShaderSignatureHeader; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineShader { SVGA3dShaderId shaderId; SVGA3dShaderType type; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineShader; +} SVGA3dCmdDXDefineShader; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGACOTableDXShaderEntry { +#pragma pack(push, 1) +typedef struct SVGACOTableDXShaderEntry { SVGA3dShaderType type; uint32 sizeInBytes; uint32 offsetInBytes; SVGAMobId mobid; uint32 pad[4]; -} -#include "vmware_pack_end.h" -SVGACOTableDXShaderEntry; +} SVGACOTableDXShaderEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyShader { SVGA3dShaderId shaderId; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyShader; +} SVGA3dCmdDXDestroyShader; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBindShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBindShader { uint32 cid; uint32 shid; SVGAMobId mobid; uint32 offsetInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBindShader; +} SVGA3dCmdDXBindShader; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBindAllShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBindAllShader { uint32 cid; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBindAllShader; +} SVGA3dCmdDXBindAllShader; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXCondBindAllShader { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXCondBindAllShader { uint32 cid; SVGAMobId testMobid; SVGAMobId mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXCondBindAllShader; - +} SVGA3dCmdDXCondBindAllShader; +#pragma pack(pop) #define SVGA3D_MAX_DX10_STREAMOUT_DECLS 64 -#define SVGA3D_MAX_STREAMOUT_DECLS 512 +#define SVGA3D_MAX_STREAMOUT_DECLS 512 -typedef -#include "vmware_pack_begin.h" -struct SVGA3dStreamOutputDeclarationEntry { +#pragma pack(push, 1) +typedef struct SVGA3dStreamOutputDeclarationEntry { uint32 outputSlot; uint32 registerIndex; - uint8 registerMask; - uint8 pad0; + uint8 registerMask; + uint8 pad0; uint16 pad1; uint32 stream; -} -#include "vmware_pack_end.h" -SVGA3dStreamOutputDeclarationEntry; +} SVGA3dStreamOutputDeclarationEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGAOTableStreamOutputEntry { +#pragma pack(push, 1) +typedef struct SVGAOTableStreamOutputEntry { uint32 numOutputStreamEntries; SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS]; uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS]; @@ -1789,184 +1492,146 @@ struct SVGAOTableStreamOutputEntry { uint8 pad0; uint16 pad1; uint32 pad2[246]; -} -#include "vmware_pack_end.h" -SVGACOTableDXStreamOutputEntry; +} SVGACOTableDXStreamOutputEntry; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineStreamOutput { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineStreamOutput { SVGA3dStreamOutputId soid; uint32 numOutputStreamEntries; SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS]; uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS]; uint32 rasterizedStream; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineStreamOutput; - - +} SVGA3dCmdDXDefineStreamOutput; +#pragma pack(pop) #define SVGA3D_DX_SO_NO_RASTERIZED_STREAM 0xFFFFFFFF -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDefineStreamOutputWithMob { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDefineStreamOutputWithMob { SVGA3dStreamOutputId soid; uint32 numOutputStreamEntries; uint32 numOutputStreamStrides; uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS]; uint32 rasterizedStream; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDefineStreamOutputWithMob; +} SVGA3dCmdDXDefineStreamOutputWithMob; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXBindStreamOutput { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXBindStreamOutput { SVGA3dStreamOutputId soid; uint32 mobid; uint32 offsetInBytes; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXBindStreamOutput; +} SVGA3dCmdDXBindStreamOutput; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXDestroyStreamOutput { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXDestroyStreamOutput { SVGA3dStreamOutputId soid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXDestroyStreamOutput; +} SVGA3dCmdDXDestroyStreamOutput; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetStreamOutput { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetStreamOutput { SVGA3dStreamOutputId soid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetStreamOutput; +} SVGA3dCmdDXSetStreamOutput; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetMinLOD { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetMinLOD { SVGA3dSurfaceId sid; float minLOD; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetMinLOD; +} SVGA3dCmdDXSetMinLOD; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint64 value; uint32 mobId; uint32 mobOffset; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXMobFence64; +} SVGA3dCmdDXMobFence64; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXSetCOTable { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXSetCOTable { uint32 cid; uint32 mobid; SVGACOTableType type; uint32 validSizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXSetCOTable; +} SVGA3dCmdDXSetCOTable; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXGrowCOTable { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXGrowCOTable { uint32 cid; uint32 mobid; SVGACOTableType type; uint32 validSizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXGrowCOTable; +} SVGA3dCmdDXGrowCOTable; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXReadbackCOTable { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXReadbackCOTable { uint32 cid; SVGACOTableType type; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXReadbackCOTable; +} SVGA3dCmdDXReadbackCOTable; +#pragma pack(pop) - -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXCopyCOTableIntoMob { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXCopyCOTableIntoMob { uint32 cid; SVGACOTableType type; uint32 mobid; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXCopyCOTableIntoMob; +} SVGA3dCmdDXCopyCOTableIntoMob; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXPredStagingCopy { +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXPredStagingCopy { SVGA3dSurfaceId dstSid; SVGA3dSurfaceId srcSid; uint8 readback; uint8 unsynchronized; uint8 mustBeZero[2]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXPredStagingCopy; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCmdDXStagingCopy { +} SVGA3dCmdDXPredStagingCopy; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCmdDXStagingCopy { SVGA3dSurfaceId dstSid; SVGA3dSurfaceId srcSid; uint8 readback; uint8 unsynchronized; uint8 mustBeZero[2]; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXStagingCopy; -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCOTableData { +} SVGA3dCmdDXStagingCopy; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct SVGA3dCOTableData { uint32 mobid; -} -#include "vmware_pack_end.h" -SVGA3dCOTableData; +} SVGA3dCOTableData; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dBufferBinding { +#pragma pack(push, 1) +typedef struct SVGA3dBufferBinding { uint32 bufferId; uint32 stride; uint32 offset; -} -#include "vmware_pack_end.h" -SVGA3dBufferBinding; +} SVGA3dBufferBinding; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dConstantBufferBinding { +#pragma pack(push, 1) +typedef struct SVGA3dConstantBufferBinding { uint32 sid; uint32 offsetInBytes; uint32 sizeInBytes; -} -#include "vmware_pack_end.h" -SVGA3dConstantBufferBinding; +} SVGA3dConstantBufferBinding; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGADXInputAssemblyMobFormat { +#pragma pack(push, 1) +typedef struct SVGADXInputAssemblyMobFormat { uint32 layoutId; SVGA3dBufferBinding vertexBuffers[SVGA3D_DX_MAX_VERTEXBUFFERS]; uint32 indexBufferSid; @@ -1974,13 +1639,11 @@ struct SVGADXInputAssemblyMobFormat { uint32 indexBufferOffset; uint32 indexBufferFormat; uint32 topology; -} -#include "vmware_pack_end.h" -SVGADXInputAssemblyMobFormat; +} SVGADXInputAssemblyMobFormat; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGADXContextMobFormat { +#pragma pack(push, 1) +typedef struct SVGADXContextMobFormat { SVGADXInputAssemblyMobFormat inputAssembly; struct { @@ -2042,16 +1705,13 @@ struct SVGADXContextMobFormat { uint32 csuaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS]; uint32 pad8[188]; -} -#include "vmware_pack_end.h" -SVGADXContextMobFormat; - +} SVGADXContextMobFormat; +#pragma pack(pop) #define SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED 256 -typedef -#include "vmware_pack_begin.h" -struct SVGADXShaderIfaceMobFormat { +#pragma pack(push, 1) +typedef struct SVGADXShaderIfaceMobFormat { struct { uint32 numClassInstances; uint32 iface[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED]; @@ -2059,23 +1719,20 @@ struct SVGADXShaderIfaceMobFormat { } shaderIfaceState[SVGA3D_NUM_SHADERTYPE]; uint32 pad0[1018]; -} -#include "vmware_pack_end.h" -SVGADXShaderIfaceMobFormat; +} SVGADXShaderIfaceMobFormat; +#pragma pack(pop) -#define SVGA_MOB_FENCE_FLAG_IRQ (1 << 0) -#define SVGA_MOB_FENCE_MASK (SVGA_MOB_FENCE_FLAG_IRQ) +#define SVGA_MOB_FENCE_FLAG_IRQ (1 << 0) +#define SVGA_MOB_FENCE_MASK (SVGA_MOB_FENCE_FLAG_IRQ) typedef uint32 SVGAMobFenceFlags; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint64 value; uint32 mobId; uint32 mobOffset; uint32 flags; -} -#include "vmware_pack_end.h" -SVGA3dCmdDXMobFenceWithFlags; +} SVGA3dCmdDXMobFenceWithFlags; +#pragma pack(pop) #endif diff --git a/src/gallium/drivers/svga/include/svga3d_limits.h b/src/gallium/drivers/svga/include/svga3d_limits.h index f1c1084e642..9cdf8091910 100644 --- a/src/gallium/drivers/svga/include/svga3d_limits.h +++ b/src/gallium/drivers/svga/include/svga3d_limits.h @@ -1,8 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2012-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2012-2021 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* @@ -11,70 +31,50 @@ * SVGA 3d hardware limits */ - - - - #ifndef _SVGA3D_LIMITS_H_ #define _SVGA3D_LIMITS_H_ +#define SVGA3D_HB_MAX_CONTEXT_IDS 256 +#define SVGA3D_HB_MAX_SURFACE_IDS (32 * 1024) - - - - - -#define SVGA3D_NUM_CLIPPLANES 6 -#define SVGA3D_MAX_CONTEXT_IDS 256 -#define SVGA3D_MAX_SURFACE_IDS (32 * 1024) - - -#define SVGA3D_MAX_RENDER_TARGETS 8 -#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS) -#define SVGA3D_MAX_UAVIEWS 8 -#define SVGA3D_DX11_1_MAX_UAVIEWS 64 - +#define SVGA3D_DX_MAX_RENDER_TARGETS 8 +#define SVGA3D_DX11_MAX_UAVIEWS 8 +#define SVGA3D_DX11_1_MAX_UAVIEWS 64 +#define SVGA3D_MAX_UAVIEWS (SVGA3D_DX11_1_MAX_UAVIEWS) +#define SVGA3D_DX11_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_MAX_UAVIEWS) +#define SVGA3D_DX11_1_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_1_MAX_UAVIEWS) +#define SVGA3D_MAX_SIMULTANEOUS_RTUAV (SVGA3D_MAX_UAVIEWS) #define SVGA3D_HB_MAX_SURFACE_SIZE MBYTES_2_BYTES(128) +#define SVGA3D_MAX_SHADERIDS 5000 -#define SVGA3D_MAX_SHADERIDS 5000 +#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000 -#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000 - -#define SVGA3D_NUM_TEXTURE_UNITS 32 -#define SVGA3D_NUM_LIGHTS 8 - - -#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32 +#define SVGA3D_NUM_TEXTURE_UNITS 32 +#define SVGA3D_NUM_LIGHTS 8 +#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32 #define SVGA3D_MAX_SHADER_MEMORY_BYTES (8 * 1024 * 1024) -#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \ - sizeof(uint32)) +#define SVGA3D_MAX_SHADER_MEMORY \ + (SVGA3D_MAX_SHADER_MEMORY_BYTES / sizeof(uint32)) #define SVGA3D_MAX_SHADER_THREAD_GROUPS 65535 -#define SVGA3D_MAX_CLIP_PLANES 6 - +#define SVGA3D_MAX_CLIP_PLANES 6 #define SVGA3D_MAX_TEXTURE_COORDS 8 - #define SVGA3D_MAX_SURFACE_FACES 6 - #define SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE 512 #define SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE 2048 -#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE - - -#define SVGA3D_MAX_VERTEX_ARRAYS 32 +#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE +#define SVGA3D_MAX_VERTEX_ARRAYS 32 #define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32 - #define SVGA3D_MAX_SAMPLES 8 - #endif diff --git a/src/gallium/drivers/svga/include/svga3d_reg.h b/src/gallium/drivers/svga/include/svga3d_reg.h index bbac25a8249..655789fe32c 100644 --- a/src/gallium/drivers/svga/include/svga3d_reg.h +++ b/src/gallium/drivers/svga/include/svga3d_reg.h @@ -1,32 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 1998-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 1998-2015 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* * svga3d_reg.h -- * - * SVGA 3d hardware definitions + * SVGA 3d hardware definitions */ #ifndef _SVGA3D_REG_H_ #define _SVGA3D_REG_H_ -#define INCLUDE_ALLOW_MODULE -#define INCLUDE_ALLOW_USERLEVEL -#define INCLUDE_ALLOW_VMCORE - -#include "includeCheck.h" - #include "svga_reg.h" -#include "svga3d_types.h" -#include "svga3d_limits.h" #include "svga3d_cmd.h" -#include "svga3d_dx.h" #include "svga3d_devcaps.h" +#include "svga3d_dx.h" +#include "svga3d_limits.h" +#include "svga3d_types.h" - -#endif /* _SVGA3D_REG_H_ */ +#endif diff --git a/src/gallium/drivers/svga/include/svga3d_shaderdefs.h b/src/gallium/drivers/svga/include/svga3d_shaderdefs.h index 206460634bd..c5f2327256a 100644 --- a/src/gallium/drivers/svga/include/svga3d_shaderdefs.h +++ b/src/gallium/drivers/svga/include/svga3d_shaderdefs.h @@ -1,78 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2007-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2007-2020 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* * svga3d_shaderdefs.h -- * - * SVGA3D byte code format and limit definitions. - * - * The format of the byte code directly corresponds to that defined - * by Microsoft DirectX SDK 9.0c (file d3d9types.h). The format can - * also be extended so that different shader formats can be supported - * for example GLSL, ARB vp/fp, NV/ATI shader formats, etc. - * + * SVGA3D byte code format and limit definitions. */ #ifndef __SVGA3D_SHADER_DEFS__ #define __SVGA3D_SHADER_DEFS__ -/* SVGA3D shader hardware limits. */ +#include "svga3d_types.h" -#define SVGA3D_INPUTREG_MAX 16 -#define SVGA3D_OUTPUTREG_MAX 12 -#define SVGA3D_VERTEX_SAMPLERREG_MAX 4 -#define SVGA3D_PIXEL_SAMPLERREG_MAX 16 -#define SVGA3D_SAMPLERREG_MAX (SVGA3D_PIXEL_SAMPLERREG_MAX+\ - SVGA3D_VERTEX_SAMPLERREG_MAX) -#define SVGA3D_TEMPREG_MAX 32 -#define SVGA3D_CONSTREG_MAX 256 -#define SVGA3D_CONSTINTREG_MAX 16 -#define SVGA3D_CONSTBOOLREG_MAX 16 -#define SVGA3D_ADDRREG_MAX 1 -#define SVGA3D_PREDREG_MAX 1 +#if defined __cplusplus +extern "C" { +#endif -/* SVGA3D byte code specific limits */ +#define SVGA3D_INPUTREG_MAX 16 +#define SVGA3D_OUTPUTREG_MAX 12 +#define SVGA3D_VERTEX_SAMPLERREG_MAX 4 +#define SVGA3D_PIXEL_SAMPLERREG_MAX 16 +#define SVGA3D_SAMPLERREG_MAX \ + (SVGA3D_PIXEL_SAMPLERREG_MAX + SVGA3D_VERTEX_SAMPLERREG_MAX) +#define SVGA3D_TEMPREG_MAX 32 +#define SVGA3D_ADDRREG_MAX 1 +#define SVGA3D_PREDREG_MAX 1 #define SVGA3D_MAX_SRC_REGS 4 #define SVGA3D_MAX_NESTING_LEVEL 32 -/* SVGA3D version information. */ - -#define SVGA3D_VS_TYPE 0xFFFE -#define SVGA3D_PS_TYPE 0xFFFF +#define SVGA3D_VS_TYPE 0xFFFE +#define SVGA3D_PS_TYPE 0xFFFF typedef struct { union { struct { uint32 minor : 8; uint32 major : 8; - uint32 type : 16; + uint32 type : 16; }; uint32 value; }; } SVGA3dShaderVersion; -#define SVGA3D_VS_10 ((SVGA3D_VS_TYPE << 16) | 1 << 8) -#define SVGA3D_VS_11 (SVGA3D_VS_10 | 1) -#define SVGA3D_VS_20 ((SVGA3D_VS_TYPE << 16) | 2 << 8) -#define SVGA3D_VS_21 (SVGA3D_VS_20 | 1) -#define SVGA3D_VS_30 ((SVGA3D_VS_TYPE << 16) | 3 << 8) +#define SVGA3D_VS_10 ((uint32)((SVGA3D_VS_TYPE << 16) | 1 << 8)) +#define SVGA3D_VS_11 ((uint32)(SVGA3D_VS_10 | 1)) +#define SVGA3D_VS_20 ((uint32)((SVGA3D_VS_TYPE << 16) | 2 << 8)) +#define SVGA3D_VS_21 ((uint32)(SVGA3D_VS_20 | 1)) +#define SVGA3D_VS_30 ((uint32)((SVGA3D_VS_TYPE << 16) | 3 << 8)) -#define SVGA3D_PS_10 ((SVGA3D_PS_TYPE << 16) | 1 << 8) -#define SVGA3D_PS_11 (SVGA3D_PS_10 | 1) -#define SVGA3D_PS_12 (SVGA3D_PS_10 | 2) -#define SVGA3D_PS_13 (SVGA3D_PS_10 | 3) -#define SVGA3D_PS_14 (SVGA3D_PS_10 | 4) -#define SVGA3D_PS_20 ((SVGA3D_PS_TYPE << 16) | 2 << 8) -#define SVGA3D_PS_21 (SVGA3D_PS_20 | 1) -#define SVGA3D_PS_30 ((SVGA3D_PS_TYPE << 16) | 3 << 8) +#define SVGA3D_PS_10 ((uint32)((SVGA3D_PS_TYPE << 16) | 1 << 8)) +#define SVGA3D_PS_11 ((uint32)(SVGA3D_PS_10 | 1)) +#define SVGA3D_PS_12 ((uint32)(SVGA3D_PS_10 | 2)) +#define SVGA3D_PS_13 ((uint32)(SVGA3D_PS_10 | 3)) +#define SVGA3D_PS_14 ((uint32)(SVGA3D_PS_10 | 4)) +#define SVGA3D_PS_20 ((uint32)((SVGA3D_PS_TYPE << 16) | 2 << 8)) +#define SVGA3D_PS_21 ((uint32)(SVGA3D_PS_20 | 1)) +#define SVGA3D_PS_30 ((uint32)((SVGA3D_PS_TYPE << 16) | 3 << 8)) -/* The *_ENABLED are for backwards compatibility with old drivers */ typedef enum { SVGA3DPSVERSION_NONE = 0, SVGA3DPSVERSION_ENABLED = 1, @@ -96,90 +106,89 @@ typedef enum { SVGA3DVSVERSION_MAX } SVGA3dVertexShaderVersion; -/* SVGA3D instruction op codes. */ - typedef enum { SVGA3DOP_NOP = 0, - SVGA3DOP_MOV, - SVGA3DOP_ADD, - SVGA3DOP_SUB, - SVGA3DOP_MAD, - SVGA3DOP_MUL, - SVGA3DOP_RCP, - SVGA3DOP_RSQ, - SVGA3DOP_DP3, - SVGA3DOP_DP4, - SVGA3DOP_MIN, - SVGA3DOP_MAX, - SVGA3DOP_SLT, - SVGA3DOP_SGE, - SVGA3DOP_EXP, - SVGA3DOP_LOG, - SVGA3DOP_LIT, - SVGA3DOP_DST, - SVGA3DOP_LRP, - SVGA3DOP_FRC, - SVGA3DOP_M4x4, - SVGA3DOP_M4x3, - SVGA3DOP_M3x4, - SVGA3DOP_M3x3, - SVGA3DOP_M3x2, - SVGA3DOP_CALL, - SVGA3DOP_CALLNZ, - SVGA3DOP_LOOP, - SVGA3DOP_RET, - SVGA3DOP_ENDLOOP, - SVGA3DOP_LABEL, - SVGA3DOP_DCL, - SVGA3DOP_POW, - SVGA3DOP_CRS, - SVGA3DOP_SGN, - SVGA3DOP_ABS, - SVGA3DOP_NRM, - SVGA3DOP_SINCOS, - SVGA3DOP_REP, - SVGA3DOP_ENDREP, - SVGA3DOP_IF, - SVGA3DOP_IFC, - SVGA3DOP_ELSE, - SVGA3DOP_ENDIF, - SVGA3DOP_BREAK, - SVGA3DOP_BREAKC, - SVGA3DOP_MOVA, - SVGA3DOP_DEFB, - SVGA3DOP_DEFI, + SVGA3DOP_MOV = 1, + SVGA3DOP_ADD = 2, + SVGA3DOP_SUB = 3, + SVGA3DOP_MAD = 4, + SVGA3DOP_MUL = 5, + SVGA3DOP_RCP = 6, + SVGA3DOP_RSQ = 7, + SVGA3DOP_DP3 = 8, + SVGA3DOP_DP4 = 9, + SVGA3DOP_MIN = 10, + SVGA3DOP_MAX = 11, + SVGA3DOP_SLT = 12, + SVGA3DOP_SGE = 13, + SVGA3DOP_EXP = 14, + SVGA3DOP_LOG = 15, + SVGA3DOP_LIT = 16, + SVGA3DOP_DST = 17, + SVGA3DOP_LRP = 18, + SVGA3DOP_FRC = 19, + SVGA3DOP_M4x4 = 20, + SVGA3DOP_M4x3 = 21, + SVGA3DOP_M3x4 = 22, + SVGA3DOP_M3x3 = 23, + SVGA3DOP_M3x2 = 24, + SVGA3DOP_CALL = 25, + SVGA3DOP_CALLNZ = 26, + SVGA3DOP_LOOP = 27, + SVGA3DOP_RET = 28, + SVGA3DOP_ENDLOOP = 29, + SVGA3DOP_LABEL = 30, + SVGA3DOP_DCL = 31, + SVGA3DOP_POW = 32, + SVGA3DOP_CRS = 33, + SVGA3DOP_SGN = 34, + SVGA3DOP_ABS = 35, + SVGA3DOP_NRM = 36, + SVGA3DOP_SINCOS = 37, + SVGA3DOP_REP = 38, + SVGA3DOP_ENDREP = 39, + SVGA3DOP_IF = 40, + SVGA3DOP_IFC = 41, + SVGA3DOP_ELSE = 42, + SVGA3DOP_ENDIF = 43, + SVGA3DOP_BREAK = 44, + SVGA3DOP_BREAKC = 45, + SVGA3DOP_MOVA = 46, + SVGA3DOP_DEFB = 47, + SVGA3DOP_DEFI = 48, + SVGA3DOP_TEXCOORD = 64, - SVGA3DOP_TEXKILL, - SVGA3DOP_TEX, - SVGA3DOP_TEXBEM, - SVGA3DOP_TEXBEML, - SVGA3DOP_TEXREG2AR, + SVGA3DOP_TEXKILL = 65, + SVGA3DOP_TEX = 66, + SVGA3DOP_TEXBEM = 67, + SVGA3DOP_TEXBEML = 68, + SVGA3DOP_TEXREG2AR = 69, SVGA3DOP_TEXREG2GB = 70, - SVGA3DOP_TEXM3x2PAD, - SVGA3DOP_TEXM3x2TEX, - SVGA3DOP_TEXM3x3PAD, - SVGA3DOP_TEXM3x3TEX, - SVGA3DOP_RESERVED0, - SVGA3DOP_TEXM3x3SPEC, - SVGA3DOP_TEXM3x3VSPEC, - SVGA3DOP_EXPP, - SVGA3DOP_LOGP, + SVGA3DOP_TEXM3x2PAD = 71, + SVGA3DOP_TEXM3x2TEX = 72, + SVGA3DOP_TEXM3x3PAD = 73, + SVGA3DOP_TEXM3x3TEX = 74, + SVGA3DOP_RESERVED0 = 75, + SVGA3DOP_TEXM3x3SPEC = 76, + SVGA3DOP_TEXM3x3VSPEC = 77, + SVGA3DOP_EXPP = 78, + SVGA3DOP_LOGP = 79, SVGA3DOP_CND = 80, - SVGA3DOP_DEF, - SVGA3DOP_TEXREG2RGB, - SVGA3DOP_TEXDP3TEX, - SVGA3DOP_TEXM3x2DEPTH, - SVGA3DOP_TEXDP3, - SVGA3DOP_TEXM3x3, - SVGA3DOP_TEXDEPTH, - SVGA3DOP_CMP, - SVGA3DOP_BEM, + SVGA3DOP_DEF = 81, + SVGA3DOP_TEXREG2RGB = 82, + SVGA3DOP_TEXDP3TEX = 83, + SVGA3DOP_TEXM3x2DEPTH = 84, + SVGA3DOP_TEXDP3 = 85, + SVGA3DOP_TEXM3x3 = 86, + SVGA3DOP_TEXDEPTH = 87, + SVGA3DOP_CMP = 88, + SVGA3DOP_BEM = 89, SVGA3DOP_DP2ADD = 90, - SVGA3DOP_DSX, - SVGA3DOP_DSY, - SVGA3DOP_TEXLDD, - SVGA3DOP_SETP, - SVGA3DOP_TEXLDL, + SVGA3DOP_DSX = 91, + SVGA3DOP_DSY = 92, + SVGA3DOP_TEXLDD = 93, + SVGA3DOP_SETP = 94, + SVGA3DOP_TEXLDL = 95, SVGA3DOP_BREAKP = 96, SVGA3DOP_LAST_INST, SVGA3DOP_PHASE = 0xFFFD, @@ -187,12 +196,10 @@ typedef enum { SVGA3DOP_END = 0xFFFF, } SVGA3dShaderOpCodeType; -/* SVGA3D operation control/comparison function types */ - typedef enum { SVGA3DOPCONT_NONE, - SVGA3DOPCONT_PROJECT, /* Projective texturing */ - SVGA3DOPCONT_BIAS, /* Texturing with a LOD bias */ + SVGA3DOPCONT_PROJECT, + SVGA3DOPCONT_BIAS, } SVGA3dShaderOpCodeControlFnType; typedef enum { @@ -201,103 +208,78 @@ typedef enum { SVGA3DOPCOMP_EQ, SVGA3DOPCOMP_GE, SVGA3DOPCOMP_LT, - SVGA3DOPCOMPC_NE, + SVGA3DOPCOMP_NE, SVGA3DOPCOMP_LE, SVGA3DOPCOMP_RESERVED1 } SVGA3dShaderOpCodeCompFnType; -/* SVGA3D register types */ - typedef enum { - SVGA3DREG_TEMP = 0, /* Temporary register file */ - SVGA3DREG_INPUT, /* Input register file */ - SVGA3DREG_CONST, /* Constant register file */ - SVGA3DREG_ADDR, /* Address register for VS */ - SVGA3DREG_TEXTURE = 3, /* Texture register file for PS */ - SVGA3DREG_RASTOUT, /* Rasterizer register file */ - SVGA3DREG_ATTROUT, /* Attribute output register file */ - SVGA3DREG_TEXCRDOUT, /* Texture coordinate output register file */ - SVGA3DREG_OUTPUT = 6, /* Output register file for VS 3.0+ */ - SVGA3DREG_CONSTINT, /* Constant integer vector register file */ - SVGA3DREG_COLOROUT, /* Color output register file */ - SVGA3DREG_DEPTHOUT, /* Depth output register file */ - SVGA3DREG_SAMPLER, /* Sampler state register file */ - SVGA3DREG_CONST2, /* Constant register file 2048 - 4095 */ - SVGA3DREG_CONST3, /* Constant register file 4096 - 6143 */ - SVGA3DREG_CONST4, /* Constant register file 6144 - 8191 */ - SVGA3DREG_CONSTBOOL, /* Constant boolean register file */ - SVGA3DREG_LOOP, /* Loop counter register file */ - SVGA3DREG_TEMPFLOAT16, /* 16-bit float temp register file */ - SVGA3DREG_MISCTYPE, /* Miscellaneous (single) registers */ - SVGA3DREG_LABEL, /* Label */ - SVGA3DREG_PREDICATE, /* Predicate register */ + SVGA3DREG_TEMP = 0, + SVGA3DREG_INPUT, + SVGA3DREG_CONST, + SVGA3DREG_ADDR, + SVGA3DREG_TEXTURE = 3, + SVGA3DREG_RASTOUT, + SVGA3DREG_ATTROUT, + SVGA3DREG_TEXCRDOUT, + SVGA3DREG_OUTPUT = 6, + SVGA3DREG_CONSTINT, + SVGA3DREG_COLOROUT, + SVGA3DREG_DEPTHOUT, + SVGA3DREG_SAMPLER, + SVGA3DREG_CONST2, + SVGA3DREG_CONST3, + SVGA3DREG_CONST4, + SVGA3DREG_CONSTBOOL, + SVGA3DREG_LOOP, + SVGA3DREG_TEMPFLOAT16, + SVGA3DREG_MISCTYPE, + SVGA3DREG_LABEL, + SVGA3DREG_PREDICATE, } SVGA3dShaderRegType; -/* SVGA3D rasterizer output register types */ - typedef enum { SVGA3DRASTOUT_POSITION = 0, SVGA3DRASTOUT_FOG, SVGA3DRASTOUT_PSIZE } SVGA3dShaderRastOutRegType; -/* SVGA3D miscellaneous register types */ - typedef enum { - SVGA3DMISCREG_POSITION = 0, /* Input position x,y,z,rhw (PS) */ - SVGA3DMISCREG_FACE /* Floating point primitive area (PS) */ + SVGA3DMISCREG_POSITION = 0, + SVGA3DMISCREG_FACE } SVGA3DShaderMiscRegType; -/* SVGA3D sampler types */ - typedef enum { - SVGA3DSAMP_UNKNOWN = 0, /* Uninitialized value */ - SVGA3DSAMP_2D = 2, /* dcl_2d s# (for declaring a 2D texture) */ - SVGA3DSAMP_CUBE, /* dcl_cube s# (for declaring a cube texture) */ - SVGA3DSAMP_VOLUME, /* dcl_volume s# (for declaring a volume texture) */ - SVGA3DSAMP_2D_SHADOW, /* dcl_2d s# (for declaring a 2D shadow texture) */ + SVGA3DSAMP_UNKNOWN = 0, + SVGA3DSAMP_2D = 2, + SVGA3DSAMP_CUBE, + SVGA3DSAMP_VOLUME, + SVGA3DSAMP_2D_SHADOW, SVGA3DSAMP_MAX, } SVGA3dShaderSamplerType; -/* SVGA3D write mask */ +#define SVGA3DWRITEMASK_0 1 +#define SVGA3DWRITEMASK_1 2 +#define SVGA3DWRITEMASK_2 4 +#define SVGA3DWRITEMASK_3 8 +#define SVGA3DWRITEMASK_ALL 15 -#define SVGA3DWRITEMASK_0 1 /* Component 0 (X;Red) */ -#define SVGA3DWRITEMASK_1 2 /* Component 1 (Y;Green) */ -#define SVGA3DWRITEMASK_2 4 /* Component 2 (Z;Blue) */ -#define SVGA3DWRITEMASK_3 8 /* Component 3 (W;Alpha) */ -#define SVGA3DWRITEMASK_ALL 15 /* All components */ +#define SVGA3DDSTMOD_NONE 0 +#define SVGA3DDSTMOD_SATURATE 1 +#define SVGA3DDSTMOD_PARTIALPRECISION 2 -/* SVGA3D destination modifiers */ - -#define SVGA3DDSTMOD_NONE 0 /* nop */ -#define SVGA3DDSTMOD_SATURATE 1 /* clamp to [0, 1] */ -#define SVGA3DDSTMOD_PARTIALPRECISION 2 /* Partial precision hint */ - -/* - * Relevant to multisampling only: - * When the pixel center is not covered, sample - * attribute or compute gradients/LOD - * using multisample "centroid" location. - * "Centroid" is some location within the covered - * region of the pixel. - */ - -#define SVGA3DDSTMOD_MSAMPCENTROID 4 - -/* SVGA3D destination shift scale */ +#define SVGA3DDSTMOD_MSAMPCENTROID 4 typedef enum { - SVGA3DDSTSHFSCALE_X1 = 0, /* 1.0 */ - SVGA3DDSTSHFSCALE_X2 = 1, /* 2.0 */ - SVGA3DDSTSHFSCALE_X4 = 2, /* 4.0 */ - SVGA3DDSTSHFSCALE_X8 = 3, /* 8.0 */ - SVGA3DDSTSHFSCALE_D8 = 13, /* 0.125 */ - SVGA3DDSTSHFSCALE_D4 = 14, /* 0.25 */ - SVGA3DDSTSHFSCALE_D2 = 15 /* 0.5 */ + SVGA3DDSTSHFSCALE_X1 = 0, + SVGA3DDSTSHFSCALE_X2 = 1, + SVGA3DDSTSHFSCALE_X4 = 2, + SVGA3DDSTSHFSCALE_X8 = 3, + SVGA3DDSTSHFSCALE_D8 = 13, + SVGA3DDSTSHFSCALE_D4 = 14, + SVGA3DDSTSHFSCALE_D2 = 15 } SVGA3dShaderDstShfScaleType; -/* SVGA3D source swizzle */ - #define SVGA3DSWIZZLE_REPLICATEX 0x00 #define SVGA3DSWIZZLE_REPLICATEY 0x55 #define SVGA3DSWIZZLE_REPLICATEZ 0xAA @@ -307,106 +289,96 @@ typedef enum { #define SVGA3DSWIZZLE_ZXYW 0xD2 #define SVGA3DSWIZZLE_WXYZ 0x1B -/* SVGA3D source modifiers */ - typedef enum { - SVGA3DSRCMOD_NONE = 0, /* nop */ - SVGA3DSRCMOD_NEG, /* negate */ - SVGA3DSRCMOD_BIAS, /* bias */ - SVGA3DSRCMOD_BIASNEG, /* bias and negate */ - SVGA3DSRCMOD_SIGN, /* sign */ - SVGA3DSRCMOD_SIGNNEG, /* sign and negate */ - SVGA3DSRCMOD_COMP, /* complement */ - SVGA3DSRCMOD_X2, /* x2 */ - SVGA3DSRCMOD_X2NEG, /* x2 and negate */ - SVGA3DSRCMOD_DZ, /* divide through by z component */ - SVGA3DSRCMOD_DW, /* divide through by w component */ - SVGA3DSRCMOD_ABS, /* abs() */ - SVGA3DSRCMOD_ABSNEG, /* -abs() */ - SVGA3DSRCMOD_NOT, /* ! (for predicate register) */ + SVGA3DSRCMOD_NONE = 0, + SVGA3DSRCMOD_NEG, + SVGA3DSRCMOD_BIAS, + SVGA3DSRCMOD_BIASNEG, + SVGA3DSRCMOD_SIGN, + SVGA3DSRCMOD_SIGNNEG, + SVGA3DSRCMOD_COMP, + SVGA3DSRCMOD_X2, + SVGA3DSRCMOD_X2NEG, + SVGA3DSRCMOD_DZ, + SVGA3DSRCMOD_DW, + SVGA3DSRCMOD_ABS, + SVGA3DSRCMOD_ABSNEG, + SVGA3DSRCMOD_NOT, } SVGA3dShaderSrcModType; -/* SVGA3D instruction token */ - typedef struct { union { struct { - uint32 comment_op : 16; + uint32 comment_op : 16; uint32 comment_size : 16; }; struct { - uint32 op : 16; - uint32 control : 3; - uint32 reserved2 : 5; - uint32 size : 4; + uint32 op : 16; + uint32 control : 3; + uint32 reserved2 : 5; + uint32 size : 4; uint32 predicated : 1; - uint32 reserved1 : 1; - uint32 coissue : 1; - uint32 reserved0 : 1; + uint32 reserved1 : 1; + uint32 coissue : 1; + uint32 reserved0 : 1; }; uint32 value; }; } SVGA3dShaderInstToken; -/* SVGA3D destination parameter token */ - typedef struct { union { struct { - uint32 num : 11; + uint32 num : 11; uint32 type_upper : 2; - uint32 relAddr : 1; - uint32 reserved1 : 2; - uint32 mask : 4; - uint32 dstMod : 4; - uint32 shfScale : 4; + uint32 relAddr : 1; + uint32 reserved1 : 2; + uint32 mask : 4; + uint32 dstMod : 4; + uint32 shfScale : 4; uint32 type_lower : 3; - uint32 reserved0 : 1; + uint32 reserved0 : 1; }; uint32 value; }; } SVGA3dShaderDestToken; -/* SVGA3D source parameter token */ - typedef struct { union { struct { - uint32 num : 11; + uint32 num : 11; uint32 type_upper : 2; - uint32 relAddr : 1; - uint32 reserved1 : 2; - uint32 swizzle : 8; - uint32 srcMod : 4; + uint32 relAddr : 1; + uint32 reserved1 : 2; + uint32 swizzle : 8; + uint32 srcMod : 4; uint32 type_lower : 3; - uint32 reserved0 : 1; + uint32 reserved0 : 1; }; uint32 value; }; } SVGA3dShaderSrcToken; -/* SVGA3DOP_DCL parameter tokens */ - typedef struct { union { struct { union { struct { - uint32 usage : 5; + uint32 usage : 5; uint32 reserved1 : 11; - uint32 index : 4; + uint32 index : 4; uint32 reserved0 : 12; - }; /* input / output declaration */ + }; struct { uint32 reserved3 : 27; - uint32 type : 4; + uint32 type : 4; uint32 reserved2 : 1; - }; /* sampler declaration */ + }; }; SVGA3dShaderDestToken dst; @@ -416,8 +388,6 @@ typedef struct { }; } SVGA3DOpDclArgs; -/* SVGA3DOP_DEF parameter tokens */ - typedef struct { union { struct { @@ -434,8 +404,6 @@ typedef struct { }; } SVGA3DOpDefArgs; -/* SVGA3D shader token */ - typedef union { uint32 value; SVGA3dShaderInstToken inst; @@ -443,14 +411,10 @@ typedef union { SVGA3dShaderSrcToken src; } SVGA3dShaderToken; -/* SVGA3D shader program */ - typedef struct { SVGA3dShaderVersion version; - /* SVGA3dShaderToken stream */ -} SVGA3dShaderProgram; -/* SVGA3D version specific register assignments */ +} SVGA3dShaderProgram; static const uint32 SVGA3D_INPUT_REG_POSITION_VS11 = 0; static const uint32 SVGA3D_INPUT_REG_PSIZE_VS11 = 1; @@ -473,23 +437,7 @@ static const uint32 SVGA3D_OUTPUT_REG_COLOR_NUM_PS20 = 4; static const uint32 SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20 = 0; static const uint32 SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20 = 1; -/* - *---------------------------------------------------------------------- - * - * SVGA3dShaderGetRegType -- - * - * As the register type is split into two non sequential fields, - * this function provides an useful way of accessing the actual - * register type without having to manually concatenate the - * type_upper and type_lower fields. - * - * Results: - * Returns the register type. - * - *---------------------------------------------------------------------- - */ - -static inline SVGA3dShaderRegType +static INLINE SVGA3dShaderRegType SVGA3dShaderGetRegType(uint32 token) { SVGA3dShaderSrcToken src; @@ -497,4 +445,8 @@ SVGA3dShaderGetRegType(uint32 token) return (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower); } -#endif /* __SVGA3D_SHADER_DEFS__ */ +#if defined __cplusplus +} +#endif + +#endif diff --git a/src/gallium/drivers/svga/include/svga3d_surfacedefs.h b/src/gallium/drivers/svga/include/svga3d_surfacedefs.h index 84d00564100..cd3e65d414d 100644 --- a/src/gallium/drivers/svga/include/svga3d_surfacedefs.h +++ b/src/gallium/drivers/svga/include/svga3d_surfacedefs.h @@ -1,1362 +1,1328 @@ -/* - * Copyright (c) 1998-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT - */ - -/* - * svga3d_surfacedefs.h -- +// SPDX-License-Identifier: GPL-2.0 OR MIT +/************************************************************************** * - * Surface/format/image helper code. - */ - -#ifndef SVGA3D_SURFACEDEFS_H -#define SVGA3D_SURFACEDEFS_H - -#include "svga_types.h" -#include "svga3d_reg.h" - -#define max_t(type, x, y) ((x) > (y) ? (x) : (y)) - -/* - * enum svga3d_block_desc describes the active data channels in a block. + * Copyright (c) 2009-2024 Broadcom. All Rights Reserved. The term + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * - * There can be at-most four active channels in a block: - * 1. Red, bump W, luminance and depth are stored in the first channel. - * 2. Green, bump V and stencil are stored in the second channel. - * 3. Blue and bump U are stored in the third channel. - * 4. Alpha and bump Q are stored in the fourth channel. - * - * Block channels can be used to store compressed and buffer data: - * 1. For compressed formats, only the data channel is used and its size - * is equal to that of a singular block in the compression scheme. - * 2. For buffer formats, only the data channel is used and its size is - * exactly one byte in length. - * 3. In each case the bit depth represent the size of a singular block. - * - * Note: Compressed and IEEE formats do not use the bitMask structure. - */ + **************************************************************************/ -enum svga3d_block_desc { +#ifndef _SVGA3D_SURFACEDEFS_H_ +#define _SVGA3D_SURFACEDEFS_H_ - SVGA3DBLOCKDESC_NONE = 0, /* No channels are active */ - SVGA3DBLOCKDESC_BLUE = 1 << 0, /* Block with red channel data */ - SVGA3DBLOCKDESC_W = 1 << 0, - SVGA3DBLOCKDESC_BUMP_L = 1 << 0, +#include +#include "svga3d_types.h" - /* Format contains Green/V data */ - SVGA3DBLOCKDESC_GREEN = 1 << 1, - SVGA3DBLOCKDESC_V = 1 << 1, +#ifdef __cplusplus +extern "C" { +#endif - /* Format contains Red/W/Luminance data */ - SVGA3DBLOCKDESC_RED = 1 << 2, - SVGA3DBLOCKDESC_U = 1 << 2, - SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, - - SVGA3DBLOCKDESC_ALPHA = 1 << 3, /* Block with an alpha channel */ - SVGA3DBLOCKDESC_Q = 1 << 3, /* Block with bump Q channel data */ - SVGA3DBLOCKDESC_BUFFER = 1 << 4, /* Block stores 1 byte of data */ - SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, /* Block stores n bytes of data depending - on the compression method used */ - SVGA3DBLOCKDESC_FP = 1 << 6, - - SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7, +typedef enum SVGA3dBlockDesc { + SVGA3DBLOCKDESC_NONE = 0, + SVGA3DBLOCKDESC_BLUE = 1 << 0, + SVGA3DBLOCKDESC_W = 1 << 0, + SVGA3DBLOCKDESC_BUMP_L = 1 << 0, + SVGA3DBLOCKDESC_GREEN = 1 << 1, + SVGA3DBLOCKDESC_V = 1 << 1, + SVGA3DBLOCKDESC_RED = 1 << 2, + SVGA3DBLOCKDESC_U = 1 << 2, + SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, + SVGA3DBLOCKDESC_ALPHA = 1 << 3, + SVGA3DBLOCKDESC_Q = 1 << 3, + SVGA3DBLOCKDESC_BUFFER = 1 << 4, + SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, + SVGA3DBLOCKDESC_FP = 1 << 6, + SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7, SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8, SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9, - SVGA3DBLOCKDESC_STENCIL = 1 << 11, - SVGA3DBLOCKDESC_TYPELESS = 1 << 12, - SVGA3DBLOCKDESC_SINT = 1 << 13, - SVGA3DBLOCKDESC_UINT = 1 << 14, - SVGA3DBLOCKDESC_NORM = 1 << 15, - SVGA3DBLOCKDESC_SRGB = 1 << 16, - SVGA3DBLOCKDESC_EXP = 1 << 17, - SVGA3DBLOCKDESC_COLOR = 1 << 18, - SVGA3DBLOCKDESC_DEPTH = 1 << 19, - SVGA3DBLOCKDESC_BUMP = 1 << 20, - SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21, - SVGA3DBLOCKDESC_MIXED = 1 << 22, - SVGA3DBLOCKDESC_CX = 1 << 23, - - /* Different compressed format groups. */ - SVGA3DBLOCKDESC_BC1 = 1 << 24, - SVGA3DBLOCKDESC_BC2 = 1 << 25, - SVGA3DBLOCKDESC_BC3 = 1 << 26, - SVGA3DBLOCKDESC_BC4 = 1 << 27, - SVGA3DBLOCKDESC_BC5 = 1 << 28, - SVGA3DBLOCKDESC_BC6H = 1 << 29, - SVGA3DBLOCKDESC_BC7 = 1 << 30, - SVGA3DBLOCKDESC_COMPRESSED_MASK = SVGA3DBLOCKDESC_BC1 | - SVGA3DBLOCKDESC_BC2 | - SVGA3DBLOCKDESC_BC3 | - SVGA3DBLOCKDESC_BC4 | - SVGA3DBLOCKDESC_BC5 | - SVGA3DBLOCKDESC_BC6H | - SVGA3DBLOCKDESC_BC7, - - SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_SINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_SINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_BLUE | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_BLUE | - SVGA3DBLOCKDESC_SINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM | - SVGA3DBLOCKDESC_SRGB, - SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_BLUE | - SVGA3DBLOCKDESC_ALPHA | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM | - SVGA3DBLOCKDESC_SRGB, - SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_BLUE | - SVGA3DBLOCKDESC_ALPHA | - SVGA3DBLOCKDESC_SINT | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_BLUE | - SVGA3DBLOCKDESC_ALPHA | - SVGA3DBLOCKDESC_FP | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U | - SVGA3DBLOCKDESC_V | - SVGA3DBLOCKDESC_BUMP, - SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | - SVGA3DBLOCKDESC_BUMP_L | - SVGA3DBLOCKDESC_MIXED | - SVGA3DBLOCKDESC_BUMP, - SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV | - SVGA3DBLOCKDESC_W | - SVGA3DBLOCKDESC_BUMP, - SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | - SVGA3DBLOCKDESC_ALPHA | - SVGA3DBLOCKDESC_MIXED | - SVGA3DBLOCKDESC_BUMP, - SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | - SVGA3DBLOCKDESC_V | - SVGA3DBLOCKDESC_W | - SVGA3DBLOCKDESC_Q | - SVGA3DBLOCKDESC_BUMP, - SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_NORM | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE | - SVGA3DBLOCKDESC_ALPHA | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_NORM | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_FP | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | - SVGA3DBLOCKDESC_BLUE | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA | - SVGA3DBLOCKDESC_YUV_VIDEO | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | - SVGA3DBLOCKDESC_GREEN | - SVGA3DBLOCKDESC_BLUE | - SVGA3DBLOCKDESC_EXP | - SVGA3DBLOCKDESC_COLOR, - - SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED | - SVGA3DBLOCKDESC_TYPELESS, + SVGA3DBLOCKDESC_STENCIL = 1 << 11, + SVGA3DBLOCKDESC_TYPELESS = 1 << 12, + SVGA3DBLOCKDESC_SINT = 1 << 13, + SVGA3DBLOCKDESC_UINT = 1 << 14, + SVGA3DBLOCKDESC_NORM = 1 << 15, + SVGA3DBLOCKDESC_SRGB = 1 << 16, + SVGA3DBLOCKDESC_EXP = 1 << 17, + SVGA3DBLOCKDESC_COLOR = 1 << 18, + SVGA3DBLOCKDESC_DEPTH = 1 << 19, + SVGA3DBLOCKDESC_BUMP = 1 << 20, + SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21, + SVGA3DBLOCKDESC_MIXED = 1 << 22, + SVGA3DBLOCKDESC_CX = 1 << 23, + SVGA3DBLOCKDESC_BC1 = 1 << 24, + SVGA3DBLOCKDESC_BC2 = 1 << 25, + SVGA3DBLOCKDESC_BC3 = 1 << 26, + SVGA3DBLOCKDESC_BC4 = 1 << 27, + SVGA3DBLOCKDESC_BC5 = 1 << 28, + SVGA3DBLOCKDESC_BC6H = 1 << 29, + SVGA3DBLOCKDESC_BC7 = 1 << 30, + SVGA3DBLOCKDESC_COMPRESSED_MASK = SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_BC2 | + SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_BC4 | + SVGA3DBLOCKDESC_BC5 | + SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_BC7, + SVGA3DBLOCKDESC_A_UINT = + SVGA3DBLOCKDESC_ALPHA | SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_R_UINT = + SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_R_SINT = + SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_G_UINT = + SVGA3DBLOCKDESC_GREEN | SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_UINT | + SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_SINT | + SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_RGB_UNORM_SRGB = + SVGA3DBLOCKDESC_RGB_UNORM | SVGA3DBLOCKDESC_SRGB, + SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA | + SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RGBA_UNORM = + SVGA3DBLOCKDESC_RGBA_UINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = + SVGA3DBLOCKDESC_RGBA_UNORM | SVGA3DBLOCKDESC_SRGB, + SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA | + SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RGBA_SNORM = + SVGA3DBLOCKDESC_RGBA_SINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA | + SVGA3DBLOCKDESC_FP | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_UV = + SVGA3DBLOCKDESC_U | SVGA3DBLOCKDESC_V | SVGA3DBLOCKDESC_BUMP, + SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_BUMP_L | + SVGA3DBLOCKDESC_MIXED | SVGA3DBLOCKDESC_BUMP, + SVGA3DBLOCKDESC_UVW = + SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_W | SVGA3DBLOCKDESC_BUMP, + SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | SVGA3DBLOCKDESC_ALPHA | + SVGA3DBLOCKDESC_MIXED | SVGA3DBLOCKDESC_BUMP, + SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | SVGA3DBLOCKDESC_V | + SVGA3DBLOCKDESC_W | SVGA3DBLOCKDESC_Q | + SVGA3DBLOCKDESC_BUMP, + SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE | SVGA3DBLOCKDESC_UINT | + SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE | + SVGA3DBLOCKDESC_ALPHA | SVGA3DBLOCKDESC_UINT | + SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_R_FP = + SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_FP | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RG_FP = + SVGA3DBLOCKDESC_R_FP | SVGA3DBLOCKDESC_GREEN | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RGB_FP = + SVGA3DBLOCKDESC_RG_FP | SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_AYUV = + SVGA3DBLOCKDESC_ALPHA | SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN | + SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_EXP | + SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_COMP_TYPELESS = + SVGA3DBLOCKDESC_COMPRESSED | SVGA3DBLOCKDESC_TYPELESS, SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED | - SVGA3DBLOCKDESC_UINT | - SVGA3DBLOCKDESC_NORM | + SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR, SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED | - SVGA3DBLOCKDESC_SINT | - SVGA3DBLOCKDESC_NORM | + SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM | - SVGA3DBLOCKDESC_SRGB, - SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 | - SVGA3DBLOCKDESC_COMP_TYPELESS, - SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 | - SVGA3DBLOCKDESC_COMP_UNORM, - SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM | - SVGA3DBLOCKDESC_SRGB, - SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 | - SVGA3DBLOCKDESC_COMP_TYPELESS, - SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 | - SVGA3DBLOCKDESC_COMP_UNORM, - SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM | - SVGA3DBLOCKDESC_SRGB, - SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 | - SVGA3DBLOCKDESC_COMP_TYPELESS, - SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 | - SVGA3DBLOCKDESC_COMP_UNORM, - SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM | - SVGA3DBLOCKDESC_SRGB, - SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 | - SVGA3DBLOCKDESC_COMP_TYPELESS, - SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 | - SVGA3DBLOCKDESC_COMP_UNORM, - SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 | - SVGA3DBLOCKDESC_COMP_SNORM, - SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 | - SVGA3DBLOCKDESC_COMP_TYPELESS, - SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 | - SVGA3DBLOCKDESC_COMP_UNORM, - SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 | - SVGA3DBLOCKDESC_COMP_SNORM, - SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H | - SVGA3DBLOCKDESC_COMP_TYPELESS, - SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H | - SVGA3DBLOCKDESC_COMPRESSED, - SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H | - SVGA3DBLOCKDESC_COMPRESSED, - SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 | - SVGA3DBLOCKDESC_COMP_TYPELESS, - SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 | - SVGA3DBLOCKDESC_COMP_UNORM, - SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM | - SVGA3DBLOCKDESC_SRGB, - - SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO | - SVGA3DBLOCKDESC_PLANAR_YUV | - SVGA3DBLOCKDESC_2PLANAR_YUV | - SVGA3DBLOCKDESC_COLOR, - SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO | - SVGA3DBLOCKDESC_PLANAR_YUV | - SVGA3DBLOCKDESC_3PLANAR_YUV | - SVGA3DBLOCKDESC_COLOR, - - SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH | - SVGA3DBLOCKDESC_UINT, - SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | - SVGA3DBLOCKDESC_STENCIL, - SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH | - SVGA3DBLOCKDESC_STENCIL | - SVGA3DBLOCKDESC_UINT, - SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | - SVGA3DBLOCKDESC_FP, - - SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | - SVGA3DBLOCKDESC_UINT, - SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV | - SVGA3DBLOCKDESC_SINT | - SVGA3DBLOCKDESC_NORM, - SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM | - SVGA3DBLOCKDESC_CX, - SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ | - SVGA3DBLOCKDESC_SINT | - SVGA3DBLOCKDESC_NORM, -}; - + SVGA3DBLOCKDESC_COMP_UNORM_SRGB = + SVGA3DBLOCKDESC_COMP_UNORM | SVGA3DBLOCKDESC_SRGB, + SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = + SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_COMP_TYPELESS, + SVGA3DBLOCKDESC_BC1_COMP_UNORM = + SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_COMP_UNORM, + SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = + SVGA3DBLOCKDESC_BC1_COMP_UNORM | SVGA3DBLOCKDESC_SRGB, + SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = + SVGA3DBLOCKDESC_BC2 | SVGA3DBLOCKDESC_COMP_TYPELESS, + SVGA3DBLOCKDESC_BC2_COMP_UNORM = + SVGA3DBLOCKDESC_BC2 | SVGA3DBLOCKDESC_COMP_UNORM, + SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = + SVGA3DBLOCKDESC_BC2_COMP_UNORM | SVGA3DBLOCKDESC_SRGB, + SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = + SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_COMP_TYPELESS, + SVGA3DBLOCKDESC_BC3_COMP_UNORM = + SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_COMP_UNORM, + SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = + SVGA3DBLOCKDESC_BC3_COMP_UNORM | SVGA3DBLOCKDESC_SRGB, + SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = + SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_TYPELESS, + SVGA3DBLOCKDESC_BC4_COMP_UNORM = + SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_UNORM, + SVGA3DBLOCKDESC_BC4_COMP_SNORM = + SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_SNORM, + SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = + SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_TYPELESS, + SVGA3DBLOCKDESC_BC5_COMP_UNORM = + SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_UNORM, + SVGA3DBLOCKDESC_BC5_COMP_SNORM = + SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_SNORM, + SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = + SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMP_TYPELESS, + SVGA3DBLOCKDESC_BC6H_COMP_UF16 = + SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMPRESSED, + SVGA3DBLOCKDESC_BC6H_COMP_SF16 = + SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMPRESSED, + SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = + SVGA3DBLOCKDESC_BC7 | SVGA3DBLOCKDESC_COMP_TYPELESS, + SVGA3DBLOCKDESC_BC7_COMP_UNORM = + SVGA3DBLOCKDESC_BC7 | SVGA3DBLOCKDESC_COMP_UNORM, + SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = + SVGA3DBLOCKDESC_BC7_COMP_UNORM | SVGA3DBLOCKDESC_SRGB, + SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO | + SVGA3DBLOCKDESC_PLANAR_YUV | + SVGA3DBLOCKDESC_2PLANAR_YUV | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO | + SVGA3DBLOCKDESC_PLANAR_YUV | + SVGA3DBLOCKDESC_3PLANAR_YUV | SVGA3DBLOCKDESC_COLOR, + SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_UINT, + SVGA3DBLOCKDESC_DEPTH_UNORM = + SVGA3DBLOCKDESC_DEPTH_UINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_STENCIL, + SVGA3DBLOCKDESC_DS_UINT = + SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_STENCIL | SVGA3DBLOCKDESC_UINT, + SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_FP, + SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_UINT, + SVGA3DBLOCKDESC_UV_SNORM = + SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_NORM, + SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM | SVGA3DBLOCKDESC_CX, + SVGA3DBLOCKDESC_UVWQ_SNORM = + SVGA3DBLOCKDESC_UVWQ | SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_NORM, +} SVGA3dBlockDesc; typedef struct SVGA3dChannelDef { - union { - uint8 blue; - uint8 w_bump; - uint8 l_bump; - uint8 uv_video; - uint8 u_video; - }; - union { - uint8 green; - uint8 stencil; - uint8 v_bump; - uint8 v_video; - }; - union { - uint8 red; - uint8 u_bump; - uint8 luminance; - uint8 y_video; - uint8 depth; - uint8 data; - }; - union { - uint8 alpha; - uint8 q_bump; - uint8 exp; - }; + union { + uint8_t blue; + uint8_t w_bump; + uint8_t l_bump; + uint8_t uv_video; + uint8_t u_video; + }; + union { + uint8_t green; + uint8_t stencil; + uint8_t v_bump; + uint8_t v_video; + }; + union { + uint8_t red; + uint8_t u_bump; + uint8_t luminance; + uint8_t y_video; + uint8_t depth; + uint8_t data; + }; + union { + uint8_t alpha; + uint8_t q_bump; + uint8_t exp; + }; } SVGA3dChannelDef; -struct svga3d_surface_desc { +typedef struct SVGA3dSurfaceDesc { SVGA3dSurfaceFormat format; - enum svga3d_block_desc block_desc; + SVGA3dBlockDesc blockDesc; + SVGA3dSize blockSize; + uint32_t bytesPerBlock; + uint32_t pitchBytesPerBlock; + SVGA3dChannelDef bitDepth; + SVGA3dChannelDef bitOffset; +} SVGA3dSurfaceDesc; - SVGA3dSize block_size; - uint32 bytes_per_block; - uint32 pitch_bytes_per_block; - - SVGA3dChannelDef bitDepth; - SVGA3dChannelDef bitOffset; +static const SVGA3dSurfaceDesc g_SVGA3dSurfaceDescs[SVGA3D_FORMAT_MAX] = { + {SVGA3D_FORMAT_INVALID, + SVGA3DBLOCKDESC_NONE, + {1, 1, 1}, + 0, + 0, + {{0}, {0}, {0}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_X8R8G8B8, + SVGA3DBLOCKDESC_RGB_UNORM, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {0}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_A8R8G8B8, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_R5G6B5, + SVGA3DBLOCKDESC_RGB_UNORM, + {1, 1, 1}, + 2, + 2, + {{5}, {6}, {5}, {0}}, + {{0}, {5}, {11}, {0}}}, + {SVGA3D_X1R5G5B5, + SVGA3DBLOCKDESC_RGB_UNORM, + {1, 1, 1}, + 2, + 2, + {{5}, {5}, {5}, {0}}, + {{0}, {5}, {10}, {0}}}, + {SVGA3D_A1R5G5B5, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 2, + 2, + {{5}, {5}, {5}, {1}}, + {{0}, {5}, {10}, {15}}}, + {SVGA3D_A4R4G4B4, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 2, + 2, + {{4}, {4}, {4}, {4}}, + {{0}, {4}, {8}, {12}}}, + {SVGA3D_Z_D32, + SVGA3DBLOCKDESC_DEPTH_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_Z_D16, + SVGA3DBLOCKDESC_DEPTH_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_Z_D24S8, + SVGA3DBLOCKDESC_DS_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {8}, {24}, {0}}, + {{0}, {0}, {8}, {0}}}, + {SVGA3D_Z_D15S1, + SVGA3DBLOCKDESC_DS_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {1}, {15}, {0}}, + {{0}, {0}, {1}, {0}}}, + {SVGA3D_LUMINANCE8, + SVGA3DBLOCKDESC_L_UNORM, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_LUMINANCE4_ALPHA4, + SVGA3DBLOCKDESC_LA_UNORM, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {4}, {4}}, + {{0}, {0}, {0}, {4}}}, + {SVGA3D_LUMINANCE16, + SVGA3DBLOCKDESC_L_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_LUMINANCE8_ALPHA8, + SVGA3DBLOCKDESC_LA_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {8}, {8}}, + {{0}, {0}, {0}, {8}}}, + {SVGA3D_DXT1, + SVGA3DBLOCKDESC_BC1_COMP_UNORM, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_DXT2, + SVGA3DBLOCKDESC_BC2_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_DXT3, + SVGA3DBLOCKDESC_BC2_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_DXT4, + SVGA3DBLOCKDESC_BC3_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_DXT5, + SVGA3DBLOCKDESC_BC3_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BUMPU8V8, + SVGA3DBLOCKDESC_UV_SNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_BUMPL6V5U5, + SVGA3DBLOCKDESC_UVL, + {1, 1, 1}, + 2, + 2, + {{6}, {5}, {5}, {0}}, + {{10}, {5}, {0}, {0}}}, + {SVGA3D_BUMPX8L8V8U8, + SVGA3DBLOCKDESC_UVL, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {0}}, + {{16}, {8}, {0}, {0}}}, + {SVGA3D_FORMAT_DEAD1, + SVGA3DBLOCKDESC_NONE, + {1, 1, 1}, + 3, + 3, + {{8}, {8}, {8}, {0}}, + {{16}, {8}, {0}, {0}}}, + {SVGA3D_ARGB_S10E5, + SVGA3DBLOCKDESC_RGBA_FP, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_ARGB_S23E8, + SVGA3DBLOCKDESC_RGBA_FP, + {1, 1, 1}, + 16, + 16, + {{32}, {32}, {32}, {32}}, + {{64}, {32}, {0}, {96}}}, + {SVGA3D_A2R10G10B10, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 4, + 4, + {{10}, {10}, {10}, {2}}, + {{0}, {10}, {20}, {30}}}, + {SVGA3D_V8U8, + SVGA3DBLOCKDESC_UV_SNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_Q8W8V8U8, + SVGA3DBLOCKDESC_UVWQ_SNORM, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{16}, {8}, {0}, {24}}}, + {SVGA3D_CxV8U8, + SVGA3DBLOCKDESC_UVCX_SNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_X8L8V8U8, + SVGA3DBLOCKDESC_UVL, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {0}}, + {{16}, {8}, {0}, {0}}}, + {SVGA3D_A2W10V10U10, + SVGA3DBLOCKDESC_UVWA, + {1, 1, 1}, + 4, + 4, + {{10}, {10}, {10}, {2}}, + {{20}, {10}, {0}, {30}}}, + {SVGA3D_ALPHA8, + SVGA3DBLOCKDESC_A_UNORM, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {0}, {8}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R_S10E5, + SVGA3DBLOCKDESC_R_FP, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R_S23E8, + SVGA3DBLOCKDESC_R_FP, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_RG_S10E5, + SVGA3DBLOCKDESC_RG_FP, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_RG_S23E8, + SVGA3DBLOCKDESC_RG_FP, + {1, 1, 1}, + 8, + 8, + {{0}, {32}, {32}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_BUFFER, + SVGA3DBLOCKDESC_BUFFER, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_Z_D24X8, + SVGA3DBLOCKDESC_DEPTH_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {24}, {0}}, + {{0}, {0}, {8}, {0}}}, + {SVGA3D_V16U16, + SVGA3DBLOCKDESC_UV_SNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_G16R16, + SVGA3DBLOCKDESC_RG_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_A16B16G16R16, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_UYVY, + SVGA3DBLOCKDESC_YUV, + {2, 1, 1}, + 4, + 4, + {{8}, {0}, {8}, {0}}, + {{0}, {0}, {8}, {0}}}, + {SVGA3D_YUY2, + SVGA3DBLOCKDESC_YUV, + {2, 1, 1}, + 4, + 4, + {{8}, {0}, {8}, {0}}, + {{8}, {0}, {0}, {0}}}, + {SVGA3D_NV12, + SVGA3DBLOCKDESC_NV12, + {2, 2, 1}, + 6, + 2, + {{0}, {0}, {48}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_FORMAT_DEAD2, + SVGA3DBLOCKDESC_NONE, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_R32G32B32A32_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 16, + 16, + {{32}, {32}, {32}, {32}}, + {{64}, {32}, {0}, {96}}}, + {SVGA3D_R32G32B32A32_UINT, + SVGA3DBLOCKDESC_RGBA_UINT, + {1, 1, 1}, + 16, + 16, + {{32}, {32}, {32}, {32}}, + {{64}, {32}, {0}, {96}}}, + {SVGA3D_R32G32B32A32_SINT, + SVGA3DBLOCKDESC_RGBA_SINT, + {1, 1, 1}, + 16, + 16, + {{32}, {32}, {32}, {32}}, + {{64}, {32}, {0}, {96}}}, + {SVGA3D_R32G32B32_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 12, + 12, + {{32}, {32}, {32}, {0}}, + {{64}, {32}, {0}, {0}}}, + {SVGA3D_R32G32B32_FLOAT, + SVGA3DBLOCKDESC_RGB_FP, + {1, 1, 1}, + 12, + 12, + {{32}, {32}, {32}, {0}}, + {{64}, {32}, {0}, {0}}}, + {SVGA3D_R32G32B32_UINT, + SVGA3DBLOCKDESC_RGB_UINT, + {1, 1, 1}, + 12, + 12, + {{32}, {32}, {32}, {0}}, + {{64}, {32}, {0}, {0}}}, + {SVGA3D_R32G32B32_SINT, + SVGA3DBLOCKDESC_RGB_SINT, + {1, 1, 1}, + 12, + 12, + {{32}, {32}, {32}, {0}}, + {{64}, {32}, {0}, {0}}}, + {SVGA3D_R16G16B16A16_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_R16G16B16A16_UINT, + SVGA3DBLOCKDESC_RGBA_UINT, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_R16G16B16A16_SNORM, + SVGA3DBLOCKDESC_RGBA_SNORM, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_R16G16B16A16_SINT, + SVGA3DBLOCKDESC_RGBA_SINT, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_R32G32_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 8, + 8, + {{0}, {32}, {32}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_R32G32_UINT, + SVGA3DBLOCKDESC_RG_UINT, + {1, 1, 1}, + 8, + 8, + {{0}, {32}, {32}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_R32G32_SINT, + SVGA3DBLOCKDESC_RG_SINT, + {1, 1, 1}, + 8, + 8, + {{0}, {32}, {32}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_R32G8X24_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 8, + 8, + {{0}, {8}, {32}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_D32_FLOAT_S8X24_UINT, + SVGA3DBLOCKDESC_DS, + {1, 1, 1}, + 8, + 8, + {{0}, {8}, {32}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_R32_FLOAT_X8X24, + SVGA3DBLOCKDESC_R_FP, + {1, 1, 1}, + 8, + 8, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_X32_G8X24_UINT, + SVGA3DBLOCKDESC_G_UINT, + {1, 1, 1}, + 8, + 8, + {{0}, {8}, {0}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_R10G10B10A2_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{10}, {10}, {10}, {2}}, + {{20}, {10}, {0}, {30}}}, + {SVGA3D_R10G10B10A2_UINT, + SVGA3DBLOCKDESC_RGBA_UINT, + {1, 1, 1}, + 4, + 4, + {{10}, {10}, {10}, {2}}, + {{20}, {10}, {0}, {30}}}, + {SVGA3D_R11G11B10_FLOAT, + SVGA3DBLOCKDESC_RGB_FP, + {1, 1, 1}, + 4, + 4, + {{10}, {11}, {11}, {0}}, + {{22}, {11}, {0}, {0}}}, + {SVGA3D_R8G8B8A8_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{16}, {8}, {0}, {24}}}, + {SVGA3D_R8G8B8A8_UNORM, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{16}, {8}, {0}, {24}}}, + {SVGA3D_R8G8B8A8_UNORM_SRGB, + SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{16}, {8}, {0}, {24}}}, + {SVGA3D_R8G8B8A8_UINT, + SVGA3DBLOCKDESC_RGBA_UINT, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{16}, {8}, {0}, {24}}}, + {SVGA3D_R8G8B8A8_SINT, + SVGA3DBLOCKDESC_RGBA_SINT, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{16}, {8}, {0}, {24}}}, + {SVGA3D_R16G16_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_R16G16_UINT, + SVGA3DBLOCKDESC_RG_UINT, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_R16G16_SINT, + SVGA3DBLOCKDESC_RG_SINT, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_R32_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_D32_FLOAT, + SVGA3DBLOCKDESC_DEPTH_FP, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R32_UINT, + SVGA3DBLOCKDESC_R_UINT, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R32_SINT, + SVGA3DBLOCKDESC_R_SINT, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R24G8_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{0}, {8}, {24}, {0}}, + {{0}, {24}, {0}, {0}}}, + {SVGA3D_D24_UNORM_S8_UINT, + SVGA3DBLOCKDESC_DS_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {8}, {24}, {0}}, + {{0}, {24}, {0}, {0}}}, + {SVGA3D_R24_UNORM_X8, + SVGA3DBLOCKDESC_R_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {24}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_X24_G8_UINT, + SVGA3DBLOCKDESC_G_UINT, + {1, 1, 1}, + 4, + 4, + {{0}, {8}, {0}, {0}}, + {{0}, {24}, {0}, {0}}}, + {SVGA3D_R8G8_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_R8G8_UNORM, + SVGA3DBLOCKDESC_RG_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_R8G8_UINT, + SVGA3DBLOCKDESC_RG_UINT, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_R8G8_SINT, + SVGA3DBLOCKDESC_RG_SINT, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_R16_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R16_UNORM, + SVGA3DBLOCKDESC_R_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R16_UINT, + SVGA3DBLOCKDESC_R_UINT, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R16_SNORM, + SVGA3DBLOCKDESC_R_SNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R16_SINT, + SVGA3DBLOCKDESC_R_SINT, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R8_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R8_UNORM, + SVGA3DBLOCKDESC_R_UNORM, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R8_UINT, + SVGA3DBLOCKDESC_R_UINT, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R8_SNORM, + SVGA3DBLOCKDESC_R_SNORM, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R8_SINT, + SVGA3DBLOCKDESC_R_SINT, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_P8, + SVGA3DBLOCKDESC_NONE, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {8}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R9G9B9E5_SHAREDEXP, + SVGA3DBLOCKDESC_RGB_EXP, + {1, 1, 1}, + 4, + 4, + {{9}, {9}, {9}, {5}}, + {{18}, {9}, {0}, {27}}}, + {SVGA3D_R8G8_B8G8_UNORM, + SVGA3DBLOCKDESC_NONE, + {2, 1, 1}, + 4, + 4, + {{0}, {8}, {8}, {0}}, + {{0}, {0}, {8}, {0}}}, + {SVGA3D_G8R8_G8B8_UNORM, + SVGA3DBLOCKDESC_NONE, + {2, 1, 1}, + 4, + 4, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_BC1_TYPELESS, + SVGA3DBLOCKDESC_BC1_COMP_TYPELESS, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC1_UNORM_SRGB, + SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC2_TYPELESS, + SVGA3DBLOCKDESC_BC2_COMP_TYPELESS, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC2_UNORM_SRGB, + SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC3_TYPELESS, + SVGA3DBLOCKDESC_BC3_COMP_TYPELESS, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC3_UNORM_SRGB, + SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC4_TYPELESS, + SVGA3DBLOCKDESC_BC4_COMP_TYPELESS, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_ATI1, + SVGA3DBLOCKDESC_BC4_COMP_UNORM, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC4_SNORM, + SVGA3DBLOCKDESC_BC4_COMP_SNORM, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC5_TYPELESS, + SVGA3DBLOCKDESC_BC5_COMP_TYPELESS, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_ATI2, + SVGA3DBLOCKDESC_BC5_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC5_SNORM, + SVGA3DBLOCKDESC_BC5_COMP_SNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 4, + 4, + {{10}, {10}, {10}, {2}}, + {{20}, {10}, {0}, {30}}}, + {SVGA3D_B8G8R8A8_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_B8G8R8A8_UNORM_SRGB, + SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_B8G8R8X8_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {0}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_B8G8R8X8_UNORM_SRGB, + SVGA3DBLOCKDESC_RGB_UNORM_SRGB, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {0}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_Z_DF16, + SVGA3DBLOCKDESC_DEPTH_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_Z_DF24, + SVGA3DBLOCKDESC_DEPTH_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {24}, {0}}, + {{0}, {0}, {8}, {0}}}, + {SVGA3D_Z_D24S8_INT, + SVGA3DBLOCKDESC_DS_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {8}, {24}, {0}}, + {{0}, {0}, {8}, {0}}}, + {SVGA3D_YV12, + SVGA3DBLOCKDESC_YV12, + {2, 2, 1}, + 6, + 2, + {{0}, {0}, {48}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R32G32B32A32_FLOAT, + SVGA3DBLOCKDESC_RGBA_FP, + {1, 1, 1}, + 16, + 16, + {{32}, {32}, {32}, {32}}, + {{64}, {32}, {0}, {96}}}, + {SVGA3D_R16G16B16A16_FLOAT, + SVGA3DBLOCKDESC_RGBA_FP, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_R16G16B16A16_UNORM, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 8, + 8, + {{16}, {16}, {16}, {16}}, + {{32}, {16}, {0}, {48}}}, + {SVGA3D_R32G32_FLOAT, + SVGA3DBLOCKDESC_RG_FP, + {1, 1, 1}, + 8, + 8, + {{0}, {32}, {32}, {0}}, + {{0}, {32}, {0}, {0}}}, + {SVGA3D_R10G10B10A2_UNORM, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 4, + 4, + {{10}, {10}, {10}, {2}}, + {{20}, {10}, {0}, {30}}}, + {SVGA3D_R8G8B8A8_SNORM, + SVGA3DBLOCKDESC_RGBA_SNORM, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{16}, {8}, {0}, {24}}}, + {SVGA3D_R16G16_FLOAT, + SVGA3DBLOCKDESC_RG_FP, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_R16G16_UNORM, + SVGA3DBLOCKDESC_RG_UNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_R16G16_SNORM, + SVGA3DBLOCKDESC_RG_SNORM, + {1, 1, 1}, + 4, + 4, + {{0}, {16}, {16}, {0}}, + {{0}, {16}, {0}, {0}}}, + {SVGA3D_R32_FLOAT, + SVGA3DBLOCKDESC_R_FP, + {1, 1, 1}, + 4, + 4, + {{0}, {0}, {32}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_R8G8_SNORM, + SVGA3DBLOCKDESC_RG_SNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {8}, {8}, {0}}, + {{0}, {8}, {0}, {0}}}, + {SVGA3D_R16_FLOAT, + SVGA3DBLOCKDESC_R_FP, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_D16_UNORM, + SVGA3DBLOCKDESC_DEPTH_UNORM, + {1, 1, 1}, + 2, + 2, + {{0}, {0}, {16}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_A8_UNORM, + SVGA3DBLOCKDESC_A_UNORM, + {1, 1, 1}, + 1, + 1, + {{0}, {0}, {0}, {8}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC1_UNORM, + SVGA3DBLOCKDESC_BC1_COMP_UNORM, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC2_UNORM, + SVGA3DBLOCKDESC_BC2_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC3_UNORM, + SVGA3DBLOCKDESC_BC3_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_B5G6R5_UNORM, + SVGA3DBLOCKDESC_RGB_UNORM, + {1, 1, 1}, + 2, + 2, + {{5}, {6}, {5}, {0}}, + {{0}, {5}, {11}, {0}}}, + {SVGA3D_B5G5R5A1_UNORM, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 2, + 2, + {{5}, {5}, {5}, {1}}, + {{0}, {5}, {10}, {15}}}, + {SVGA3D_B8G8R8A8_UNORM, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_B8G8R8X8_UNORM, + SVGA3DBLOCKDESC_RGB_UNORM, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {0}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_BC4_UNORM, + SVGA3DBLOCKDESC_BC4_COMP_UNORM, + {4, 4, 1}, + 8, + 8, + {{0}, {0}, {64}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC5_UNORM, + SVGA3DBLOCKDESC_BC5_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_B4G4R4A4_UNORM, + SVGA3DBLOCKDESC_RGBA_UNORM, + {1, 1, 1}, + 2, + 2, + {{4}, {4}, {4}, {4}}, + {{0}, {4}, {8}, {12}}}, + {SVGA3D_BC6H_TYPELESS, + SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC6H_UF16, + SVGA3DBLOCKDESC_BC6H_COMP_UF16, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC6H_SF16, + SVGA3DBLOCKDESC_BC6H_COMP_SF16, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC7_TYPELESS, + SVGA3DBLOCKDESC_BC7_COMP_TYPELESS, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC7_UNORM, + SVGA3DBLOCKDESC_BC7_COMP_UNORM, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_BC7_UNORM_SRGB, + SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB, + {4, 4, 1}, + 16, + 16, + {{0}, {0}, {128}, {0}}, + {{0}, {0}, {0}, {0}}}, + {SVGA3D_AYUV, + SVGA3DBLOCKDESC_AYUV, + {1, 1, 1}, + 4, + 4, + {{8}, {8}, {8}, {8}}, + {{0}, {8}, {16}, {24}}}, + {SVGA3D_R11G11B10_TYPELESS, + SVGA3DBLOCKDESC_TYPELESS, + {1, 1, 1}, + 4, + 4, + {{10}, {11}, {11}, {0}}, + {{22}, {11}, {0}, {0}}}, }; -static const struct svga3d_surface_desc svga3d_surface_descs[] = { - {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE, - {1, 1, 1}, 0, 0, - {{0}, {0}, {0}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {0}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM, - {1, 1, 1}, 2, 2, - {{5}, {6}, {5}, {0}}, - {{0}, {5}, {11}, {0}}}, - - {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM, - {1, 1, 1}, 2, 2, - {{5}, {5}, {5}, {0}}, - {{0}, {5}, {10}, {0}}}, - - {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 2, 2, - {{5}, {5}, {5}, {1}}, - {{0}, {5}, {10}, {15}}}, - - {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 2, 2, - {{4}, {4}, {4}, {4}}, - {{0}, {4}, {8}, {12}}}, - - {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {8}, {24}, {0}}, - {{0}, {0}, {8}, {0}}}, - - {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {1}, {15}, {0}}, - {{0}, {0}, {1}, {0}}}, - - {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM, - {1, 1, 1}, 1, 1, - {{0}, {0}, {4}, {4}}, - {{0}, {0}, {0}, {4}}}, - - {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {0}, {8}, {8}}, - {{0}, {0}, {0}, {8}}}, - - {SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL, - {1, 1, 1}, 2, 2, - {{6}, {5}, {5}, {0}}, - {{10}, {5}, {0}, {0}}}, - - {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {0}}, - {{16}, {8}, {0}, {0}}}, - - {SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE, - {1, 1, 1}, 3, 3, - {{8}, {8}, {8}, {0}}, - {{16}, {8}, {0}, {0}}}, - - {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP, - {1, 1, 1}, 16, 16, - {{32}, {32}, {32}, {32}}, - {{64}, {32}, {0}, {96}}}, - - {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 4, 4, - {{10}, {10}, {10}, {2}}, - {{0}, {10}, {20}, {30}}}, - - {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{16}, {8}, {0}, {24}}}, - - {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {0}}, - {{16}, {8}, {0}, {0}}}, - - {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA, - {1, 1, 1}, 4, 4, - {{10}, {10}, {10}, {2}}, - {{20}, {10}, {0}, {30}}}, - - {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM, - {1, 1, 1}, 1, 1, - {{0}, {0}, {0}, {8}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP, - {1, 1, 1}, 4, 4, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP, - {1, 1, 1}, 8, 8, - {{0}, {32}, {32}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {0}, {24}, {0}}, - {{0}, {0}, {8}, {0}}}, - - {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV, - {2, 1, 1}, 4, 4, - {{8}, {0}, {8}, {0}}, - {{0}, {0}, {8}, {0}}}, - - {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV, - {2, 1, 1}, 4, 4, - {{8}, {0}, {8}, {0}}, - {{8}, {0}, {0}, {0}}}, - - {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12, - {2, 2, 1}, 6, 2, - {{0}, {0}, {48}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_FORMAT_DEAD2, SVGA3DBLOCKDESC_NONE, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 16, 16, - {{32}, {32}, {32}, {32}}, - {{64}, {32}, {0}, {96}}}, - - {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT, - {1, 1, 1}, 16, 16, - {{32}, {32}, {32}, {32}}, - {{64}, {32}, {0}, {96}}}, - - {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT, - {1, 1, 1}, 16, 16, - {{32}, {32}, {32}, {32}}, - {{64}, {32}, {0}, {96}}}, - - {SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 12, 12, - {{32}, {32}, {32}, {0}}, - {{64}, {32}, {0}, {0}}}, - - {SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP, - {1, 1, 1}, 12, 12, - {{32}, {32}, {32}, {0}}, - {{64}, {32}, {0}, {0}}}, - - {SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB_UINT, - {1, 1, 1}, 12, 12, - {{32}, {32}, {32}, {0}}, - {{64}, {32}, {0}, {0}}}, - - {SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_RGB_SINT, - {1, 1, 1}, 12, 12, - {{32}, {32}, {32}, {0}}, - {{64}, {32}, {0}, {0}}}, - - {SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA_UINT, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_RGBA_SINT, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 8, 8, - {{0}, {32}, {32}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG_UINT, - {1, 1, 1}, 8, 8, - {{0}, {32}, {32}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_RG_SINT, - {1, 1, 1}, 8, 8, - {{0}, {32}, {32}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 8, 8, - {{0}, {8}, {32}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS, - {1, 1, 1}, 8, 8, - {{0}, {8}, {32}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_R32_FLOAT_X8X24, SVGA3DBLOCKDESC_R_FP, - {1, 1, 1}, 8, 8, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_X32_G8X24_UINT, SVGA3DBLOCKDESC_G_UINT, - {1, 1, 1}, 8, 8, - {{0}, {8}, {0}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{10}, {10}, {10}, {2}}, - {{20}, {10}, {0}, {30}}}, - - {SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA_UINT, - {1, 1, 1}, 4, 4, - {{10}, {10}, {10}, {2}}, - {{20}, {10}, {0}, {30}}}, - - {SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP, - {1, 1, 1}, 4, 4, - {{10}, {11}, {11}, {0}}, - {{22}, {11}, {0}, {0}}}, - - {SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{16}, {8}, {0}, {24}}}, - - {SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{16}, {8}, {0}, {24}}}, - - {SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{16}, {8}, {0}, {24}}}, - - {SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA_UINT, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{16}, {8}, {0}, {24}}}, - - {SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA_SINT, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{16}, {8}, {0}, {24}}}, - - {SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_UINT, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_RG_SINT, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH_FP, - {1, 1, 1}, 4, 4, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R32_UINT, SVGA3DBLOCKDESC_R_UINT, - {1, 1, 1}, 4, 4, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R32_SINT, SVGA3DBLOCKDESC_R_SINT, - {1, 1, 1}, 4, 4, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{0}, {8}, {24}, {0}}, - {{0}, {24}, {0}, {0}}}, - - {SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {8}, {24}, {0}}, - {{0}, {24}, {0}, {0}}}, - - {SVGA3D_R24_UNORM_X8, SVGA3DBLOCKDESC_R_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {0}, {24}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_X24_G8_UINT, SVGA3DBLOCKDESC_G_UINT, - {1, 1, 1}, 4, 4, - {{0}, {8}, {0}, {0}}, - {{0}, {24}, {0}, {0}}}, - - {SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG_UINT, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_RG_SINT, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_R_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R16_UINT, SVGA3DBLOCKDESC_R_UINT, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_R_SNORM, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R16_SINT, SVGA3DBLOCKDESC_R_SINT, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_R_UNORM, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R8_UINT, SVGA3DBLOCKDESC_R_UINT, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_R_SNORM, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R8_SINT, SVGA3DBLOCKDESC_R_SINT, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_P8, SVGA3DBLOCKDESC_NONE, - {1, 1, 1}, 1, 1, - {{0}, {0}, {8}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGB_EXP, - {1, 1, 1}, 4, 4, - {{9}, {9}, {9}, {5}}, - {{18}, {9}, {0}, {27}}}, - - {SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_NONE, - {2, 1, 1}, 4, 4, - {{0}, {8}, {8}, {0}}, - {{0}, {0}, {8}, {0}}}, - - {SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_NONE, - {2, 1, 1}, 4, 4, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_BC1_COMP_TYPELESS, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_BC2_COMP_TYPELESS, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_BC3_COMP_TYPELESS, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_BC4_COMP_TYPELESS, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_ATI1, SVGA3DBLOCKDESC_BC4_COMP_UNORM, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_BC4_COMP_SNORM, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_BC5_COMP_TYPELESS, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_ATI2, SVGA3DBLOCKDESC_BC5_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_BC5_COMP_SNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 4, 4, - {{10}, {10}, {10}, {2}}, - {{20}, {10}, {0}, {30}}}, - - {SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {0}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_UNORM_SRGB, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {0}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {0}, {24}, {0}}, - {{0}, {0}, {8}, {0}}}, - - {SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {8}, {24}, {0}}, - {{0}, {0}, {8}, {0}}}, - - {SVGA3D_YV12, SVGA3DBLOCKDESC_YV12, - {2, 2, 1}, 6, 2, - {{0}, {0}, {48}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, - {1, 1, 1}, 16, 16, - {{32}, {32}, {32}, {32}}, - {{64}, {32}, {0}, {96}}}, - - {SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 8, 8, - {{16}, {16}, {16}, {16}}, - {{32}, {16}, {0}, {48}}}, - - {SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP, - {1, 1, 1}, 8, 8, - {{0}, {32}, {32}, {0}}, - {{0}, {32}, {0}, {0}}}, - - {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 4, 4, - {{10}, {10}, {10}, {2}}, - {{20}, {10}, {0}, {30}}}, - - {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{16}, {8}, {0}, {24}}}, - - {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM, - {1, 1, 1}, 4, 4, - {{0}, {16}, {16}, {0}}, - {{0}, {16}, {0}, {0}}}, - - {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP, - {1, 1, 1}, 4, 4, - {{0}, {0}, {32}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM, - {1, 1, 1}, 2, 2, - {{0}, {8}, {8}, {0}}, - {{0}, {8}, {0}, {0}}}, - - {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM, - {1, 1, 1}, 2, 2, - {{0}, {0}, {16}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM, - {1, 1, 1}, 1, 1, - {{0}, {0}, {0}, {8}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, - {1, 1, 1}, 2, 2, - {{5}, {6}, {5}, {0}}, - {{0}, {5}, {11}, {0}}}, - - {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 2, 2, - {{5}, {5}, {5}, {1}}, - {{0}, {5}, {10}, {15}}}, - - {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {0}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM, - {4, 4, 1}, 8, 8, - {{0}, {0}, {64}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, - {1, 1, 1}, 2, 2, - {{4}, {4}, {4}, {4}}, - {{0}, {4}, {8}, {12}}}, - - {SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB, - {4, 4, 1}, 16, 16, - {{0}, {0}, {128}, {0}}, - {{0}, {0}, {0}, {0}}}, - - {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV, - {1, 1, 1}, 4, 4, - {{8}, {8}, {8}, {8}}, - {{0}, {8}, {16}, {24}}}, - - {SVGA3D_R11G11B10_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, - {1, 1, 1}, 4, 4, - {{10}, {11}, {11}, {0}}, - {{22}, {11}, {0}, {0}}}, -}; - - - -extern const struct svga3d_surface_desc g_SVGA3dSurfaceDescs[]; -extern int g_SVGA3dSurfaceDescs_size; - -static inline uint32 clamped_umul32(uint32 a, uint32 b) -{ - uint64_t tmp = (uint64_t) a*b; - return (tmp > (uint64_t) ((uint32) -1)) ? (uint32) -1 : tmp; -} - -static inline uint32 clamped_uadd32(uint32 a, uint32 b) -{ - uint32 c = a + b; - if (c < a || c < b) { - return MAX_UINT32; - } - return c; -} - - -static inline const struct svga3d_surface_desc * -svga3dsurface_get_desc(SVGA3dSurfaceFormat format) -{ - if (format < ARRAY_SIZE(svga3d_surface_descs)) - return &svga3d_surface_descs[format]; - - return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID]; -} - -/* - *---------------------------------------------------------------------- - * - * svga3dsurface_get_mip_size -- - * - * Given a base level size and the mip level, compute the size of - * the mip level. - * - * Results: - * See above. - * - * Side effects: - * None. - * - *---------------------------------------------------------------------- - */ - -static inline SVGA3dSize -svga3dsurface_get_mip_size(SVGA3dSize base_level, uint32 mip_level) -{ - SVGA3dSize size; - - size.width = max_t(uint32, base_level.width >> mip_level, 1); - size.height = max_t(uint32, base_level.height >> mip_level, 1); - size.depth = max_t(uint32, base_level.depth >> mip_level, 1); - return size; -} - -static inline void -svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc, - const SVGA3dSize *pixel_size, - SVGA3dSize *block_size) -{ - block_size->width = DIV_ROUND_UP(pixel_size->width, - desc->block_size.width); - block_size->height = DIV_ROUND_UP(pixel_size->height, - desc->block_size.height); - block_size->depth = DIV_ROUND_UP(pixel_size->depth, - desc->block_size.depth); -} - -static inline bool -svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc) -{ - return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0; -} - -static inline uint32 -svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc, - const SVGA3dSize *size) -{ - uint32 pitch; - SVGA3dSize blocks; - - svga3dsurface_get_size_in_blocks(desc, size, &blocks); - - pitch = blocks.width * desc->pitch_bytes_per_block; - - return pitch; -} - -/* - *----------------------------------------------------------------------------- - * - * svga3dsurface_get_image_buffer_size -- - * - * Return the number of bytes of buffer space required to store - * one image of a surface, optionally using the specified pitch. - * - * If pitch is zero, it is assumed that rows are tightly packed. - * - * This function is overflow-safe. If the result would have - * overflowed, instead we return MAX_UINT32. - * - * Results: - * Byte count. - * - * Side effects: - * None. - * - *----------------------------------------------------------------------------- - */ - -static inline uint32 -svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc, - const SVGA3dSize *size, - uint32 pitch) -{ - SVGA3dSize image_blocks; - uint32 slice_size, total_size; - - svga3dsurface_get_size_in_blocks(desc, size, &image_blocks); - - if (svga3dsurface_is_planar_surface(desc)) { - total_size = clamped_umul32(image_blocks.width, - image_blocks.height); - total_size = clamped_umul32(total_size, image_blocks.depth); - total_size = clamped_umul32(total_size, desc->bytes_per_block); - return total_size; - } - - if (pitch == 0) - pitch = svga3dsurface_calculate_pitch(desc, size); - - slice_size = clamped_umul32(image_blocks.height, pitch); - total_size = clamped_umul32(slice_size, image_blocks.depth); - - return total_size; -} - - -static inline uint32 -svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format, - SVGA3dSize baseLevelSize, - uint32 numMipLevels, - uint32 layer, - uint32 mip) - -{ - uint32 offset; - uint32 mipChainBytes; - uint32 mipChainBytesToLevel; - uint32 i; - const struct svga3d_surface_desc *desc; - SVGA3dSize mipSize; - uint32 bytes; - - desc = svga3dsurface_get_desc(format); - - mipChainBytes = 0; - mipChainBytesToLevel = 0; - for (i = 0; i < numMipLevels; i++) { - mipSize = svga3dsurface_get_mip_size(baseLevelSize, i); - bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0); - mipChainBytes += bytes; - if (i < mip) { - mipChainBytesToLevel += bytes; - } - } - - offset = mipChainBytes * layer + mipChainBytesToLevel; - - return offset; -} - - -static inline uint32 -svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, - SVGA3dSize base_level_size, - uint32 num_mip_levels, - uint32 num_layers) -{ - const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); - uint64_t total_size = 0; - uint32 mip; - - for (mip = 0; mip < num_mip_levels; mip++) { - SVGA3dSize size = - svga3dsurface_get_mip_size(base_level_size, mip); - total_size += svga3dsurface_get_image_buffer_size(desc, - &size, 0); - } - - total_size *= num_layers; - - return (total_size > (uint64_t) MAX_UINT32) ? MAX_UINT32 : - (uint32) total_size; -} - - -/** - * svga3dsurface_get_serialized_size_extended - Returns the number of bytes - * required for a surface with given parameters. Support for sample count. - * - */ -static inline uint32 -svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format, - SVGA3dSize base_level_size, - uint32 num_mip_levels, - uint32 num_layers, - uint32 num_samples) -{ - uint64_t total_size = svga3dsurface_get_serialized_size(format, - base_level_size, - num_mip_levels, - num_layers); - - total_size *= (num_samples > 1 ? num_samples : 1); - - return (total_size > (uint64_t) MAX_UINT32) ? MAX_UINT32 : - (uint32) total_size; -} - - -/** - * Compute the offset (in bytes) to a pixel in an image (or volume). - * 'width' is the image width in pixels - * 'height' is the image height in pixels - */ -static inline uint32 -svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format, - uint32 width, uint32 height, - uint32 x, uint32 y, uint32 z) -{ - const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); - const uint32 bw = desc->block_size.width, bh = desc->block_size.height; - const uint32 bd = desc->block_size.depth; - const uint32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block; - const uint32 imgstride = DIV_ROUND_UP(height, bh) * rowstride; - const uint32 offset = (z / bd * imgstride + - y / bh * rowstride + - x / bw * desc->bytes_per_block); - return offset; +#ifdef __cplusplus } +#endif #endif diff --git a/src/gallium/drivers/svga/include/svga3d_types.h b/src/gallium/drivers/svga/include/svga3d_types.h index 59a01fc1d03..cab5aec29ff 100644 --- a/src/gallium/drivers/svga/include/svga3d_types.h +++ b/src/gallium/drivers/svga/include/svga3d_types.h @@ -1,8 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2012-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2012-2024 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* @@ -11,61 +31,13 @@ * SVGA 3d hardware definitions for basic types */ - - - - #ifndef _SVGA3D_TYPES_H_ #define _SVGA3D_TYPES_H_ -#define INCLUDE_ALLOW_MODULE -#define INCLUDE_ALLOW_USERLEVEL -#define INCLUDE_ALLOW_VMCORE +#include "vm_basic_types.h" -#include "includeCheck.h" - -/* - * Suffix for 64-bit constants. Use it like this: - * CONST64(0x7fffffffffffffff) for signed or - * CONST64U(0x7fffffffffffffff) for unsigned. - * - * 2004.08.30(thutt): - * The vmcore/asm64/gen* programs are compiled as 32-bit - * applications, but must handle 64 bit constants. If the - * 64-bit-constant defining macros are already defined, the - * definition will not be overwritten. - */ - -#if !defined(CONST64) || !defined(CONST64U) -#ifdef _MSC_VER -#define CONST64(c) c##I64 -#define CONST64U(c) c##uI64 -#elif defined __APPLE__ -#define CONST64(c) c##LL -#define CONST64U(c) c##uLL -#elif __GNUC__ -#if defined(VM_X86_64) || defined(VM_ARM_64) -#define CONST64(c) c##L -#define CONST64U(c) c##uL -#else -#define CONST64(c) c##LL -#define CONST64U(c) c##uLL -#endif -#else -#error - Need compiler define for CONST64 -#endif -#endif - -#define MIN_UINT64 (CONST64U(0)) -#define MAX_UINT64 (CONST64U(0xffffffffffffffff)) -#include "svga_types.h" - -/* - * Generic Types - */ - -#define SVGA3D_INVALID_ID ((uint32)-1) -#define SVGA3D_RESERVED_ID ((uint32)-2) +#define SVGA3D_INVALID_ID ((uint32) - 1) +#define SVGA3D_RESERVED_ID ((uint32) - 2) #define SVGA3D_RESOURCE_TYPE_MIN 1 #define SVGA3D_RESOURCE_BUFFER 1 @@ -78,100 +50,85 @@ #define SVGA3D_RESOURCE_TYPE_MAX 7 typedef uint32 SVGA3dResourceType; -typedef uint8 SVGABool8; /* 8-bit Bool definition */ -typedef uint32 SVGA3dBool; /* 32-bit Bool definition */ -typedef uint32 SVGA3dColor; /* a, r, g, b */ +typedef uint8 SVGABool8; +typedef uint32 SVGA3dBool; +typedef uint32 SVGA3dColor; typedef uint32 SVGA3dSurfaceId; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 numerator; uint32 denominator; -} -#include "vmware_pack_end.h" -SVGA3dFraction64; +} SVGA3dFraction64; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCopyRect { - uint32 x; - uint32 y; - uint32 w; - uint32 h; - uint32 srcx; - uint32 srcy; -} -#include "vmware_pack_end.h" -SVGA3dCopyRect; +#pragma pack(push, 1) +typedef struct SVGA3dCopyRect { + uint32 x; + uint32 y; + uint32 w; + uint32 h; + uint32 srcx; + uint32 srcy; +} SVGA3dCopyRect; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dCopyBox { - uint32 x; - uint32 y; - uint32 z; - uint32 w; - uint32 h; - uint32 d; - uint32 srcx; - uint32 srcy; - uint32 srcz; -} -#include "vmware_pack_end.h" -SVGA3dCopyBox; +#pragma pack(push, 1) +typedef struct SVGA3dCopyBox { + uint32 x; + uint32 y; + uint32 z; + uint32 w; + uint32 h; + uint32 d; + uint32 srcx; + uint32 srcy; + uint32 srcz; +} SVGA3dCopyBox; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dRect { - uint32 x; - uint32 y; - uint32 w; - uint32 h; -} -#include "vmware_pack_end.h" -SVGA3dRect; +#pragma pack(push, 1) +typedef struct SVGA3dRect { + uint32 x; + uint32 y; + uint32 w; + uint32 h; +} SVGA3dRect; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 x; - uint32 y; - uint32 z; - uint32 w; - uint32 h; - uint32 d; -} -#include "vmware_pack_end.h" -SVGA3dBox; +#pragma pack(push, 1) +typedef struct { + uint32 x; + uint32 y; + uint32 z; + uint32 w; + uint32 h; + uint32 d; +} SVGA3dBox; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - int32 x; - int32 y; - int32 z; - int32 w; - int32 h; - int32 d; -} -#include "vmware_pack_end.h" -SVGA3dSignedBox; +#pragma pack(push, 1) +typedef struct { + int32 x; + int32 y; + int32 z; + int32 w; + int32 h; + int32 d; +} SVGA3dSignedBox; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { - uint32 x; - uint32 y; - uint32 z; -} -#include "vmware_pack_end.h" -SVGA3dPoint; +#pragma pack(push, 1) +typedef struct { + uint32 x; + uint32 y; + uint32 z; +} SVGA3dPoint; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -union { +#pragma pack(push, 1) +typedef union { struct { float r; float g; @@ -180,312 +137,257 @@ union { }; float value[4]; -} -#include "vmware_pack_end.h" -SVGA3dRGBAFloat; +} SVGA3dRGBAFloat; +#pragma pack(pop) - -/* - * Surface formats. - */ typedef enum SVGA3dSurfaceFormat { - SVGA3D_FORMAT_INVALID = 0, + SVGA3D_FORMAT_INVALID = 0, - SVGA3D_X8R8G8B8 = 1, - SVGA3D_FORMAT_MIN = 1, + SVGA3D_X8R8G8B8 = 1, + SVGA3D_FORMAT_MIN = 1, - SVGA3D_A8R8G8B8 = 2, + SVGA3D_A8R8G8B8 = 2, - SVGA3D_R5G6B5 = 3, - SVGA3D_X1R5G5B5 = 4, - SVGA3D_A1R5G5B5 = 5, - SVGA3D_A4R4G4B4 = 6, + SVGA3D_R5G6B5 = 3, + SVGA3D_X1R5G5B5 = 4, + SVGA3D_A1R5G5B5 = 5, + SVGA3D_A4R4G4B4 = 6, - SVGA3D_Z_D32 = 7, - SVGA3D_Z_D16 = 8, - SVGA3D_Z_D24S8 = 9, - SVGA3D_Z_D15S1 = 10, + SVGA3D_Z_D32 = 7, + SVGA3D_Z_D16 = 8, + SVGA3D_Z_D24S8 = 9, + SVGA3D_Z_D15S1 = 10, - SVGA3D_LUMINANCE8 = 11, - SVGA3D_LUMINANCE4_ALPHA4 = 12, - SVGA3D_LUMINANCE16 = 13, - SVGA3D_LUMINANCE8_ALPHA8 = 14, + SVGA3D_LUMINANCE8 = 11, + SVGA3D_LUMINANCE4_ALPHA4 = 12, + SVGA3D_LUMINANCE16 = 13, + SVGA3D_LUMINANCE8_ALPHA8 = 14, - SVGA3D_DXT1 = 15, - SVGA3D_DXT2 = 16, - SVGA3D_DXT3 = 17, - SVGA3D_DXT4 = 18, - SVGA3D_DXT5 = 19, + SVGA3D_DXT1 = 15, + SVGA3D_DXT2 = 16, + SVGA3D_DXT3 = 17, + SVGA3D_DXT4 = 18, + SVGA3D_DXT5 = 19, - SVGA3D_BUMPU8V8 = 20, - SVGA3D_BUMPL6V5U5 = 21, - SVGA3D_BUMPX8L8V8U8 = 22, - SVGA3D_FORMAT_DEAD1 = 23, + SVGA3D_BUMPU8V8 = 20, + SVGA3D_BUMPL6V5U5 = 21, + SVGA3D_BUMPX8L8V8U8 = 22, + SVGA3D_FORMAT_DEAD1 = 23, - SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */ - SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */ + SVGA3D_ARGB_S10E5 = 24, + SVGA3D_ARGB_S23E8 = 25, - SVGA3D_A2R10G10B10 = 26, + SVGA3D_A2R10G10B10 = 26, - /* signed formats */ - SVGA3D_V8U8 = 27, - SVGA3D_Q8W8V8U8 = 28, - SVGA3D_CxV8U8 = 29, + SVGA3D_V8U8 = 27, + SVGA3D_Q8W8V8U8 = 28, + SVGA3D_CxV8U8 = 29, - /* mixed formats */ - SVGA3D_X8L8V8U8 = 30, - SVGA3D_A2W10V10U10 = 31, + SVGA3D_X8L8V8U8 = 30, + SVGA3D_A2W10V10U10 = 31, - SVGA3D_ALPHA8 = 32, + SVGA3D_ALPHA8 = 32, - /* Single- and dual-component floating point formats */ - SVGA3D_R_S10E5 = 33, - SVGA3D_R_S23E8 = 34, - SVGA3D_RG_S10E5 = 35, - SVGA3D_RG_S23E8 = 36, + SVGA3D_R_S10E5 = 33, + SVGA3D_R_S23E8 = 34, + SVGA3D_RG_S10E5 = 35, + SVGA3D_RG_S23E8 = 36, - SVGA3D_BUFFER = 37, + SVGA3D_BUFFER = 37, - SVGA3D_Z_D24X8 = 38, + SVGA3D_Z_D24X8 = 38, - SVGA3D_V16U16 = 39, + SVGA3D_V16U16 = 39, - SVGA3D_G16R16 = 40, - SVGA3D_A16B16G16R16 = 41, + SVGA3D_G16R16 = 40, + SVGA3D_A16B16G16R16 = 41, - /* Packed Video formats */ - SVGA3D_UYVY = 42, - SVGA3D_YUY2 = 43, + SVGA3D_UYVY = 42, + SVGA3D_YUY2 = 43, - /* Planar video formats */ - SVGA3D_NV12 = 44, + SVGA3D_NV12 = 44, - SVGA3D_FORMAT_DEAD2 = 45, + SVGA3D_FORMAT_DEAD2 = 45, - SVGA3D_R32G32B32A32_TYPELESS = 46, - SVGA3D_R32G32B32A32_UINT = 47, - SVGA3D_R32G32B32A32_SINT = 48, - SVGA3D_R32G32B32_TYPELESS = 49, - SVGA3D_R32G32B32_FLOAT = 50, - SVGA3D_R32G32B32_UINT = 51, - SVGA3D_R32G32B32_SINT = 52, - SVGA3D_R16G16B16A16_TYPELESS = 53, - SVGA3D_R16G16B16A16_UINT = 54, - SVGA3D_R16G16B16A16_SNORM = 55, - SVGA3D_R16G16B16A16_SINT = 56, - SVGA3D_R32G32_TYPELESS = 57, - SVGA3D_R32G32_UINT = 58, - SVGA3D_R32G32_SINT = 59, - SVGA3D_R32G8X24_TYPELESS = 60, - SVGA3D_D32_FLOAT_S8X24_UINT = 61, - SVGA3D_R32_FLOAT_X8X24 = 62, - SVGA3D_X32_G8X24_UINT = 63, - SVGA3D_R10G10B10A2_TYPELESS = 64, - SVGA3D_R10G10B10A2_UINT = 65, - SVGA3D_R11G11B10_FLOAT = 66, - SVGA3D_R8G8B8A8_TYPELESS = 67, - SVGA3D_R8G8B8A8_UNORM = 68, - SVGA3D_R8G8B8A8_UNORM_SRGB = 69, - SVGA3D_R8G8B8A8_UINT = 70, - SVGA3D_R8G8B8A8_SINT = 71, - SVGA3D_R16G16_TYPELESS = 72, - SVGA3D_R16G16_UINT = 73, - SVGA3D_R16G16_SINT = 74, - SVGA3D_R32_TYPELESS = 75, - SVGA3D_D32_FLOAT = 76, - SVGA3D_R32_UINT = 77, - SVGA3D_R32_SINT = 78, - SVGA3D_R24G8_TYPELESS = 79, - SVGA3D_D24_UNORM_S8_UINT = 80, - SVGA3D_R24_UNORM_X8 = 81, - SVGA3D_X24_G8_UINT = 82, - SVGA3D_R8G8_TYPELESS = 83, - SVGA3D_R8G8_UNORM = 84, - SVGA3D_R8G8_UINT = 85, - SVGA3D_R8G8_SINT = 86, - SVGA3D_R16_TYPELESS = 87, - SVGA3D_R16_UNORM = 88, - SVGA3D_R16_UINT = 89, - SVGA3D_R16_SNORM = 90, - SVGA3D_R16_SINT = 91, - SVGA3D_R8_TYPELESS = 92, - SVGA3D_R8_UNORM = 93, - SVGA3D_R8_UINT = 94, - SVGA3D_R8_SNORM = 95, - SVGA3D_R8_SINT = 96, - SVGA3D_P8 = 97, - SVGA3D_R9G9B9E5_SHAREDEXP = 98, - SVGA3D_R8G8_B8G8_UNORM = 99, - SVGA3D_G8R8_G8B8_UNORM = 100, - SVGA3D_BC1_TYPELESS = 101, - SVGA3D_BC1_UNORM_SRGB = 102, - SVGA3D_BC2_TYPELESS = 103, - SVGA3D_BC2_UNORM_SRGB = 104, - SVGA3D_BC3_TYPELESS = 105, - SVGA3D_BC3_UNORM_SRGB = 106, - SVGA3D_BC4_TYPELESS = 107, - SVGA3D_ATI1 = 108, /* DX9-specific BC4_UNORM */ - SVGA3D_BC4_SNORM = 109, - SVGA3D_BC5_TYPELESS = 110, - SVGA3D_ATI2 = 111, /* DX9-specific BC5_UNORM */ - SVGA3D_BC5_SNORM = 112, - SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113, - SVGA3D_B8G8R8A8_TYPELESS = 114, - SVGA3D_B8G8R8A8_UNORM_SRGB = 115, - SVGA3D_B8G8R8X8_TYPELESS = 116, - SVGA3D_B8G8R8X8_UNORM_SRGB = 117, + SVGA3D_R32G32B32A32_TYPELESS = 46, + SVGA3D_R32G32B32A32_UINT = 47, + SVGA3D_R32G32B32A32_SINT = 48, + SVGA3D_R32G32B32_TYPELESS = 49, + SVGA3D_R32G32B32_FLOAT = 50, + SVGA3D_R32G32B32_UINT = 51, + SVGA3D_R32G32B32_SINT = 52, + SVGA3D_R16G16B16A16_TYPELESS = 53, + SVGA3D_R16G16B16A16_UINT = 54, + SVGA3D_R16G16B16A16_SNORM = 55, + SVGA3D_R16G16B16A16_SINT = 56, + SVGA3D_R32G32_TYPELESS = 57, + SVGA3D_R32G32_UINT = 58, + SVGA3D_R32G32_SINT = 59, + SVGA3D_R32G8X24_TYPELESS = 60, + SVGA3D_D32_FLOAT_S8X24_UINT = 61, + SVGA3D_R32_FLOAT_X8X24 = 62, + SVGA3D_X32_G8X24_UINT = 63, + SVGA3D_R10G10B10A2_TYPELESS = 64, + SVGA3D_R10G10B10A2_UINT = 65, + SVGA3D_R11G11B10_FLOAT = 66, + SVGA3D_R8G8B8A8_TYPELESS = 67, + SVGA3D_R8G8B8A8_UNORM = 68, + SVGA3D_R8G8B8A8_UNORM_SRGB = 69, + SVGA3D_R8G8B8A8_UINT = 70, + SVGA3D_R8G8B8A8_SINT = 71, + SVGA3D_R16G16_TYPELESS = 72, + SVGA3D_R16G16_UINT = 73, + SVGA3D_R16G16_SINT = 74, + SVGA3D_R32_TYPELESS = 75, + SVGA3D_D32_FLOAT = 76, + SVGA3D_R32_UINT = 77, + SVGA3D_R32_SINT = 78, + SVGA3D_R24G8_TYPELESS = 79, + SVGA3D_D24_UNORM_S8_UINT = 80, + SVGA3D_R24_UNORM_X8 = 81, + SVGA3D_X24_G8_UINT = 82, + SVGA3D_R8G8_TYPELESS = 83, + SVGA3D_R8G8_UNORM = 84, + SVGA3D_R8G8_UINT = 85, + SVGA3D_R8G8_SINT = 86, + SVGA3D_R16_TYPELESS = 87, + SVGA3D_R16_UNORM = 88, + SVGA3D_R16_UINT = 89, + SVGA3D_R16_SNORM = 90, + SVGA3D_R16_SINT = 91, + SVGA3D_R8_TYPELESS = 92, + SVGA3D_R8_UNORM = 93, + SVGA3D_R8_UINT = 94, + SVGA3D_R8_SNORM = 95, + SVGA3D_R8_SINT = 96, + SVGA3D_P8 = 97, + SVGA3D_R9G9B9E5_SHAREDEXP = 98, + SVGA3D_R8G8_B8G8_UNORM = 99, + SVGA3D_G8R8_G8B8_UNORM = 100, + SVGA3D_BC1_TYPELESS = 101, + SVGA3D_BC1_UNORM_SRGB = 102, + SVGA3D_BC2_TYPELESS = 103, + SVGA3D_BC2_UNORM_SRGB = 104, + SVGA3D_BC3_TYPELESS = 105, + SVGA3D_BC3_UNORM_SRGB = 106, + SVGA3D_BC4_TYPELESS = 107, + SVGA3D_ATI1 = 108, + SVGA3D_BC4_SNORM = 109, + SVGA3D_BC5_TYPELESS = 110, + SVGA3D_ATI2 = 111, + SVGA3D_BC5_SNORM = 112, + SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113, + SVGA3D_B8G8R8A8_TYPELESS = 114, + SVGA3D_B8G8R8A8_UNORM_SRGB = 115, + SVGA3D_B8G8R8X8_TYPELESS = 116, + SVGA3D_B8G8R8X8_UNORM_SRGB = 117, - /* Advanced depth formats. */ - SVGA3D_Z_DF16 = 118, - SVGA3D_Z_DF24 = 119, - SVGA3D_Z_D24S8_INT = 120, + SVGA3D_Z_DF16 = 118, + SVGA3D_Z_DF24 = 119, + SVGA3D_Z_D24S8_INT = 120, - /* Planar video formats. */ - SVGA3D_YV12 = 121, + SVGA3D_YV12 = 121, - SVGA3D_R32G32B32A32_FLOAT = 122, - SVGA3D_R16G16B16A16_FLOAT = 123, - SVGA3D_R16G16B16A16_UNORM = 124, - SVGA3D_R32G32_FLOAT = 125, - SVGA3D_R10G10B10A2_UNORM = 126, - SVGA3D_R8G8B8A8_SNORM = 127, - SVGA3D_R16G16_FLOAT = 128, - SVGA3D_R16G16_UNORM = 129, - SVGA3D_R16G16_SNORM = 130, - SVGA3D_R32_FLOAT = 131, - SVGA3D_R8G8_SNORM = 132, - SVGA3D_R16_FLOAT = 133, - SVGA3D_D16_UNORM = 134, - SVGA3D_A8_UNORM = 135, - SVGA3D_BC1_UNORM = 136, - SVGA3D_BC2_UNORM = 137, - SVGA3D_BC3_UNORM = 138, - SVGA3D_B5G6R5_UNORM = 139, - SVGA3D_B5G5R5A1_UNORM = 140, - SVGA3D_B8G8R8A8_UNORM = 141, - SVGA3D_B8G8R8X8_UNORM = 142, - SVGA3D_BC4_UNORM = 143, - SVGA3D_BC5_UNORM = 144, - SVGA3D_B4G4R4A4_UNORM = 145, + SVGA3D_R32G32B32A32_FLOAT = 122, + SVGA3D_R16G16B16A16_FLOAT = 123, + SVGA3D_R16G16B16A16_UNORM = 124, + SVGA3D_R32G32_FLOAT = 125, + SVGA3D_R10G10B10A2_UNORM = 126, + SVGA3D_R8G8B8A8_SNORM = 127, + SVGA3D_R16G16_FLOAT = 128, + SVGA3D_R16G16_UNORM = 129, + SVGA3D_R16G16_SNORM = 130, + SVGA3D_R32_FLOAT = 131, + SVGA3D_R8G8_SNORM = 132, + SVGA3D_R16_FLOAT = 133, + SVGA3D_D16_UNORM = 134, + SVGA3D_A8_UNORM = 135, + SVGA3D_BC1_UNORM = 136, + SVGA3D_BC2_UNORM = 137, + SVGA3D_BC3_UNORM = 138, + SVGA3D_B5G6R5_UNORM = 139, + SVGA3D_B5G5R5A1_UNORM = 140, + SVGA3D_B8G8R8A8_UNORM = 141, + SVGA3D_B8G8R8X8_UNORM = 142, + SVGA3D_BC4_UNORM = 143, + SVGA3D_BC5_UNORM = 144, + SVGA3D_B4G4R4A4_UNORM = 145, + SVGA3D_BC6H_TYPELESS = 146, + SVGA3D_BC6H_UF16 = 147, + SVGA3D_BC6H_SF16 = 148, + SVGA3D_BC7_TYPELESS = 149, + SVGA3D_BC7_UNORM = 150, + SVGA3D_BC7_UNORM_SRGB = 151, - SVGA3D_BC6H_TYPELESS = 146, - SVGA3D_BC6H_UF16 = 147, - SVGA3D_BC6H_SF16 = 148, - SVGA3D_BC7_TYPELESS = 149, - SVGA3D_BC7_UNORM = 150, - SVGA3D_BC7_UNORM_SRGB = 151, - SVGA3D_AYUV = 152, - SVGA3D_R11G11B10_TYPELESS = 153, + SVGA3D_AYUV = 152, + + SVGA3D_R11G11B10_TYPELESS = 153, SVGA3D_FORMAT_MAX } SVGA3dSurfaceFormat; +#define SVGA3D_SURFACE_CUBEMAP (1 << 0) -#define SVGA3D_SURFACE_CUBEMAP (1 << 0) +#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1) +#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2) +#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3) +#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4) +#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5) +#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6) +#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7) +#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8) +#define SVGA3D_SURFACE_DEAD2 (CONST64U(1) << 9) +#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10) -/* - * HINT flags are not enforced by the device but are useful for - * performance. - */ -#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1) -#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2) -#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3) -#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4) -#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5) -#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6) -#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7) -#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8) -#define SVGA3D_SURFACE_DEAD2 (CONST64U(1) << 9) -#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10) +#define SVGA3D_SURFACE_DEAD1 (CONST64U(1) << 11) -#define SVGA3D_SURFACE_DEAD1 (CONST64U(1) << 11) +#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12) -/* - * Is this surface using a base-level pitch for it's mob backing? - * - * This flag is not intended to be set by guest-drivers, but is instead - * set by the device when the surface is bound to a mob with a specified - * pitch. - */ -#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12) +#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13) +#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14) +#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15) -#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13) -#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14) -#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15) +#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16) -/* - * Required to be set on a surface to bind it to a screen target. - */ -#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16) +#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17) -/* - * Align images in the guest-backing mob to 16-bytes. - */ -#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17) +#define SVGA3D_SURFACE_1D (CONST64U(1) << 18) +#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19) -#define SVGA3D_SURFACE_1D (CONST64U(1) << 18) -#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19) +#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20) +#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21) +#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22) +#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23) +#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24) +#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25) +#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26) -/* - * Bind flags. - * These are enforced for any surface defined with DefineGBSurface_v2. - */ -#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20) -#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21) -#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22) -#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23) -#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24) -#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25) -#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26) +#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27) +#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28) +#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29) -/* - * The STAGING flags notes that the surface will not be used directly by the - * drawing pipeline, i.e. that it will not be bound to any bind point. - * Staging surfaces may be used by copy operations to move data in and out - * of other surfaces. No bind flags may be set on surfaces with this flag. - * - * The HINT_INDIRECT_UPDATE flag suggests that the surface will receive - * updates indirectly, i.e. the surface will not be updated directly, but - * will receive copies from staging surfaces. - */ -#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27) -#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28) -#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29) +#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30) -/* - * Setting this flag allow this surface to be used with the - * SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for - * buffer surfaces, and no bind flags are allowed to be set on surfaces - * with this flag. - */ -#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30) +#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31) -#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31) +#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32) +#define SVGA3D_SURFACE_BIND_UAVIEW (CONST64U(1) << 33) -#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32) +#define SVGA3D_SURFACE_TRANSFER_TO_BUFFER (CONST64U(1) << 34) +#define SVGA3D_SURFACE_BIND_LOGICOPS (CONST64U(1) << 35) -#define SVGA3D_SURFACE_BIND_UAVIEW (CONST64U(1) << 33) +#define SVGA3D_SURFACE_BIND_RAW_VIEWS (CONST64U(1) << 36) +#define SVGA3D_SURFACE_BUFFER_STRUCTURED (CONST64U(1) << 37) +#define SVGA3D_SURFACE_DRAWINDIRECT_ARGS (CONST64U(1) << 38) +#define SVGA3D_SURFACE_RESOURCE_CLAMP (CONST64U(1) << 39) -#define SVGA3D_SURFACE_TRANSFER_TO_BUFFER (CONST64U(1) << 34) - -#define SVGA3D_SURFACE_BIND_LOGICOPS (CONST64U(1) << 35) - - -#define SVGA3D_SURFACE_BIND_RAW_VIEWS (CONST64U(1) << 36) -#define SVGA3D_SURFACE_BUFFER_STRUCTURED (CONST64U(1) << 37) - -#define SVGA3D_SURFACE_DRAWINDIRECT_ARGS (CONST64U(1) << 38) -#define SVGA3D_SURFACE_RESOURCE_CLAMP (CONST64U(1) << 39) - - -#define SVGA3D_SURFACE_STAGING_COPY (CONST64U(1) << 40) - -#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 44) +#define SVGA3D_SURFACE_STAGING_COPY (CONST64U(1) << 40) +#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 44) typedef uint32 SVGA3dSurface1Flags; typedef uint32 SVGA3dSurface2Flags; @@ -494,831 +396,690 @@ typedef uint64 SVGA3dSurfaceAllFlags; #define SVGA3D_SURFACE_FLAGS1_MASK ((uint64)MAX_UINT32) #define SVGA3D_SURFACE_FLAGS2_MASK (MAX_UINT64 & ~SVGA3D_SURFACE_FLAGS1_MASK) -#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_MOB_PITCH | \ - SVGA3D_SURFACE_SCREENTARGET | \ - SVGA3D_SURFACE_ALIGN16 | \ - SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ - SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ - SVGA3D_SURFACE_STAGING_UPLOAD | \ - SVGA3D_SURFACE_STAGING_DOWNLOAD | \ - SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \ - SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ - SVGA3D_SURFACE_MULTISAMPLE | \ - SVGA3D_SURFACE_BIND_UAVIEW | \ - SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ - SVGA3D_SURFACE_BIND_LOGICOPS | \ - SVGA3D_SURFACE_BIND_RAW_VIEWS | \ - SVGA3D_SURFACE_BUFFER_STRUCTURED | \ - SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ - SVGA3D_SURFACE_RESOURCE_CLAMP | \ - SVGA3D_SURFACE_STAGING_COPY | \ - SVGA3D_SURFACE_RESTRICT_UPDATE | \ - SVGA3D_SURFACE_BIND_TENSOR | \ - SVGA3D_SURFACE_LO_STAGING \ - ) +#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \ + (SVGA3D_SURFACE_MOB_PITCH | SVGA3D_SURFACE_SCREENTARGET | \ + SVGA3D_SURFACE_ALIGN16 | SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ + SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_STAGING_UPLOAD | \ + SVGA3D_SURFACE_STAGING_DOWNLOAD | SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \ + SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \ + SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ + SVGA3D_SURFACE_BIND_LOGICOPS | SVGA3D_SURFACE_BIND_RAW_VIEWS | \ + SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ + SVGA3D_SURFACE_RESOURCE_CLAMP | SVGA3D_SURFACE_STAGING_COPY | \ + SVGA3D_SURFACE_RESTRICT_UPDATE | SVGA3D_SURFACE_BIND_TENSOR | \ + SVGA3D_SURFACE_LO_STAGING) -#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_1D | \ - SVGA3D_SURFACE_MULTISAMPLE | \ - SVGA3D_SURFACE_STAGING_COPY \ - ) +#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \ + (SVGA3D_SURFACE_1D | SVGA3D_SURFACE_MULTISAMPLE | \ + SVGA3D_SURFACE_STAGING_COPY) -#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_CUBEMAP | \ - SVGA3D_SURFACE_AUTOGENMIPMAPS | \ - SVGA3D_SURFACE_VOLUME | \ - SVGA3D_SURFACE_1D | \ - SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \ - SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ - SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ - SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \ - SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ - SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ - SVGA3D_SURFACE_MULTISAMPLE | \ - SVGA3D_SURFACE_BIND_UAVIEW | \ - SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ - SVGA3D_SURFACE_BIND_RAW_VIEWS | \ - SVGA3D_SURFACE_BUFFER_STRUCTURED | \ - SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ - SVGA3D_SURFACE_RESOURCE_CLAMP | \ - SVGA3D_SURFACE_BIND_TENSOR \ - ) +#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \ + (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \ + SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \ + SVGA3D_SURFACE_BIND_VERTEX_BUFFER | SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ + SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \ + SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ + SVGA3D_SURFACE_MULTISAMPLE | SVGA3D_SURFACE_BIND_UAVIEW | \ + SVGA3D_SURFACE_TRANSFER_TO_BUFFER | SVGA3D_SURFACE_BIND_RAW_VIEWS | \ + SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ + SVGA3D_SURFACE_RESOURCE_CLAMP | SVGA3D_SURFACE_BIND_TENSOR) -#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_CUBEMAP | \ - SVGA3D_SURFACE_AUTOGENMIPMAPS | \ - SVGA3D_SURFACE_VOLUME | \ - SVGA3D_SURFACE_1D | \ - SVGA3D_SURFACE_MULTISAMPLE \ - ) +#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \ + (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \ + SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | SVGA3D_SURFACE_MULTISAMPLE) -#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_CUBEMAP | \ - SVGA3D_SURFACE_AUTOGENMIPMAPS | \ - SVGA3D_SURFACE_VOLUME | \ - SVGA3D_SURFACE_1D | \ - SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \ - SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ - SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ - SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \ - SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ - SVGA3D_SURFACE_INACTIVE | \ - SVGA3D_SURFACE_STAGING_UPLOAD | \ - SVGA3D_SURFACE_STAGING_DOWNLOAD | \ - SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \ - SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ - SVGA3D_SURFACE_MULTISAMPLE | \ - SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ - SVGA3D_SURFACE_BIND_RAW_VIEWS | \ - SVGA3D_SURFACE_BUFFER_STRUCTURED | \ - SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ - SVGA3D_SURFACE_RESOURCE_CLAMP | \ - SVGA3D_SURFACE_STAGING_COPY | \ - SVGA3D_SURFACE_BIND_TENSOR | \ - SVGA3D_SURFACE_LO_STAGING \ - ) +#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \ + (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \ + SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \ + SVGA3D_SURFACE_BIND_VERTEX_BUFFER | SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ + SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \ + SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_INACTIVE | \ + SVGA3D_SURFACE_STAGING_UPLOAD | SVGA3D_SURFACE_STAGING_DOWNLOAD | \ + SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \ + SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \ + SVGA3D_SURFACE_TRANSFER_TO_BUFFER | SVGA3D_SURFACE_BIND_RAW_VIEWS | \ + SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ + SVGA3D_SURFACE_RESOURCE_CLAMP | SVGA3D_SURFACE_STAGING_COPY | \ + SVGA3D_SURFACE_BIND_TENSOR | SVGA3D_SURFACE_LO_STAGING) -#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_CUBEMAP | \ - SVGA3D_SURFACE_AUTOGENMIPMAPS | \ - SVGA3D_SURFACE_VOLUME | \ - SVGA3D_SURFACE_1D | \ - SVGA3D_SURFACE_DEAD2 | \ - SVGA3D_SURFACE_ARRAY | \ - SVGA3D_SURFACE_MULTISAMPLE | \ - SVGA3D_SURFACE_MOB_PITCH | \ - SVGA3D_SURFACE_RESOURCE_CLAMP \ - ) +#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \ + (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \ + SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | SVGA3D_SURFACE_DEAD2 | \ + SVGA3D_SURFACE_ARRAY | SVGA3D_SURFACE_MULTISAMPLE | \ + SVGA3D_SURFACE_MOB_PITCH | SVGA3D_SURFACE_RESOURCE_CLAMP) -#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_CUBEMAP | \ - SVGA3D_SURFACE_AUTOGENMIPMAPS | \ - SVGA3D_SURFACE_VOLUME | \ - SVGA3D_SURFACE_1D | \ - SVGA3D_SURFACE_SCREENTARGET | \ - SVGA3D_SURFACE_MOB_PITCH | \ - SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ - SVGA3D_SURFACE_BIND_UAVIEW | \ - SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ - SVGA3D_SURFACE_BIND_LOGICOPS | \ - SVGA3D_SURFACE_BIND_RAW_VIEWS | \ - SVGA3D_SURFACE_BUFFER_STRUCTURED | \ - SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ - SVGA3D_SURFACE_STAGING_COPY \ - ) +#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \ + (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \ + SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | SVGA3D_SURFACE_SCREENTARGET | \ + SVGA3D_SURFACE_MOB_PITCH | SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ + SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ + SVGA3D_SURFACE_BIND_LOGICOPS | SVGA3D_SURFACE_BIND_RAW_VIEWS | \ + SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ + SVGA3D_SURFACE_STAGING_COPY) -#define SVGA3D_SURFACE_DX_ONLY_MASK \ - ( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ - SVGA3D_SURFACE_STAGING_UPLOAD | \ - SVGA3D_SURFACE_STAGING_DOWNLOAD | \ - SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ - SVGA3D_SURFACE_TRANSFER_TO_BUFFER \ - ) +#define SVGA3D_SURFACE_DX_ONLY_MASK \ + (SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_STAGING_UPLOAD | \ + SVGA3D_SURFACE_STAGING_DOWNLOAD | SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ + SVGA3D_SURFACE_TRANSFER_TO_BUFFER) -#define SVGA3D_SURFACE_ANY_STAGING_MASK \ - ( SVGA3D_SURFACE_STAGING_UPLOAD | \ - SVGA3D_SURFACE_STAGING_DOWNLOAD | \ - SVGA3D_SURFACE_STAGING_COPY | \ - SVGA3D_SURFACE_LO_STAGING \ - ) +#define SVGA3D_SURFACE_ANY_STAGING_MASK \ + (SVGA3D_SURFACE_STAGING_UPLOAD | SVGA3D_SURFACE_STAGING_DOWNLOAD | \ + SVGA3D_SURFACE_STAGING_COPY | SVGA3D_SURFACE_LO_STAGING) -#define SVGA3D_SURFACE_ANY_NONHINT_STAGING_MASK \ - (SVGA3D_SURFACE_ANY_STAGING_MASK & \ - ~( \ - SVGA3D_SURFACE_LO_STAGING \ - )) +#define SVGA3D_SURFACE_ANY_NONHINT_STAGING_MASK \ + (SVGA3D_SURFACE_ANY_STAGING_MASK & ~(SVGA3D_SURFACE_LO_STAGING)) -#define SVGA3D_SURFACE_BIND_MASK \ - ( SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \ - SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ - SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ - SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \ - SVGA3D_SURFACE_BIND_RENDER_TARGET | \ - SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \ - SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ - SVGA3D_SURFACE_BIND_UAVIEW | \ - SVGA3D_SURFACE_BIND_LOGICOPS | \ - SVGA3D_SURFACE_BIND_RAW_VIEWS | \ - SVGA3D_SURFACE_BIND_TENSOR \ - ) +#define SVGA3D_SURFACE_BIND_MASK \ + (SVGA3D_SURFACE_BIND_VERTEX_BUFFER | SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ + SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ + SVGA3D_SURFACE_BIND_SHADER_RESOURCE | SVGA3D_SURFACE_BIND_RENDER_TARGET | \ + SVGA3D_SURFACE_BIND_DEPTH_STENCIL | SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ + SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_BIND_LOGICOPS | \ + SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BIND_TENSOR) -#define SVGA3D_SURFACE_STAGING_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_BIND_MASK | \ - SVGA3D_SURFACE_AUTOGENMIPMAPS | \ - SVGA3D_SURFACE_SCREENTARGET | \ - SVGA3D_SURFACE_HINT_RENDERTARGET | \ - SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \ - SVGA3D_SURFACE_MULTISAMPLE | \ - SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ - SVGA3D_SURFACE_RESOURCE_CLAMP | \ - SVGA3D_SURFACE_BIND_TENSOR \ - ) +#define SVGA3D_SURFACE_STAGING_DISALLOWED_MASK \ + (SVGA3D_SURFACE_BIND_MASK | SVGA3D_SURFACE_AUTOGENMIPMAPS | \ + SVGA3D_SURFACE_SCREENTARGET | SVGA3D_SURFACE_HINT_RENDERTARGET | \ + SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | SVGA3D_SURFACE_MULTISAMPLE | \ + SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \ + SVGA3D_SURFACE_BIND_TENSOR) -#define SVGA3D_SURFACE_STAGING_COPY_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_STAGING_DISALLOWED_MASK | \ - SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ - SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \ - ) +#define SVGA3D_SURFACE_STAGING_COPY_DISALLOWED_MASK \ + (SVGA3D_SURFACE_STAGING_DISALLOWED_MASK | \ + SVGA3D_SURFACE_TRANSFER_TO_BUFFER | SVGA3D_SURFACE_TRANSFER_FROM_BUFFER) -#define SVGA3D_SURFACE_LOGICOPS_DISALLOWED_MASK \ - ( SVGA3D_SURFACE_CUBEMAP | \ - SVGA3D_SURFACE_DEAD2 | \ - SVGA3D_SURFACE_AUTOGENMIPMAPS | \ - SVGA3D_SURFACE_VOLUME | \ - SVGA3D_SURFACE_1D | \ - SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \ - SVGA3D_SURFACE_BIND_INDEX_BUFFER | \ - SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ - SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \ - SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ - SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \ - SVGA3D_SURFACE_MULTISAMPLE | \ - SVGA3D_SURFACE_BIND_UAVIEW | \ - SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ - SVGA3D_SURFACE_BIND_RAW_VIEWS | \ - SVGA3D_SURFACE_BUFFER_STRUCTURED | \ - SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ - SVGA3D_SURFACE_RESOURCE_CLAMP | \ - SVGA3D_SURFACE_STAGING_COPY \ - ) +#define SVGA3D_SURFACE_LOGICOPS_DISALLOWED_MASK \ + (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_DEAD2 | \ + SVGA3D_SURFACE_AUTOGENMIPMAPS | SVGA3D_SURFACE_VOLUME | \ + SVGA3D_SURFACE_1D | SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \ + SVGA3D_SURFACE_BIND_INDEX_BUFFER | SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \ + SVGA3D_SURFACE_BIND_DEPTH_STENCIL | SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \ + SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \ + SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \ + SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \ + SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \ + SVGA3D_SURFACE_STAGING_COPY) -#define SVGA3D_SURFACE_SM5_MASK \ - ( SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \ - SVGA3D_SURFACE_BUFFER_STRUCTURED | \ - SVGA3D_SURFACE_BIND_RAW_VIEWS | \ - SVGA3D_SURFACE_BIND_UAVIEW | \ - SVGA3D_SURFACE_RESOURCE_CLAMP \ - ) +#define SVGA3D_SURFACE_SM5_MASK \ + (SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \ + SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BIND_UAVIEW | \ + SVGA3D_SURFACE_RESOURCE_CLAMP) #define SVGA3D_BUFFER_STRUCTURED_STRIDE_MAX 2048 - - typedef enum { - SVGA3DFORMAT_OP_TEXTURE = 0x00000001, - SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002, - SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004, - SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008, - SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010, - SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040, - SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080, + SVGA3DFORMAT_OP_TEXTURE = 0x00000001, + SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002, + SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004, + SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008, + SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010, + SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040, + SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080, + SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100, - SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100, + SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400, + SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800, - SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400, + SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000, + SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000, - SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800, + SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000, + SVGA3DFORMAT_OP_SRGBREAD = 0x00008000, - SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000, + SVGA3DFORMAT_OP_BUMPMAP = 0x00010000, + SVGA3DFORMAT_OP_DMAP = 0x00020000, - SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000, + SVGA3DFORMAT_OP_NOFILTER = 0x00040000, + SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000, - SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000, + SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000, + SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000, - SVGA3DFORMAT_OP_SRGBREAD = 0x00008000, + SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000, + SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000, - SVGA3DFORMAT_OP_BUMPMAP = 0x00010000, - - - SVGA3DFORMAT_OP_DMAP = 0x00020000, - - - SVGA3DFORMAT_OP_NOFILTER = 0x00040000, - - - SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000, - - - SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000, - - - SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000, - - - SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000, - - - SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000, - - - SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000 + SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000 } SVGA3dFormatOp; -#define SVGA3D_FORMAT_POSITIVE \ - (SVGA3DFORMAT_OP_TEXTURE | \ - SVGA3DFORMAT_OP_VOLUMETEXTURE | \ - SVGA3DFORMAT_OP_CUBETEXTURE | \ - SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \ - SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | \ - SVGA3DFORMAT_OP_ZSTENCIL | \ - SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \ - SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \ - SVGA3DFORMAT_OP_DISPLAYMODE | \ - SVGA3DFORMAT_OP_3DACCELERATION | \ - SVGA3DFORMAT_OP_PIXELSIZE | \ - SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \ - SVGA3DFORMAT_OP_OFFSCREENPLAIN | \ - SVGA3DFORMAT_OP_SRGBREAD | \ - SVGA3DFORMAT_OP_BUMPMAP | \ - SVGA3DFORMAT_OP_DMAP | \ - SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | \ - SVGA3DFORMAT_OP_SRGBWRITE | \ - SVGA3DFORMAT_OP_AUTOGENMIPMAP | \ - SVGA3DFORMAT_OP_VERTEXTEXTURE) +#define SVGA3D_FORMAT_POSITIVE \ + (SVGA3DFORMAT_OP_TEXTURE | SVGA3DFORMAT_OP_VOLUMETEXTURE | \ + SVGA3DFORMAT_OP_CUBETEXTURE | SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \ + SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | SVGA3DFORMAT_OP_ZSTENCIL | \ + SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \ + SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \ + SVGA3DFORMAT_OP_DISPLAYMODE | SVGA3DFORMAT_OP_3DACCELERATION | \ + SVGA3DFORMAT_OP_PIXELSIZE | SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \ + SVGA3DFORMAT_OP_OFFSCREENPLAIN | SVGA3DFORMAT_OP_SRGBREAD | \ + SVGA3DFORMAT_OP_BUMPMAP | SVGA3DFORMAT_OP_DMAP | \ + SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | SVGA3DFORMAT_OP_SRGBWRITE | \ + SVGA3DFORMAT_OP_AUTOGENMIPMAP | SVGA3DFORMAT_OP_VERTEXTEXTURE) -#define SVGA3D_FORMAT_NEGATIVE \ - (SVGA3DFORMAT_OP_NOFILTER | \ - SVGA3DFORMAT_OP_NOALPHABLEND | \ +#define SVGA3D_FORMAT_NEGATIVE \ + (SVGA3DFORMAT_OP_NOFILTER | SVGA3DFORMAT_OP_NOALPHABLEND | \ SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP) - typedef union { uint32 value; struct { - uint32 texture : 1; - uint32 volumeTexture : 1; - uint32 cubeTexture : 1; - uint32 offscreenRenderTarget : 1; + uint32 texture : 1; + uint32 volumeTexture : 1; + uint32 cubeTexture : 1; + uint32 offscreenRenderTarget : 1; uint32 sameFormatRenderTarget : 1; - uint32 unknown1 : 1; - uint32 zStencil : 1; + uint32 unknown1 : 1; + uint32 zStencil : 1; uint32 zStencilArbitraryDepth : 1; - uint32 sameFormatUpToAlpha : 1; - uint32 unknown2 : 1; - uint32 displayMode : 1; - uint32 acceleration3d : 1; - uint32 pixelSize : 1; - uint32 convertToARGB : 1; - uint32 offscreenPlain : 1; - uint32 sRGBRead : 1; - uint32 bumpMap : 1; - uint32 dmap : 1; - uint32 noFilter : 1; - uint32 memberOfGroupARGB : 1; - uint32 sRGBWrite : 1; - uint32 noAlphaBlend : 1; - uint32 autoGenMipMap : 1; - uint32 vertexTexture : 1; - uint32 noTexCoordWrapNorMip : 1; + uint32 sameFormatUpToAlpha : 1; + uint32 unknown2 : 1; + uint32 displayMode : 1; + uint32 acceleration3d : 1; + uint32 pixelSize : 1; + uint32 convertToARGB : 1; + uint32 offscreenPlain : 1; + uint32 sRGBRead : 1; + uint32 bumpMap : 1; + uint32 dmap : 1; + uint32 noFilter : 1; + uint32 memberOfGroupARGB : 1; + uint32 sRGBWrite : 1; + uint32 noAlphaBlend : 1; + uint32 autoGenMipMap : 1; + uint32 vertexTexture : 1; + uint32 noTexCoordWrapNorMip : 1; }; } SVGA3dSurfaceFormatCaps; - - typedef enum { - SVGA3D_RS_INVALID = 0, - SVGA3D_RS_MIN = 1, - SVGA3D_RS_ZENABLE = 1, - SVGA3D_RS_ZWRITEENABLE = 2, - SVGA3D_RS_ALPHATESTENABLE = 3, - SVGA3D_RS_DITHERENABLE = 4, - SVGA3D_RS_BLENDENABLE = 5, - SVGA3D_RS_FOGENABLE = 6, - SVGA3D_RS_SPECULARENABLE = 7, - SVGA3D_RS_STENCILENABLE = 8, - SVGA3D_RS_LIGHTINGENABLE = 9, - SVGA3D_RS_NORMALIZENORMALS = 10, - SVGA3D_RS_POINTSPRITEENABLE = 11, - SVGA3D_RS_POINTSCALEENABLE = 12, - SVGA3D_RS_STENCILREF = 13, - SVGA3D_RS_STENCILMASK = 14, - SVGA3D_RS_STENCILWRITEMASK = 15, - SVGA3D_RS_FOGSTART = 16, - SVGA3D_RS_FOGEND = 17, - SVGA3D_RS_FOGDENSITY = 18, - SVGA3D_RS_POINTSIZE = 19, - SVGA3D_RS_POINTSIZEMIN = 20, - SVGA3D_RS_POINTSIZEMAX = 21, - SVGA3D_RS_POINTSCALE_A = 22, - SVGA3D_RS_POINTSCALE_B = 23, - SVGA3D_RS_POINTSCALE_C = 24, - SVGA3D_RS_FOGCOLOR = 25, - SVGA3D_RS_AMBIENT = 26, - SVGA3D_RS_CLIPPLANEENABLE = 27, - SVGA3D_RS_FOGMODE = 28, - SVGA3D_RS_FILLMODE = 29, - SVGA3D_RS_SHADEMODE = 30, - SVGA3D_RS_LINEPATTERN = 31, - SVGA3D_RS_SRCBLEND = 32, - SVGA3D_RS_DSTBLEND = 33, - SVGA3D_RS_BLENDEQUATION = 34, - SVGA3D_RS_CULLMODE = 35, - SVGA3D_RS_ZFUNC = 36, - SVGA3D_RS_ALPHAFUNC = 37, - SVGA3D_RS_STENCILFUNC = 38, - SVGA3D_RS_STENCILFAIL = 39, - SVGA3D_RS_STENCILZFAIL = 40, - SVGA3D_RS_STENCILPASS = 41, - SVGA3D_RS_ALPHAREF = 42, - SVGA3D_RS_FRONTWINDING = 43, - SVGA3D_RS_COORDINATETYPE = 44, - SVGA3D_RS_ZBIAS = 45, - SVGA3D_RS_RANGEFOGENABLE = 46, - SVGA3D_RS_COLORWRITEENABLE = 47, - SVGA3D_RS_VERTEXMATERIALENABLE = 48, - SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, - SVGA3D_RS_SPECULARMATERIALSOURCE = 50, - SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, - SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, - SVGA3D_RS_TEXTUREFACTOR = 53, - SVGA3D_RS_LOCALVIEWER = 54, - SVGA3D_RS_SCISSORTESTENABLE = 55, - SVGA3D_RS_BLENDCOLOR = 56, - SVGA3D_RS_STENCILENABLE2SIDED = 57, - SVGA3D_RS_CCWSTENCILFUNC = 58, - SVGA3D_RS_CCWSTENCILFAIL = 59, - SVGA3D_RS_CCWSTENCILZFAIL = 60, - SVGA3D_RS_CCWSTENCILPASS = 61, - SVGA3D_RS_VERTEXBLEND = 62, - SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, - SVGA3D_RS_DEPTHBIAS = 64, + SVGA3D_RS_INVALID = 0, + SVGA3D_RS_MIN = 1, + SVGA3D_RS_ZENABLE = 1, + SVGA3D_RS_ZWRITEENABLE = 2, + SVGA3D_RS_ALPHATESTENABLE = 3, + SVGA3D_RS_DITHERENABLE = 4, + SVGA3D_RS_BLENDENABLE = 5, + SVGA3D_RS_FOGENABLE = 6, + SVGA3D_RS_SPECULARENABLE = 7, + SVGA3D_RS_STENCILENABLE = 8, + SVGA3D_RS_LIGHTINGENABLE = 9, + SVGA3D_RS_NORMALIZENORMALS = 10, + SVGA3D_RS_POINTSPRITEENABLE = 11, + SVGA3D_RS_POINTSCALEENABLE = 12, + SVGA3D_RS_STENCILREF = 13, + SVGA3D_RS_STENCILMASK = 14, + SVGA3D_RS_STENCILWRITEMASK = 15, + SVGA3D_RS_FOGSTART = 16, + SVGA3D_RS_FOGEND = 17, + SVGA3D_RS_FOGDENSITY = 18, + SVGA3D_RS_POINTSIZE = 19, + SVGA3D_RS_POINTSIZEMIN = 20, + SVGA3D_RS_POINTSIZEMAX = 21, + SVGA3D_RS_POINTSCALE_A = 22, + SVGA3D_RS_POINTSCALE_B = 23, + SVGA3D_RS_POINTSCALE_C = 24, + SVGA3D_RS_FOGCOLOR = 25, + SVGA3D_RS_AMBIENT = 26, + SVGA3D_RS_CLIPPLANEENABLE = 27, + SVGA3D_RS_FOGMODE = 28, + SVGA3D_RS_FILLMODE = 29, + SVGA3D_RS_SHADEMODE = 30, + SVGA3D_RS_LINEPATTERN = 31, + SVGA3D_RS_SRCBLEND = 32, + SVGA3D_RS_DSTBLEND = 33, + SVGA3D_RS_BLENDEQUATION = 34, + SVGA3D_RS_CULLMODE = 35, + SVGA3D_RS_ZFUNC = 36, + SVGA3D_RS_ALPHAFUNC = 37, + SVGA3D_RS_STENCILFUNC = 38, + SVGA3D_RS_STENCILFAIL = 39, + SVGA3D_RS_STENCILZFAIL = 40, + SVGA3D_RS_STENCILPASS = 41, + SVGA3D_RS_ALPHAREF = 42, + SVGA3D_RS_FRONTWINDING = 43, + SVGA3D_RS_COORDINATETYPE = 44, + SVGA3D_RS_ZBIAS = 45, + SVGA3D_RS_RANGEFOGENABLE = 46, + SVGA3D_RS_COLORWRITEENABLE = 47, + SVGA3D_RS_VERTEXMATERIALENABLE = 48, + SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, + SVGA3D_RS_SPECULARMATERIALSOURCE = 50, + SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, + SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, + SVGA3D_RS_TEXTUREFACTOR = 53, + SVGA3D_RS_LOCALVIEWER = 54, + SVGA3D_RS_SCISSORTESTENABLE = 55, + SVGA3D_RS_BLENDCOLOR = 56, + SVGA3D_RS_STENCILENABLE2SIDED = 57, + SVGA3D_RS_CCWSTENCILFUNC = 58, + SVGA3D_RS_CCWSTENCILFAIL = 59, + SVGA3D_RS_CCWSTENCILZFAIL = 60, + SVGA3D_RS_CCWSTENCILPASS = 61, + SVGA3D_RS_VERTEXBLEND = 62, + SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, + SVGA3D_RS_DEPTHBIAS = 64, - - - - SVGA3D_RS_OUTPUTGAMMA = 65, - SVGA3D_RS_ZVISIBLE = 66, - SVGA3D_RS_LASTPIXEL = 67, - SVGA3D_RS_CLIPPING = 68, - SVGA3D_RS_WRAP0 = 69, - SVGA3D_RS_WRAP1 = 70, - SVGA3D_RS_WRAP2 = 71, - SVGA3D_RS_WRAP3 = 72, - SVGA3D_RS_WRAP4 = 73, - SVGA3D_RS_WRAP5 = 74, - SVGA3D_RS_WRAP6 = 75, - SVGA3D_RS_WRAP7 = 76, - SVGA3D_RS_WRAP8 = 77, - SVGA3D_RS_WRAP9 = 78, - SVGA3D_RS_WRAP10 = 79, - SVGA3D_RS_WRAP11 = 80, - SVGA3D_RS_WRAP12 = 81, - SVGA3D_RS_WRAP13 = 82, - SVGA3D_RS_WRAP14 = 83, - SVGA3D_RS_WRAP15 = 84, - SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, - SVGA3D_RS_MULTISAMPLEMASK = 86, - SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, - SVGA3D_RS_TWEENFACTOR = 88, - SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, - SVGA3D_RS_COLORWRITEENABLE1 = 90, - SVGA3D_RS_COLORWRITEENABLE2 = 91, - SVGA3D_RS_COLORWRITEENABLE3 = 92, - SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, - SVGA3D_RS_SRCBLENDALPHA = 94, - SVGA3D_RS_DSTBLENDALPHA = 95, - SVGA3D_RS_BLENDEQUATIONALPHA = 96, - SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, - SVGA3D_RS_LINEWIDTH = 98, + SVGA3D_RS_OUTPUTGAMMA = 65, + SVGA3D_RS_ZVISIBLE = 66, + SVGA3D_RS_LASTPIXEL = 67, + SVGA3D_RS_CLIPPING = 68, + SVGA3D_RS_WRAP0 = 69, + SVGA3D_RS_WRAP1 = 70, + SVGA3D_RS_WRAP2 = 71, + SVGA3D_RS_WRAP3 = 72, + SVGA3D_RS_WRAP4 = 73, + SVGA3D_RS_WRAP5 = 74, + SVGA3D_RS_WRAP6 = 75, + SVGA3D_RS_WRAP7 = 76, + SVGA3D_RS_WRAP8 = 77, + SVGA3D_RS_WRAP9 = 78, + SVGA3D_RS_WRAP10 = 79, + SVGA3D_RS_WRAP11 = 80, + SVGA3D_RS_WRAP12 = 81, + SVGA3D_RS_WRAP13 = 82, + SVGA3D_RS_WRAP14 = 83, + SVGA3D_RS_WRAP15 = 84, + SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, + SVGA3D_RS_MULTISAMPLEMASK = 86, + SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, + SVGA3D_RS_TWEENFACTOR = 88, + SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, + SVGA3D_RS_COLORWRITEENABLE1 = 90, + SVGA3D_RS_COLORWRITEENABLE2 = 91, + SVGA3D_RS_COLORWRITEENABLE3 = 92, + SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, + SVGA3D_RS_SRCBLENDALPHA = 94, + SVGA3D_RS_DSTBLENDALPHA = 95, + SVGA3D_RS_BLENDEQUATIONALPHA = 96, + SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, + SVGA3D_RS_LINEWIDTH = 98, SVGA3D_RS_MAX } SVGA3dRenderStateName; typedef enum { - SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0, - SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1, - SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2, + SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0, + SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1, + SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2, SVGA3D_TRANSPARENCYANTIALIAS_MAX } SVGA3dTransparencyAntialiasType; typedef enum { - SVGA3D_VERTEXMATERIAL_NONE = 0, - SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, + SVGA3D_VERTEXMATERIAL_NONE = 0, + SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, SVGA3D_VERTEXMATERIAL_SPECULAR = 2, - SVGA3D_VERTEXMATERIAL_MAX = 3, + SVGA3D_VERTEXMATERIAL_MAX = 3, } SVGA3dVertexMaterial; typedef enum { SVGA3D_FILLMODE_INVALID = 0, - SVGA3D_FILLMODE_MIN = 1, - SVGA3D_FILLMODE_POINT = 1, - SVGA3D_FILLMODE_LINE = 2, - SVGA3D_FILLMODE_FILL = 3, + SVGA3D_FILLMODE_MIN = 1, + SVGA3D_FILLMODE_POINT = 1, + SVGA3D_FILLMODE_LINE = 2, + SVGA3D_FILLMODE_FILL = 3, SVGA3D_FILLMODE_MAX } SVGA3dFillModeType; - -typedef -#include "vmware_pack_begin.h" -union { +#pragma pack(push, 1) +typedef union { struct { - uint16 mode; /* SVGA3dFillModeType */ - uint16 face; /* SVGA3dFace */ + uint16 mode; + uint16 face; }; uint32 uintValue; -} -#include "vmware_pack_end.h" -SVGA3dFillMode; +} SVGA3dFillMode; +#pragma pack(pop) typedef enum { SVGA3D_SHADEMODE_INVALID = 0, - SVGA3D_SHADEMODE_FLAT = 1, - SVGA3D_SHADEMODE_SMOOTH = 2, - SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */ + SVGA3D_SHADEMODE_FLAT = 1, + SVGA3D_SHADEMODE_SMOOTH = 2, + SVGA3D_SHADEMODE_PHONG = 3, SVGA3D_SHADEMODE_MAX } SVGA3dShadeMode; -typedef -#include "vmware_pack_begin.h" -union { +#pragma pack(push, 1) +typedef union { struct { uint16 repeat; uint16 pattern; }; uint32 uintValue; -} -#include "vmware_pack_end.h" -SVGA3dLinePattern; +} SVGA3dLinePattern; +#pragma pack(pop) typedef enum { - SVGA3D_BLENDOP_INVALID = 0, - SVGA3D_BLENDOP_MIN = 1, - SVGA3D_BLENDOP_ZERO = 1, - SVGA3D_BLENDOP_ONE = 2, - SVGA3D_BLENDOP_SRCCOLOR = 3, - SVGA3D_BLENDOP_INVSRCCOLOR = 4, - SVGA3D_BLENDOP_SRCALPHA = 5, - SVGA3D_BLENDOP_INVSRCALPHA = 6, - SVGA3D_BLENDOP_DESTALPHA = 7, - SVGA3D_BLENDOP_INVDESTALPHA = 8, - SVGA3D_BLENDOP_DESTCOLOR = 9, - SVGA3D_BLENDOP_INVDESTCOLOR = 10, - SVGA3D_BLENDOP_SRCALPHASAT = 11, - SVGA3D_BLENDOP_BLENDFACTOR = 12, - SVGA3D_BLENDOP_INVBLENDFACTOR = 13, - SVGA3D_BLENDOP_SRC1COLOR = 14, - SVGA3D_BLENDOP_INVSRC1COLOR = 15, - SVGA3D_BLENDOP_SRC1ALPHA = 16, - SVGA3D_BLENDOP_INVSRC1ALPHA = 17, - SVGA3D_BLENDOP_BLENDFACTORALPHA = 18, + SVGA3D_BLENDOP_INVALID = 0, + SVGA3D_BLENDOP_MIN = 1, + SVGA3D_BLENDOP_ZERO = 1, + SVGA3D_BLENDOP_ONE = 2, + SVGA3D_BLENDOP_SRCCOLOR = 3, + SVGA3D_BLENDOP_INVSRCCOLOR = 4, + SVGA3D_BLENDOP_SRCALPHA = 5, + SVGA3D_BLENDOP_INVSRCALPHA = 6, + SVGA3D_BLENDOP_DESTALPHA = 7, + SVGA3D_BLENDOP_INVDESTALPHA = 8, + SVGA3D_BLENDOP_DESTCOLOR = 9, + SVGA3D_BLENDOP_INVDESTCOLOR = 10, + SVGA3D_BLENDOP_SRCALPHASAT = 11, + SVGA3D_BLENDOP_BLENDFACTOR = 12, + SVGA3D_BLENDOP_INVBLENDFACTOR = 13, + SVGA3D_BLENDOP_SRC1COLOR = 14, + SVGA3D_BLENDOP_INVSRC1COLOR = 15, + SVGA3D_BLENDOP_SRC1ALPHA = 16, + SVGA3D_BLENDOP_INVSRC1ALPHA = 17, + SVGA3D_BLENDOP_BLENDFACTORALPHA = 18, SVGA3D_BLENDOP_INVBLENDFACTORALPHA = 19, SVGA3D_BLENDOP_MAX } SVGA3dBlendOp; typedef enum { - SVGA3D_BLENDEQ_INVALID = 0, - SVGA3D_BLENDEQ_MIN = 1, - SVGA3D_BLENDEQ_ADD = 1, - SVGA3D_BLENDEQ_SUBTRACT = 2, - SVGA3D_BLENDEQ_REVSUBTRACT = 3, - SVGA3D_BLENDEQ_MINIMUM = 4, - SVGA3D_BLENDEQ_MAXIMUM = 5, + SVGA3D_BLENDEQ_INVALID = 0, + SVGA3D_BLENDEQ_MIN = 1, + SVGA3D_BLENDEQ_ADD = 1, + SVGA3D_BLENDEQ_SUBTRACT = 2, + SVGA3D_BLENDEQ_REVSUBTRACT = 3, + SVGA3D_BLENDEQ_MINIMUM = 4, + SVGA3D_BLENDEQ_MAXIMUM = 5, SVGA3D_BLENDEQ_MAX } SVGA3dBlendEquation; typedef enum { - SVGA3D_DX11_LOGICOP_MIN = 0, - SVGA3D_DX11_LOGICOP_CLEAR = 0, - SVGA3D_DX11_LOGICOP_SET = 1, - SVGA3D_DX11_LOGICOP_COPY = 2, + SVGA3D_DX11_LOGICOP_MIN = 0, + SVGA3D_DX11_LOGICOP_CLEAR = 0, + SVGA3D_DX11_LOGICOP_SET = 1, + SVGA3D_DX11_LOGICOP_COPY = 2, SVGA3D_DX11_LOGICOP_COPY_INVERTED = 3, - SVGA3D_DX11_LOGICOP_NOOP = 4, - SVGA3D_DX11_LOGICOP_INVERT = 5, - SVGA3D_DX11_LOGICOP_AND = 6, - SVGA3D_DX11_LOGICOP_NAND = 7, - SVGA3D_DX11_LOGICOP_OR = 8, - SVGA3D_DX11_LOGICOP_NOR = 9, - SVGA3D_DX11_LOGICOP_XOR = 10, - SVGA3D_DX11_LOGICOP_EQUIV = 11, - SVGA3D_DX11_LOGICOP_AND_REVERSE = 12, - SVGA3D_DX11_LOGICOP_AND_INVERTED = 13, - SVGA3D_DX11_LOGICOP_OR_REVERSE = 14, - SVGA3D_DX11_LOGICOP_OR_INVERTED = 15, + SVGA3D_DX11_LOGICOP_NOOP = 4, + SVGA3D_DX11_LOGICOP_INVERT = 5, + SVGA3D_DX11_LOGICOP_AND = 6, + SVGA3D_DX11_LOGICOP_NAND = 7, + SVGA3D_DX11_LOGICOP_OR = 8, + SVGA3D_DX11_LOGICOP_NOR = 9, + SVGA3D_DX11_LOGICOP_XOR = 10, + SVGA3D_DX11_LOGICOP_EQUIV = 11, + SVGA3D_DX11_LOGICOP_AND_REVERSE = 12, + SVGA3D_DX11_LOGICOP_AND_INVERTED = 13, + SVGA3D_DX11_LOGICOP_OR_REVERSE = 14, + SVGA3D_DX11_LOGICOP_OR_INVERTED = 15, SVGA3D_DX11_LOGICOP_MAX } SVGA3dDX11LogicOp; typedef enum { SVGA3D_FRONTWINDING_INVALID = 0, - SVGA3D_FRONTWINDING_CW = 1, - SVGA3D_FRONTWINDING_CCW = 2, + SVGA3D_FRONTWINDING_CW = 1, + SVGA3D_FRONTWINDING_MIN = 1, + SVGA3D_FRONTWINDING_CCW = 2, SVGA3D_FRONTWINDING_MAX } SVGA3dFrontWinding; typedef enum { - SVGA3D_FACE_INVALID = 0, - SVGA3D_FACE_NONE = 1, - SVGA3D_FACE_MIN = 1, - SVGA3D_FACE_FRONT = 2, - SVGA3D_FACE_BACK = 3, + SVGA3D_FACE_INVALID = 0, + SVGA3D_FACE_NONE = 1, + SVGA3D_FACE_MIN = 1, + SVGA3D_FACE_FRONT = 2, + SVGA3D_FACE_BACK = 3, SVGA3D_FACE_FRONT_BACK = 4, SVGA3D_FACE_MAX } SVGA3dFace; - - typedef enum { - SVGA3D_CMP_INVALID = 0, - SVGA3D_CMP_NEVER = 1, - SVGA3D_CMP_LESS = 2, - SVGA3D_CMP_EQUAL = 3, - SVGA3D_CMP_LESSEQUAL = 4, - SVGA3D_CMP_GREATER = 5, - SVGA3D_CMP_NOTEQUAL = 6, - SVGA3D_CMP_GREATEREQUAL = 7, - SVGA3D_CMP_ALWAYS = 8, + SVGA3D_CMP_INVALID = 0, + SVGA3D_CMP_NEVER = 1, + SVGA3D_CMP_LESS = 2, + SVGA3D_CMP_EQUAL = 3, + SVGA3D_CMP_LESSEQUAL = 4, + SVGA3D_CMP_GREATER = 5, + SVGA3D_CMP_NOTEQUAL = 6, + SVGA3D_CMP_GREATEREQUAL = 7, + SVGA3D_CMP_ALWAYS = 8, SVGA3D_CMP_MAX } SVGA3dCmpFunc; - typedef enum { - SVGA3D_FOGFUNC_INVALID = 0, - SVGA3D_FOGFUNC_EXP = 1, - SVGA3D_FOGFUNC_EXP2 = 2, - SVGA3D_FOGFUNC_LINEAR = 3, - SVGA3D_FOGFUNC_PER_VERTEX = 4 + SVGA3D_FOGFUNC_INVALID = 0, + SVGA3D_FOGFUNC_EXP = 1, + SVGA3D_FOGFUNC_EXP2 = 2, + SVGA3D_FOGFUNC_LINEAR = 3, + SVGA3D_FOGFUNC_PER_VERTEX = 4 } SVGA3dFogFunction; - typedef enum { - SVGA3D_FOGTYPE_INVALID = 0, - SVGA3D_FOGTYPE_VERTEX = 1, - SVGA3D_FOGTYPE_PIXEL = 2, - SVGA3D_FOGTYPE_MAX = 3 + SVGA3D_FOGTYPE_INVALID = 0, + SVGA3D_FOGTYPE_VERTEX = 1, + SVGA3D_FOGTYPE_PIXEL = 2, + SVGA3D_FOGTYPE_MAX = 3 } SVGA3dFogType; - typedef enum { - SVGA3D_FOGBASE_INVALID = 0, - SVGA3D_FOGBASE_DEPTHBASED = 1, - SVGA3D_FOGBASE_RANGEBASED = 2, - SVGA3D_FOGBASE_MAX = 3 + SVGA3D_FOGBASE_INVALID = 0, + SVGA3D_FOGBASE_DEPTHBASED = 1, + SVGA3D_FOGBASE_RANGEBASED = 2, + SVGA3D_FOGBASE_MAX = 3 } SVGA3dFogBase; typedef enum { - SVGA3D_STENCILOP_INVALID = 0, - SVGA3D_STENCILOP_MIN = 1, - SVGA3D_STENCILOP_KEEP = 1, - SVGA3D_STENCILOP_ZERO = 2, - SVGA3D_STENCILOP_REPLACE = 3, - SVGA3D_STENCILOP_INCRSAT = 4, - SVGA3D_STENCILOP_DECRSAT = 5, - SVGA3D_STENCILOP_INVERT = 6, - SVGA3D_STENCILOP_INCR = 7, - SVGA3D_STENCILOP_DECR = 8, + SVGA3D_STENCILOP_INVALID = 0, + SVGA3D_STENCILOP_MIN = 1, + SVGA3D_STENCILOP_KEEP = 1, + SVGA3D_STENCILOP_ZERO = 2, + SVGA3D_STENCILOP_REPLACE = 3, + SVGA3D_STENCILOP_INCRSAT = 4, + SVGA3D_STENCILOP_DECRSAT = 5, + SVGA3D_STENCILOP_INVERT = 6, + SVGA3D_STENCILOP_INCR = 7, + SVGA3D_STENCILOP_DECR = 8, SVGA3D_STENCILOP_MAX } SVGA3dStencilOp; typedef enum { - SVGA3D_CLIPPLANE_0 = (1 << 0), - SVGA3D_CLIPPLANE_1 = (1 << 1), - SVGA3D_CLIPPLANE_2 = (1 << 2), - SVGA3D_CLIPPLANE_3 = (1 << 3), - SVGA3D_CLIPPLANE_4 = (1 << 4), - SVGA3D_CLIPPLANE_5 = (1 << 5), + SVGA3D_CLIPPLANE_0 = (1 << 0), + SVGA3D_CLIPPLANE_1 = (1 << 1), + SVGA3D_CLIPPLANE_2 = (1 << 2), + SVGA3D_CLIPPLANE_3 = (1 << 3), + SVGA3D_CLIPPLANE_4 = (1 << 4), + SVGA3D_CLIPPLANE_5 = (1 << 5), } SVGA3dClipPlanes; typedef enum { - SVGA3D_CLEAR_COLOR = 0x1, - SVGA3D_CLEAR_DEPTH = 0x2, - SVGA3D_CLEAR_STENCIL = 0x4, + SVGA3D_CLEAR_COLOR = 0x1, + SVGA3D_CLEAR_DEPTH = 0x2, + SVGA3D_CLEAR_STENCIL = 0x4, - - SVGA3D_CLEAR_COLORFILL = 0x8 + SVGA3D_CLEAR_COLORFILL = 0x8 } SVGA3dClearFlag; typedef enum { - SVGA3D_RT_DEPTH = 0, - SVGA3D_RT_MIN = 0, - SVGA3D_RT_STENCIL = 1, - SVGA3D_RT_COLOR0 = 2, - SVGA3D_RT_COLOR1 = 3, - SVGA3D_RT_COLOR2 = 4, - SVGA3D_RT_COLOR3 = 5, - SVGA3D_RT_COLOR4 = 6, - SVGA3D_RT_COLOR5 = 7, - SVGA3D_RT_COLOR6 = 8, - SVGA3D_RT_COLOR7 = 9, + SVGA3D_RT_DEPTH = 0, + SVGA3D_RT_MIN = 0, + SVGA3D_RT_STENCIL = 1, + SVGA3D_RT_COLOR0 = 2, + SVGA3D_RT_COLOR1 = 3, + SVGA3D_RT_COLOR2 = 4, + SVGA3D_RT_COLOR3 = 5, + SVGA3D_RT_COLOR4 = 6, + SVGA3D_RT_COLOR5 = 7, + SVGA3D_RT_COLOR6 = 8, + SVGA3D_RT_COLOR7 = 9, SVGA3D_RT_MAX, - SVGA3D_RT_INVALID = ((uint32)-1), + SVGA3D_RT_INVALID = ((uint32)-1), } SVGA3dRenderTargetType; #define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1) -typedef -#include "vmware_pack_begin.h" -union { +#pragma pack(push, 1) +typedef union { struct { - uint32 red : 1; - uint32 green : 1; - uint32 blue : 1; - uint32 alpha : 1; + uint32 red : 1; + uint32 green : 1; + uint32 blue : 1; + uint32 alpha : 1; }; uint32 uintValue; -} -#include "vmware_pack_end.h" -SVGA3dColorMask; +} SVGA3dColorMask; +#pragma pack(pop) typedef enum { - SVGA3D_VBLEND_DISABLE = 0, - SVGA3D_VBLEND_1WEIGHT = 1, - SVGA3D_VBLEND_2WEIGHT = 2, - SVGA3D_VBLEND_3WEIGHT = 3, - SVGA3D_VBLEND_MAX = 4, + SVGA3D_VBLEND_DISABLE = 0, + SVGA3D_VBLEND_1WEIGHT = 1, + SVGA3D_VBLEND_2WEIGHT = 2, + SVGA3D_VBLEND_3WEIGHT = 3, + SVGA3D_VBLEND_MAX = 4, } SVGA3dVertexBlendFlags; typedef enum { - SVGA3D_WRAPCOORD_0 = 1 << 0, - SVGA3D_WRAPCOORD_1 = 1 << 1, - SVGA3D_WRAPCOORD_2 = 1 << 2, - SVGA3D_WRAPCOORD_3 = 1 << 3, + SVGA3D_WRAPCOORD_0 = 1 << 0, + SVGA3D_WRAPCOORD_1 = 1 << 1, + SVGA3D_WRAPCOORD_2 = 1 << 2, + SVGA3D_WRAPCOORD_3 = 1 << 3, SVGA3D_WRAPCOORD_ALL = 0xF, } SVGA3dWrapFlags; - - typedef enum { - SVGA3D_TS_INVALID = 0, - SVGA3D_TS_MIN = 1, - SVGA3D_TS_BIND_TEXTURE = 1, - SVGA3D_TS_COLOROP = 2, - SVGA3D_TS_COLORARG1 = 3, - SVGA3D_TS_COLORARG2 = 4, - SVGA3D_TS_ALPHAOP = 5, - SVGA3D_TS_ALPHAARG1 = 6, - SVGA3D_TS_ALPHAARG2 = 7, - SVGA3D_TS_ADDRESSU = 8, - SVGA3D_TS_ADDRESSV = 9, - SVGA3D_TS_MIPFILTER = 10, - SVGA3D_TS_MAGFILTER = 11, - SVGA3D_TS_MINFILTER = 12, - SVGA3D_TS_BORDERCOLOR = 13, - SVGA3D_TS_TEXCOORDINDEX = 14, - SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, - SVGA3D_TS_TEXCOORDGEN = 16, - SVGA3D_TS_BUMPENVMAT00 = 17, - SVGA3D_TS_BUMPENVMAT01 = 18, - SVGA3D_TS_BUMPENVMAT10 = 19, - SVGA3D_TS_BUMPENVMAT11 = 20, - SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, - SVGA3D_TS_TEXTURE_LOD_BIAS = 22, - SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, - SVGA3D_TS_ADDRESSW = 24, + SVGA3D_TS_INVALID = 0, + SVGA3D_TS_MIN = 1, + SVGA3D_TS_BIND_TEXTURE = 1, + SVGA3D_TS_COLOROP = 2, + SVGA3D_TS_COLORARG1 = 3, + SVGA3D_TS_COLORARG2 = 4, + SVGA3D_TS_ALPHAOP = 5, + SVGA3D_TS_ALPHAARG1 = 6, + SVGA3D_TS_ALPHAARG2 = 7, + SVGA3D_TS_ADDRESSU = 8, + SVGA3D_TS_ADDRESSV = 9, + SVGA3D_TS_MIPFILTER = 10, + SVGA3D_TS_MAGFILTER = 11, + SVGA3D_TS_MINFILTER = 12, + SVGA3D_TS_BORDERCOLOR = 13, + SVGA3D_TS_TEXCOORDINDEX = 14, + SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, + SVGA3D_TS_TEXCOORDGEN = 16, + SVGA3D_TS_BUMPENVMAT00 = 17, + SVGA3D_TS_BUMPENVMAT01 = 18, + SVGA3D_TS_BUMPENVMAT10 = 19, + SVGA3D_TS_BUMPENVMAT11 = 20, + SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, + SVGA3D_TS_TEXTURE_LOD_BIAS = 22, + SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, + SVGA3D_TS_ADDRESSW = 24, + SVGA3D_TS_GAMMA = 25, + SVGA3D_TS_BUMPENVLSCALE = 26, + SVGA3D_TS_BUMPENVLOFFSET = 27, + SVGA3D_TS_COLORARG0 = 28, + SVGA3D_TS_ALPHAARG0 = 29, + SVGA3D_TS_PREGB_MAX = 30, - - SVGA3D_TS_GAMMA = 25, - SVGA3D_TS_BUMPENVLSCALE = 26, - SVGA3D_TS_BUMPENVLOFFSET = 27, - SVGA3D_TS_COLORARG0 = 28, - SVGA3D_TS_ALPHAARG0 = 29, - SVGA3D_TS_PREGB_MAX = 30, - SVGA3D_TS_CONSTANT = 30, - SVGA3D_TS_COLOR_KEY_ENABLE = 31, - SVGA3D_TS_COLOR_KEY = 32, + SVGA3D_TS_CONSTANT = 30, + SVGA3D_TS_COLOR_KEY_ENABLE = 31, + SVGA3D_TS_COLOR_KEY = 32, SVGA3D_TS_MAX } SVGA3dTextureStateName; typedef enum { - SVGA3D_TC_INVALID = 0, - SVGA3D_TC_DISABLE = 1, - SVGA3D_TC_SELECTARG1 = 2, - SVGA3D_TC_SELECTARG2 = 3, - SVGA3D_TC_MODULATE = 4, - SVGA3D_TC_ADD = 5, - SVGA3D_TC_ADDSIGNED = 6, - SVGA3D_TC_SUBTRACT = 7, - SVGA3D_TC_BLENDTEXTUREALPHA = 8, - SVGA3D_TC_BLENDDIFFUSEALPHA = 9, - SVGA3D_TC_BLENDCURRENTALPHA = 10, - SVGA3D_TC_BLENDFACTORALPHA = 11, - SVGA3D_TC_MODULATE2X = 12, - SVGA3D_TC_MODULATE4X = 13, - SVGA3D_TC_DSDT = 14, - SVGA3D_TC_DOTPRODUCT3 = 15, - SVGA3D_TC_BLENDTEXTUREALPHAPM = 16, - SVGA3D_TC_ADDSIGNED2X = 17, - SVGA3D_TC_ADDSMOOTH = 18, - SVGA3D_TC_PREMODULATE = 19, - SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20, - SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21, + SVGA3D_TC_INVALID = 0, + SVGA3D_TC_DISABLE = 1, + SVGA3D_TC_SELECTARG1 = 2, + SVGA3D_TC_SELECTARG2 = 3, + SVGA3D_TC_MODULATE = 4, + SVGA3D_TC_ADD = 5, + SVGA3D_TC_ADDSIGNED = 6, + SVGA3D_TC_SUBTRACT = 7, + SVGA3D_TC_BLENDTEXTUREALPHA = 8, + SVGA3D_TC_BLENDDIFFUSEALPHA = 9, + SVGA3D_TC_BLENDCURRENTALPHA = 10, + SVGA3D_TC_BLENDFACTORALPHA = 11, + SVGA3D_TC_MODULATE2X = 12, + SVGA3D_TC_MODULATE4X = 13, + SVGA3D_TC_DSDT = 14, + SVGA3D_TC_DOTPRODUCT3 = 15, + SVGA3D_TC_BLENDTEXTUREALPHAPM = 16, + SVGA3D_TC_ADDSIGNED2X = 17, + SVGA3D_TC_ADDSMOOTH = 18, + SVGA3D_TC_PREMODULATE = 19, + SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20, + SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21, SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22, SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23, - SVGA3D_TC_BUMPENVMAPLUMINANCE = 24, - SVGA3D_TC_MULTIPLYADD = 25, - SVGA3D_TC_LERP = 26, + SVGA3D_TC_BUMPENVMAPLUMINANCE = 24, + SVGA3D_TC_MULTIPLYADD = 25, + SVGA3D_TC_LERP = 26, SVGA3D_TC_MAX } SVGA3dTextureCombiner; -#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0) +#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) \ + (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0) typedef enum { - SVGA3D_TEX_ADDRESS_INVALID = 0, - SVGA3D_TEX_ADDRESS_MIN = 1, - SVGA3D_TEX_ADDRESS_WRAP = 1, - SVGA3D_TEX_ADDRESS_MIRROR = 2, - SVGA3D_TEX_ADDRESS_CLAMP = 3, - SVGA3D_TEX_ADDRESS_BORDER = 4, + SVGA3D_TEX_ADDRESS_INVALID = 0, + SVGA3D_TEX_ADDRESS_MIN = 1, + SVGA3D_TEX_ADDRESS_WRAP = 1, + SVGA3D_TEX_ADDRESS_MIRROR = 2, + SVGA3D_TEX_ADDRESS_CLAMP = 3, + SVGA3D_TEX_ADDRESS_BORDER = 4, SVGA3D_TEX_ADDRESS_MIRRORONCE = 5, - SVGA3D_TEX_ADDRESS_EDGE = 6, + SVGA3D_TEX_ADDRESS_EDGE = 6, SVGA3D_TEX_ADDRESS_MAX } SVGA3dTextureAddress; - typedef enum { - SVGA3D_TEX_FILTER_NONE = 0, - SVGA3D_TEX_FILTER_MIN = 0, - SVGA3D_TEX_FILTER_NEAREST = 1, - SVGA3D_TEX_FILTER_LINEAR = 2, - SVGA3D_TEX_FILTER_ANISOTROPIC = 3, - SVGA3D_TEX_FILTER_FLATCUBIC = 4, - SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, - SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, - SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, + SVGA3D_TEX_FILTER_NONE = 0, + SVGA3D_TEX_FILTER_MIN = 0, + SVGA3D_TEX_FILTER_NEAREST = 1, + SVGA3D_TEX_FILTER_LINEAR = 2, + SVGA3D_TEX_FILTER_ANISOTROPIC = 3, + SVGA3D_TEX_FILTER_FLATCUBIC = 4, + SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, + SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, + SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, SVGA3D_TEX_FILTER_MAX } SVGA3dTextureFilter; typedef enum { - SVGA3D_TEX_TRANSFORM_OFF = 0, - SVGA3D_TEX_TRANSFORM_S = (1 << 0), - SVGA3D_TEX_TRANSFORM_T = (1 << 1), - SVGA3D_TEX_TRANSFORM_R = (1 << 2), - SVGA3D_TEX_TRANSFORM_Q = (1 << 3), - SVGA3D_TEX_PROJECTED = (1 << 15), + SVGA3D_TEX_TRANSFORM_OFF = 0, + SVGA3D_TEX_TRANSFORM_S = (1 << 0), + SVGA3D_TEX_TRANSFORM_T = (1 << 1), + SVGA3D_TEX_TRANSFORM_R = (1 << 2), + SVGA3D_TEX_TRANSFORM_Q = (1 << 3), + SVGA3D_TEX_PROJECTED = (1 << 15), } SVGA3dTexTransformFlags; typedef enum { - SVGA3D_TEXCOORD_GEN_OFF = 0, - SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1, - SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2, + SVGA3D_TEXCOORD_GEN_OFF = 0, + SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1, + SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2, SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3, - SVGA3D_TEXCOORD_GEN_SPHERE = 4, + SVGA3D_TEXCOORD_GEN_SPHERE = 4, SVGA3D_TEXCOORD_GEN_MAX } SVGA3dTextureCoordGen; - typedef enum { - SVGA3D_TA_INVALID = 0, - SVGA3D_TA_TFACTOR = 1, - SVGA3D_TA_PREVIOUS = 2, - SVGA3D_TA_DIFFUSE = 3, - SVGA3D_TA_TEXTURE = 4, - SVGA3D_TA_SPECULAR = 5, - SVGA3D_TA_CONSTANT = 6, + SVGA3D_TA_INVALID = 0, + SVGA3D_TA_TFACTOR = 1, + SVGA3D_TA_PREVIOUS = 2, + SVGA3D_TA_DIFFUSE = 3, + SVGA3D_TA_TEXTURE = 4, + SVGA3D_TA_SPECULAR = 5, + SVGA3D_TA_CONSTANT = 6, SVGA3D_TA_MAX } SVGA3dTextureArgData; #define SVGA3D_TM_MASK_LEN 4 - typedef enum { - SVGA3D_TM_NONE = 0, - SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN), - SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN), + SVGA3D_TM_NONE = 0, + SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN), + SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN), } SVGA3dTextureArgModifier; - - typedef enum { - SVGA3D_DECLUSAGE_POSITION = 0, + SVGA3D_DECLUSAGE_POSITION = 0, SVGA3D_DECLUSAGE_BLENDWEIGHT, SVGA3D_DECLUSAGE_BLENDINDICES, SVGA3D_DECLUSAGE_NORMAL, @@ -1336,7 +1097,7 @@ typedef enum { } SVGA3dDeclUsage; typedef enum { - SVGA3D_DECLMETHOD_DEFAULT = 0, + SVGA3D_DECLMETHOD_DEFAULT = 0, SVGA3D_DECLMETHOD_PARTIALU, SVGA3D_DECLMETHOD_PARTIALV, SVGA3D_DECLMETHOD_CROSSUV, @@ -1346,36 +1107,33 @@ typedef enum { } SVGA3dDeclMethod; typedef enum { - SVGA3D_DECLTYPE_FLOAT1 = 0, - SVGA3D_DECLTYPE_FLOAT2 = 1, - SVGA3D_DECLTYPE_FLOAT3 = 2, - SVGA3D_DECLTYPE_FLOAT4 = 3, - SVGA3D_DECLTYPE_D3DCOLOR = 4, - SVGA3D_DECLTYPE_UBYTE4 = 5, - SVGA3D_DECLTYPE_SHORT2 = 6, - SVGA3D_DECLTYPE_SHORT4 = 7, - SVGA3D_DECLTYPE_UBYTE4N = 8, - SVGA3D_DECLTYPE_SHORT2N = 9, - SVGA3D_DECLTYPE_SHORT4N = 10, - SVGA3D_DECLTYPE_USHORT2N = 11, - SVGA3D_DECLTYPE_USHORT4N = 12, - SVGA3D_DECLTYPE_UDEC3 = 13, - SVGA3D_DECLTYPE_DEC3N = 14, - SVGA3D_DECLTYPE_FLOAT16_2 = 15, - SVGA3D_DECLTYPE_FLOAT16_4 = 16, + SVGA3D_DECLTYPE_FLOAT1 = 0, + SVGA3D_DECLTYPE_FLOAT2 = 1, + SVGA3D_DECLTYPE_FLOAT3 = 2, + SVGA3D_DECLTYPE_FLOAT4 = 3, + SVGA3D_DECLTYPE_D3DCOLOR = 4, + SVGA3D_DECLTYPE_UBYTE4 = 5, + SVGA3D_DECLTYPE_SHORT2 = 6, + SVGA3D_DECLTYPE_SHORT4 = 7, + SVGA3D_DECLTYPE_UBYTE4N = 8, + SVGA3D_DECLTYPE_SHORT2N = 9, + SVGA3D_DECLTYPE_SHORT4N = 10, + SVGA3D_DECLTYPE_USHORT2N = 11, + SVGA3D_DECLTYPE_USHORT4N = 12, + SVGA3D_DECLTYPE_UDEC3 = 13, + SVGA3D_DECLTYPE_DEC3N = 14, + SVGA3D_DECLTYPE_FLOAT16_2 = 15, + SVGA3D_DECLTYPE_FLOAT16_4 = 16, SVGA3D_DECLTYPE_MAX, } SVGA3dDeclType; - typedef union { struct { uint32 count : 30; - uint32 indexedData : 1; - uint32 instanceData : 1; }; @@ -1384,212 +1142,197 @@ typedef union { typedef enum { - SVGA3D_PRIMITIVE_INVALID = 0, - SVGA3D_PRIMITIVE_MIN = 0, - SVGA3D_PRIMITIVE_TRIANGLELIST = 1, - SVGA3D_PRIMITIVE_POINTLIST = 2, - SVGA3D_PRIMITIVE_LINELIST = 3, - SVGA3D_PRIMITIVE_LINESTRIP = 4, - SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5, - SVGA3D_PRIMITIVE_TRIANGLEFAN = 6, - SVGA3D_PRIMITIVE_LINELIST_ADJ = 7, - SVGA3D_PRIMITIVE_PREDX_MAX = 7, - SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8, - SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9, - SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10, - SVGA3D_PRIMITIVE_DX10_MAX = 11, - SVGA3D_PRIMITIVE_1_CONTROL_POINT_PATCH = 11, - SVGA3D_PRIMITIVE_2_CONTROL_POINT_PATCH = 12, - SVGA3D_PRIMITIVE_3_CONTROL_POINT_PATCH = 13, - SVGA3D_PRIMITIVE_4_CONTROL_POINT_PATCH = 14, - SVGA3D_PRIMITIVE_5_CONTROL_POINT_PATCH = 15, - SVGA3D_PRIMITIVE_6_CONTROL_POINT_PATCH = 16, - SVGA3D_PRIMITIVE_7_CONTROL_POINT_PATCH = 17, - SVGA3D_PRIMITIVE_8_CONTROL_POINT_PATCH = 18, - SVGA3D_PRIMITIVE_9_CONTROL_POINT_PATCH = 19, - SVGA3D_PRIMITIVE_10_CONTROL_POINT_PATCH = 20, - SVGA3D_PRIMITIVE_11_CONTROL_POINT_PATCH = 21, - SVGA3D_PRIMITIVE_12_CONTROL_POINT_PATCH = 22, - SVGA3D_PRIMITIVE_13_CONTROL_POINT_PATCH = 23, - SVGA3D_PRIMITIVE_14_CONTROL_POINT_PATCH = 24, - SVGA3D_PRIMITIVE_15_CONTROL_POINT_PATCH = 25, - SVGA3D_PRIMITIVE_16_CONTROL_POINT_PATCH = 26, - SVGA3D_PRIMITIVE_17_CONTROL_POINT_PATCH = 27, - SVGA3D_PRIMITIVE_18_CONTROL_POINT_PATCH = 28, - SVGA3D_PRIMITIVE_19_CONTROL_POINT_PATCH = 29, - SVGA3D_PRIMITIVE_20_CONTROL_POINT_PATCH = 30, - SVGA3D_PRIMITIVE_21_CONTROL_POINT_PATCH = 31, - SVGA3D_PRIMITIVE_22_CONTROL_POINT_PATCH = 32, - SVGA3D_PRIMITIVE_23_CONTROL_POINT_PATCH = 33, - SVGA3D_PRIMITIVE_24_CONTROL_POINT_PATCH = 34, - SVGA3D_PRIMITIVE_25_CONTROL_POINT_PATCH = 35, - SVGA3D_PRIMITIVE_26_CONTROL_POINT_PATCH = 36, - SVGA3D_PRIMITIVE_27_CONTROL_POINT_PATCH = 37, - SVGA3D_PRIMITIVE_28_CONTROL_POINT_PATCH = 38, - SVGA3D_PRIMITIVE_29_CONTROL_POINT_PATCH = 39, - SVGA3D_PRIMITIVE_30_CONTROL_POINT_PATCH = 40, - SVGA3D_PRIMITIVE_31_CONTROL_POINT_PATCH = 41, - SVGA3D_PRIMITIVE_32_CONTROL_POINT_PATCH = 42, - SVGA3D_PRIMITIVE_MAX = 43 + SVGA3D_PRIMITIVE_INVALID = 0, + SVGA3D_PRIMITIVE_MIN = 0, + SVGA3D_PRIMITIVE_TRIANGLELIST = 1, + SVGA3D_PRIMITIVE_POINTLIST = 2, + SVGA3D_PRIMITIVE_LINELIST = 3, + SVGA3D_PRIMITIVE_LINESTRIP = 4, + SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5, + SVGA3D_PRIMITIVE_TRIANGLEFAN = 6, + SVGA3D_PRIMITIVE_LINELIST_ADJ = 7, + SVGA3D_PRIMITIVE_PREDX_MAX = 7, + SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8, + SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9, + SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10, + SVGA3D_PRIMITIVE_DX10_MAX = 11, + SVGA3D_PRIMITIVE_1_CONTROL_POINT_PATCH = 11, + SVGA3D_PRIMITIVE_2_CONTROL_POINT_PATCH = 12, + SVGA3D_PRIMITIVE_3_CONTROL_POINT_PATCH = 13, + SVGA3D_PRIMITIVE_4_CONTROL_POINT_PATCH = 14, + SVGA3D_PRIMITIVE_5_CONTROL_POINT_PATCH = 15, + SVGA3D_PRIMITIVE_6_CONTROL_POINT_PATCH = 16, + SVGA3D_PRIMITIVE_7_CONTROL_POINT_PATCH = 17, + SVGA3D_PRIMITIVE_8_CONTROL_POINT_PATCH = 18, + SVGA3D_PRIMITIVE_9_CONTROL_POINT_PATCH = 19, + SVGA3D_PRIMITIVE_10_CONTROL_POINT_PATCH = 20, + SVGA3D_PRIMITIVE_11_CONTROL_POINT_PATCH = 21, + SVGA3D_PRIMITIVE_12_CONTROL_POINT_PATCH = 22, + SVGA3D_PRIMITIVE_13_CONTROL_POINT_PATCH = 23, + SVGA3D_PRIMITIVE_14_CONTROL_POINT_PATCH = 24, + SVGA3D_PRIMITIVE_15_CONTROL_POINT_PATCH = 25, + SVGA3D_PRIMITIVE_16_CONTROL_POINT_PATCH = 26, + SVGA3D_PRIMITIVE_17_CONTROL_POINT_PATCH = 27, + SVGA3D_PRIMITIVE_18_CONTROL_POINT_PATCH = 28, + SVGA3D_PRIMITIVE_19_CONTROL_POINT_PATCH = 29, + SVGA3D_PRIMITIVE_20_CONTROL_POINT_PATCH = 30, + SVGA3D_PRIMITIVE_21_CONTROL_POINT_PATCH = 31, + SVGA3D_PRIMITIVE_22_CONTROL_POINT_PATCH = 32, + SVGA3D_PRIMITIVE_23_CONTROL_POINT_PATCH = 33, + SVGA3D_PRIMITIVE_24_CONTROL_POINT_PATCH = 34, + SVGA3D_PRIMITIVE_25_CONTROL_POINT_PATCH = 35, + SVGA3D_PRIMITIVE_26_CONTROL_POINT_PATCH = 36, + SVGA3D_PRIMITIVE_27_CONTROL_POINT_PATCH = 37, + SVGA3D_PRIMITIVE_28_CONTROL_POINT_PATCH = 38, + SVGA3D_PRIMITIVE_29_CONTROL_POINT_PATCH = 39, + SVGA3D_PRIMITIVE_30_CONTROL_POINT_PATCH = 40, + SVGA3D_PRIMITIVE_31_CONTROL_POINT_PATCH = 41, + SVGA3D_PRIMITIVE_32_CONTROL_POINT_PATCH = 42, + SVGA3D_PRIMITIVE_MAX = 43 } SVGA3dPrimitiveType; typedef enum { - SVGA3D_COORDINATE_INVALID = 0, - SVGA3D_COORDINATE_LEFTHANDED = 1, - SVGA3D_COORDINATE_RIGHTHANDED = 2, + SVGA3D_COORDINATE_INVALID = 0, + SVGA3D_COORDINATE_LEFTHANDED = 1, + SVGA3D_COORDINATE_RIGHTHANDED = 2, SVGA3D_COORDINATE_MAX } SVGA3dCoordinateType; typedef enum { - SVGA3D_TRANSFORM_INVALID = 0, - SVGA3D_TRANSFORM_WORLD = 1, - SVGA3D_TRANSFORM_MIN = 1, - SVGA3D_TRANSFORM_VIEW = 2, - SVGA3D_TRANSFORM_PROJECTION = 3, - SVGA3D_TRANSFORM_TEXTURE0 = 4, - SVGA3D_TRANSFORM_TEXTURE1 = 5, - SVGA3D_TRANSFORM_TEXTURE2 = 6, - SVGA3D_TRANSFORM_TEXTURE3 = 7, - SVGA3D_TRANSFORM_TEXTURE4 = 8, - SVGA3D_TRANSFORM_TEXTURE5 = 9, - SVGA3D_TRANSFORM_TEXTURE6 = 10, - SVGA3D_TRANSFORM_TEXTURE7 = 11, - SVGA3D_TRANSFORM_WORLD1 = 12, - SVGA3D_TRANSFORM_WORLD2 = 13, - SVGA3D_TRANSFORM_WORLD3 = 14, + SVGA3D_TRANSFORM_INVALID = 0, + SVGA3D_TRANSFORM_WORLD = 1, + SVGA3D_TRANSFORM_MIN = 1, + SVGA3D_TRANSFORM_VIEW = 2, + SVGA3D_TRANSFORM_PROJECTION = 3, + SVGA3D_TRANSFORM_TEXTURE0 = 4, + SVGA3D_TRANSFORM_TEXTURE1 = 5, + SVGA3D_TRANSFORM_TEXTURE2 = 6, + SVGA3D_TRANSFORM_TEXTURE3 = 7, + SVGA3D_TRANSFORM_TEXTURE4 = 8, + SVGA3D_TRANSFORM_TEXTURE5 = 9, + SVGA3D_TRANSFORM_TEXTURE6 = 10, + SVGA3D_TRANSFORM_TEXTURE7 = 11, + SVGA3D_TRANSFORM_WORLD1 = 12, + SVGA3D_TRANSFORM_WORLD2 = 13, + SVGA3D_TRANSFORM_WORLD3 = 14, SVGA3D_TRANSFORM_MAX } SVGA3dTransformType; typedef enum { - SVGA3D_LIGHTTYPE_INVALID = 0, - SVGA3D_LIGHTTYPE_MIN = 1, - SVGA3D_LIGHTTYPE_POINT = 1, - SVGA3D_LIGHTTYPE_SPOT1 = 2, - SVGA3D_LIGHTTYPE_SPOT2 = 3, - SVGA3D_LIGHTTYPE_DIRECTIONAL = 4, + SVGA3D_LIGHTTYPE_INVALID = 0, + SVGA3D_LIGHTTYPE_MIN = 1, + SVGA3D_LIGHTTYPE_POINT = 1, + SVGA3D_LIGHTTYPE_SPOT1 = 2, + SVGA3D_LIGHTTYPE_SPOT2 = 3, + SVGA3D_LIGHTTYPE_DIRECTIONAL = 4, SVGA3D_LIGHTTYPE_MAX } SVGA3dLightType; typedef enum { - SVGA3D_CUBEFACE_POSX = 0, - SVGA3D_CUBEFACE_NEGX = 1, - SVGA3D_CUBEFACE_POSY = 2, - SVGA3D_CUBEFACE_NEGY = 3, - SVGA3D_CUBEFACE_POSZ = 4, - SVGA3D_CUBEFACE_NEGZ = 5, + SVGA3D_CUBEFACE_POSX = 0, + SVGA3D_CUBEFACE_NEGX = 1, + SVGA3D_CUBEFACE_POSY = 2, + SVGA3D_CUBEFACE_NEGY = 3, + SVGA3D_CUBEFACE_POSZ = 4, + SVGA3D_CUBEFACE_NEGZ = 5, } SVGA3dCubeFace; typedef enum { - SVGA3D_SHADERTYPE_INVALID = 0, - SVGA3D_SHADERTYPE_MIN = 1, - SVGA3D_SHADERTYPE_VS = 1, - SVGA3D_SHADERTYPE_PS = 2, - SVGA3D_SHADERTYPE_PREDX_MAX = 3, - SVGA3D_SHADERTYPE_GS = 3, - SVGA3D_SHADERTYPE_DX10_MAX = 4, - SVGA3D_SHADERTYPE_HS = 4, - SVGA3D_SHADERTYPE_DS = 5, - SVGA3D_SHADERTYPE_CS = 6, - SVGA3D_SHADERTYPE_MAX = 7 + SVGA3D_SHADERTYPE_INVALID = 0, + SVGA3D_SHADERTYPE_MIN = 1, + SVGA3D_SHADERTYPE_VS = 1, + SVGA3D_SHADERTYPE_PS = 2, + SVGA3D_SHADERTYPE_PREDX_MAX = 3, + SVGA3D_SHADERTYPE_GS = 3, + SVGA3D_SHADERTYPE_DX10_MAX = 4, + SVGA3D_SHADERTYPE_HS = 4, + SVGA3D_SHADERTYPE_DS = 5, + SVGA3D_SHADERTYPE_CS = 6, + SVGA3D_SHADERTYPE_MAX = 7 } SVGA3dShaderType; -#define SVGA3D_NUM_SHADERTYPE_PREDX \ +#define SVGA3D_NUM_SHADERTYPE_PREDX \ (SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN) -#define SVGA3D_NUM_SHADERTYPE_DX10 \ +#define SVGA3D_NUM_SHADERTYPE_DX10 \ (SVGA3D_SHADERTYPE_DX10_MAX - SVGA3D_SHADERTYPE_MIN) -#define SVGA3D_NUM_SHADERTYPE \ - (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN) +#define SVGA3D_NUM_SHADERTYPE (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN) typedef enum { - SVGA3D_CONST_TYPE_MIN = 0, - SVGA3D_CONST_TYPE_FLOAT = 0, - SVGA3D_CONST_TYPE_INT = 1, - SVGA3D_CONST_TYPE_BOOL = 2, - SVGA3D_CONST_TYPE_MAX = 3, + SVGA3D_CONST_TYPE_MIN = 0, + SVGA3D_CONST_TYPE_FLOAT = 0, + SVGA3D_CONST_TYPE_INT = 1, + SVGA3D_CONST_TYPE_BOOL = 2, + SVGA3D_CONST_TYPE_MAX = 3, } SVGA3dShaderConstType; - -#define SVGA3D_CONSTREG_MAX 256 -#define SVGA3D_CONSTINTREG_MAX 16 -#define SVGA3D_CONSTBOOLREG_MAX 16 +#define SVGA3D_CONSTREG_MAX 256 +#define SVGA3D_CONSTINTREG_MAX 16 +#define SVGA3D_CONSTBOOLREG_MAX 16 typedef enum { - SVGA3D_STRETCH_BLT_POINT = 0, - SVGA3D_STRETCH_BLT_LINEAR = 1, + SVGA3D_STRETCH_BLT_POINT = 0, + SVGA3D_STRETCH_BLT_LINEAR = 1, SVGA3D_STRETCH_BLT_MAX } SVGA3dStretchBltMode; typedef enum { - SVGA3D_QUERYTYPE_INVALID = ((uint8)-1), - SVGA3D_QUERYTYPE_MIN = 0, - SVGA3D_QUERYTYPE_OCCLUSION = 0, - SVGA3D_QUERYTYPE_TIMESTAMP = 1, - SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2, - SVGA3D_QUERYTYPE_PIPELINESTATS = 3, - SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4, - SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5, - SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6, - SVGA3D_QUERYTYPE_OCCLUSION64 = 7, - SVGA3D_QUERYTYPE_DX10_MAX = 8, - SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 8, - SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 9, - SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 10, - SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 11, - SVGA3D_QUERYTYPE_SOP_STREAM0 = 12, - SVGA3D_QUERYTYPE_SOP_STREAM1 = 13, - SVGA3D_QUERYTYPE_SOP_STREAM2 = 14, - SVGA3D_QUERYTYPE_SOP_STREAM3 = 15, + SVGA3D_QUERYTYPE_INVALID = ((uint8)-1), + SVGA3D_QUERYTYPE_MIN = 0, + SVGA3D_QUERYTYPE_OCCLUSION = 0, + SVGA3D_QUERYTYPE_TIMESTAMP = 1, + SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2, + SVGA3D_QUERYTYPE_PIPELINESTATS = 3, + SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4, + SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5, + SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6, + SVGA3D_QUERYTYPE_OCCLUSION64 = 7, + SVGA3D_QUERYTYPE_DX10_MAX = 8, + SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 8, + SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 9, + SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 10, + SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 11, + SVGA3D_QUERYTYPE_SOP_STREAM0 = 12, + SVGA3D_QUERYTYPE_SOP_STREAM1 = 13, + SVGA3D_QUERYTYPE_SOP_STREAM2 = 14, + SVGA3D_QUERYTYPE_SOP_STREAM3 = 15, SVGA3D_QUERYTYPE_MAX } SVGA3dQueryType; typedef uint8 SVGA3dQueryTypeUint8; -#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN) - +#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN) #define SVGA3D_MAX_QUERY 64 -/* - * Query result buffer formats - */ -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 samplesRendered; -} -#include "vmware_pack_end.h" -SVGADXOcclusionQueryResult; +} SVGADXOcclusionQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 passed; -} -#include "vmware_pack_end.h" -SVGADXEventQueryResult; +} SVGADXEventQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint64 timestamp; -} -#include "vmware_pack_end.h" -SVGADXTimestampQueryResult; +} SVGADXTimestampQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint64 realFrequency; uint32 disjoint; -} -#include "vmware_pack_end.h" -SVGADXTimestampDisjointQueryResult; +} SVGADXTimestampDisjointQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint64 inputAssemblyVertices; uint64 inputAssemblyPrimitives; uint64 vertexShaderInvocations; @@ -1601,50 +1344,36 @@ struct { uint64 hullShaderInvocations; uint64 domainShaderInvocations; uint64 computeShaderInvocations; -} -#include "vmware_pack_end.h" -SVGADXPipelineStatisticsQueryResult; +} SVGADXPipelineStatisticsQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 anySamplesRendered; -} -#include "vmware_pack_end.h" -SVGADXOcclusionPredicateQueryResult; +} SVGADXOcclusionPredicateQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint64 numPrimitivesWritten; uint64 numPrimitivesRequired; -} -#include "vmware_pack_end.h" -SVGADXStreamOutStatisticsQueryResult; +} SVGADXStreamOutStatisticsQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint32 overflowed; -} -#include "vmware_pack_end.h" -SVGADXStreamOutPredicateQueryResult; +} SVGADXStreamOutPredicateQueryResult; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { uint64 samplesRendered; -} -#include "vmware_pack_end.h" -SVGADXOcclusion64QueryResult; +} SVGADXOcclusion64QueryResult; +#pragma pack(pop) -/* - * SVGADXQueryResultUnion is not intended for use in the protocol, but is - * very helpful when working with queries generically. - */ -typedef -#include "vmware_pack_begin.h" -union SVGADXQueryResultUnion { +#pragma pack(push, 1) +typedef union SVGADXQueryResultUnion { SVGADXOcclusionQueryResult occ; SVGADXEventQueryResult event; SVGADXTimestampQueryResult ts; @@ -1654,188 +1383,160 @@ union SVGADXQueryResultUnion { SVGADXStreamOutStatisticsQueryResult soStats; SVGADXStreamOutPredicateQueryResult soPred; SVGADXOcclusion64QueryResult occ64; -} -#include "vmware_pack_end.h" -SVGADXQueryResultUnion; - +} SVGADXQueryResultUnion; +#pragma pack(pop) typedef enum { - SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */ - SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */ - SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully */ - SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (guest only) */ + SVGA3D_QUERYSTATE_PENDING = 0, + SVGA3D_QUERYSTATE_SUCCEEDED = 1, + SVGA3D_QUERYSTATE_FAILED = 2, + SVGA3D_QUERYSTATE_NEW = 3, } SVGA3dQueryState; typedef enum { - SVGA3D_WRITE_HOST_VRAM = 1, - SVGA3D_READ_HOST_VRAM = 2, + SVGA3D_WRITE_HOST_VRAM = 1, + SVGA3D_READ_HOST_VRAM = 2, } SVGA3dTransferType; -#define SVGA3D_LOGICOP_INVALID 0 -#define SVGA3D_LOGICOP_COPY 1 -#define SVGA3D_LOGICOP_MIN 1 -#define SVGA3D_LOGICOP_NOT 2 -#define SVGA3D_LOGICOP_AND 3 -#define SVGA3D_LOGICOP_OR 4 -#define SVGA3D_LOGICOP_XOR 5 -#define SVGA3D_LOGICOP_NXOR 6 -#define SVGA3D_LOGICOP_ROP3 7 -#define SVGA3D_LOGICOP_MAX 8 +#define SVGA3D_LOGICOP_INVALID 0 +#define SVGA3D_LOGICOP_COPY 1 + +#define SVGA3D_LOGICOP_MIN 1 +#define SVGA3D_LOGICOP_NOT 2 +#define SVGA3D_LOGICOP_AND 3 +#define SVGA3D_LOGICOP_OR 4 +#define SVGA3D_LOGICOP_XOR 5 +#define SVGA3D_LOGICOP_NXOR 6 +#define SVGA3D_LOGICOP_ROP3 7 + +#define SVGA3D_LOGICOP_MAX 8 typedef uint16 SVGA3dLogicOp; -#define SVGA3D_LOGICOP_ROP3_INVALID ((uint16) -1) +#define SVGA3D_LOGICOP_ROP3_INVALID ((uint16) - 1) #define SVGA3D_LOGICOP_ROP3_MIN 0 #define SVGA3D_LOGICOP_ROP3_MAX 256 typedef uint16 SVGA3dLogicOpRop3; -typedef -#include "vmware_pack_begin.h" -struct { +#pragma pack(push, 1) +typedef struct { union { struct { - uint16 function; /* SVGA3dFogFunction */ - uint8 type; /* SVGA3dFogType */ - uint8 base; /* SVGA3dFogBase */ + uint16 function; + uint8 type; + uint8 base; }; - uint32 uintValue; + uint32 uintValue; }; -} -#include "vmware_pack_end.h" -SVGA3dFogMode; +} SVGA3dFogMode; +#pragma pack(pop) -/* - * Uniquely identify one image (a 1D/2D/3D array) from a surface. This - * is a surface ID as well as face/mipmap indices. - */ -typedef -#include "vmware_pack_begin.h" -struct SVGA3dSurfaceImageId { - uint32 sid; - uint32 face; - uint32 mipmap; -} -#include "vmware_pack_end.h" -SVGA3dSurfaceImageId; +#pragma pack(push, 1) +typedef struct SVGA3dSurfaceImageId { + uint32 sid; + uint32 face; + uint32 mipmap; +} SVGA3dSurfaceImageId; +#pragma pack(pop) -typedef -#include "vmware_pack_begin.h" -struct SVGA3dSubSurfaceId { +#pragma pack(push, 1) +typedef struct SVGA3dSubSurfaceId { uint32 sid; uint32 subResourceId; -} -#include "vmware_pack_end.h" -SVGA3dSubSurfaceId; - -typedef -#include "vmware_pack_begin.h" -struct { - uint32 width; - uint32 height; - uint32 depth; -} -#include "vmware_pack_end.h" -SVGA3dSize; +} SVGA3dSubSurfaceId; +#pragma pack(pop) +#pragma pack(push, 1) +typedef struct { + uint32 width; + uint32 height; + uint32 depth; +} SVGA3dSize; +#pragma pack(pop) typedef enum { - SVGA_OTABLE_MOB = 0, - SVGA_OTABLE_MIN = 0, - SVGA_OTABLE_SURFACE = 1, - SVGA_OTABLE_CONTEXT = 2, - SVGA_OTABLE_SHADER = 3, - SVGA_OTABLE_SCREENTARGET = 4, + SVGA_OTABLE_MOB = 0, + SVGA_OTABLE_MIN = 0, + SVGA_OTABLE_SURFACE = 1, + SVGA_OTABLE_CONTEXT = 2, + SVGA_OTABLE_SHADER = 3, + SVGA_OTABLE_SCREENTARGET = 4, - SVGA_OTABLE_DX9_MAX = 5, + SVGA_OTABLE_DX9_MAX = 5, - SVGA_OTABLE_DXCONTEXT = 5, - SVGA_OTABLE_DX_MAX = 6, + SVGA_OTABLE_DXCONTEXT = 5, + SVGA_OTABLE_DX_MAX = 6, + SVGA_OTABLE_DEVEL_MAX = 6, + SVGA_OTABLE_MAX = 6, - - SVGA_OTABLE_DEVEL_MAX = 6, - SVGA_OTABLE_MAX = 6, - - - SVGA_OTABLE_RESERVED1 = 6, - SVGA_OTABLE_RESERVED2 = 7, + SVGA_OTABLE_RESERVED1 = 6, + SVGA_OTABLE_RESERVED2 = 7, SVGA_OTABLE_BUG_1952836_MAX = 8, } SVGAOTableType; typedef enum { - SVGA_COTABLE_MIN = 0, - SVGA_COTABLE_RTVIEW = 0, - SVGA_COTABLE_DSVIEW = 1, - SVGA_COTABLE_SRVIEW = 2, - SVGA_COTABLE_ELEMENTLAYOUT = 3, - SVGA_COTABLE_BLENDSTATE = 4, - SVGA_COTABLE_DEPTHSTENCIL = 5, + SVGA_COTABLE_MIN = 0, + SVGA_COTABLE_RTVIEW = 0, + SVGA_COTABLE_DSVIEW = 1, + SVGA_COTABLE_SRVIEW = 2, + SVGA_COTABLE_ELEMENTLAYOUT = 3, + SVGA_COTABLE_BLENDSTATE = 4, + SVGA_COTABLE_DEPTHSTENCIL = 5, SVGA_COTABLE_RASTERIZERSTATE = 6, - SVGA_COTABLE_SAMPLER = 7, - SVGA_COTABLE_STREAMOUTPUT = 8, - SVGA_COTABLE_DXQUERY = 9, - SVGA_COTABLE_DXSHADER = 10, - SVGA_COTABLE_DX10_MAX = 11, - SVGA_COTABLE_UAVIEW = 11, - SVGA_COTABLE_MAX = 12, + SVGA_COTABLE_SAMPLER = 7, + SVGA_COTABLE_STREAMOUTPUT = 8, + SVGA_COTABLE_DXQUERY = 9, + SVGA_COTABLE_DXSHADER = 10, + SVGA_COTABLE_DX10_MAX = 11, + SVGA_COTABLE_UAVIEW = 11, + SVGA_COTABLE_MAX = 12, } SVGACOTableType; - #define SVGA_COTABLE_MAX_IDS (MAX_UINT16 - 2) typedef enum SVGAMobFormat { - SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID, - SVGA3D_MOBFMT_PT_0 = 0, - SVGA3D_MOBFMT_MIN = 0, - SVGA3D_MOBFMT_PT_1 = 1, - SVGA3D_MOBFMT_PT_2 = 2, - SVGA3D_MOBFMT_RANGE = 3, - SVGA3D_MOBFMT_PT64_0 = 4, - SVGA3D_MOBFMT_PT64_1 = 5, - SVGA3D_MOBFMT_PT64_2 = 6, - SVGA3D_MOBFMT_PREDX_MAX = 7, - SVGA3D_MOBFMT_EMPTY = 7, + SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID, + SVGA3D_MOBFMT_PT_0 = 0, + SVGA3D_MOBFMT_MIN = 0, + SVGA3D_MOBFMT_PT_1 = 1, + SVGA3D_MOBFMT_PT_2 = 2, + SVGA3D_MOBFMT_RANGE = 3, + SVGA3D_MOBFMT_PT64_0 = 4, + SVGA3D_MOBFMT_PT64_1 = 5, + SVGA3D_MOBFMT_PT64_2 = 6, + SVGA3D_MOBFMT_PREDX_MAX = 7, + SVGA3D_MOBFMT_EMPTY = 7, + SVGA3D_MOBFMT_MAX, - - SVGA3D_MOBFMT_HB, } SVGAMobFormat; #define SVGA3D_MOB_EMPTY_BASE 1 -/* - * Multisample pattern types. - */ - typedef enum SVGA3dMSPattern { - SVGA3D_MS_PATTERN_NONE = 0, - SVGA3D_MS_PATTERN_MIN = 0, + SVGA3D_MS_PATTERN_NONE = 0, + SVGA3D_MS_PATTERN_MIN = 0, SVGA3D_MS_PATTERN_STANDARD = 1, - SVGA3D_MS_PATTERN_CENTER = 2, - SVGA3D_MS_PATTERN_MAX = 3, + SVGA3D_MS_PATTERN_CENTER = 2, + SVGA3D_MS_PATTERN_MAX = 3, } SVGA3dMSPattern; -/* - * Precision settings for each sample. - */ - typedef enum SVGA3dMSQualityLevel { SVGA3D_MS_QUALITY_NONE = 0, - SVGA3D_MS_QUALITY_MIN = 0, + SVGA3D_MS_QUALITY_MIN = 0, SVGA3D_MS_QUALITY_FULL = 1, SVGA3D_MS_QUALITY_RESOLVED = 2, - SVGA3D_MS_QUALITY_MAX = 3, + SVGA3D_MS_QUALITY_MAX = 3, } SVGA3dMSQualityLevel; - - typedef enum SVGA3dFrameUpdateType { - SVGA3D_FRAME_END = 0, - SVGA3D_FRAME_MIN = 0, + SVGA3D_FRAME_END = 0, + SVGA3D_FRAME_MIN = 0, SVGA3D_FRAME_PARTIAL = 1, SVGA3D_FRAME_UNKNOWN = 2, - SVGA3D_FRAME_MAX = 3, + SVGA3D_FRAME_MAX = 3, } SVGA3dFrameUpdateType; #endif diff --git a/src/gallium/drivers/svga/include/svga_escape.h b/src/gallium/drivers/svga/include/svga_escape.h index bd353f68080..0cef5455154 100644 --- a/src/gallium/drivers/svga/include/svga_escape.h +++ b/src/gallium/drivers/svga/include/svga_escape.h @@ -1,8 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2007-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2007,2020 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* @@ -14,58 +34,22 @@ #ifndef _SVGA_ESCAPE_H_ #define _SVGA_ESCAPE_H_ - -/* - * Namespace IDs for the escape command - */ - #define SVGA_ESCAPE_NSID_VMWARE 0x00000000 #define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF +#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000 -/* - * Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to - * the first DWORD of escape data (after the nsID and size). As a - * guideline we're using the high word and low word as a major and - * minor command number, respectively. - * - * Major command number allocation: - * - * 0000: Reserved - * 0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h) - * 0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h) - * 0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h) - */ +#define SVGA_ESCAPE_VMWARE_HINT 0x00030000 +#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 -#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000 - - -/* - * SVGA Hint commands. - * - * These escapes let the SVGA driver provide optional information to - * he host about the state of the guest or guest applications. The - * host can use these hints to make user interface or performance - * decisions. - * - * Notes: - * - * - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests - * that use the SVGA Screen Object extension. Instead of sending - * this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your - * Screen Object. - */ - -#define SVGA_ESCAPE_VMWARE_HINT 0x00030000 -#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 /* Deprecated */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 command; uint32 fullscreen; struct { int32 x, y; } monitorPosition; } SVGAEscapeHintFullscreen; +#pragma pack(pop) -#endif /* _SVGA_ESCAPE_H_ */ +#endif diff --git a/src/gallium/drivers/svga/include/svga_overlay.h b/src/gallium/drivers/svga/include/svga_overlay.h index 2b3058588f1..e5bd4ffebf0 100644 --- a/src/gallium/drivers/svga/include/svga_overlay.h +++ b/src/gallium/drivers/svga/include/svga_overlay.h @@ -1,8 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 2007-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 2007-2021 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* @@ -16,13 +36,13 @@ #include "svga_reg.h" -/* - * Video formats we support - */ +#if defined __cplusplus +extern "C" { +#endif -#define VMWARE_FOURCC_YV12 0x32315659 /* 'Y' 'V' '1' '2' */ -#define VMWARE_FOURCC_YUY2 0x32595559 /* 'Y' 'U' 'Y' '2' */ -#define VMWARE_FOURCC_UYVY 0x59565955 /* 'U' 'Y' 'V' 'Y' */ +#define VMWARE_FOURCC_YV12 0x32315659 +#define VMWARE_FOURCC_YUY2 0x32595559 +#define VMWARE_FOURCC_UYVY 0x59565955 typedef enum { SVGA_OVERLAY_FORMAT_INVALID = 0, @@ -31,151 +51,66 @@ typedef enum { SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY, } SVGAOverlayFormat; -#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff +#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff -#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000 +#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000 -#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001 - /* FIFO escape layout: - * Type, Stream Id, (Register Id, Value) pairs */ +#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001 -#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002 - /* FIFO escape layout: - * Type, Stream Id */ +#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002 -typedef -struct SVGAEscapeVideoSetRegs { +typedef struct SVGAEscapeVideoSetRegs { struct { uint32 cmdType; uint32 streamId; } header; - /* May include zero or more items. */ struct { uint32 registerId; uint32 value; } items[1]; } SVGAEscapeVideoSetRegs; -typedef -struct SVGAEscapeVideoFlush { +typedef struct SVGAEscapeVideoFlush { uint32 cmdType; uint32 streamId; } SVGAEscapeVideoFlush; - -/* - * Struct definitions for the video overlay commands built on - * SVGAFifoCmdEscape. - */ -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 command; uint32 overlay; } SVGAFifoEscapeCmdVideoBase; +#pragma pack(pop) -typedef -struct { +#pragma pack(push, 1) +typedef struct { SVGAFifoEscapeCmdVideoBase videoCmd; } SVGAFifoEscapeCmdVideoFlush; +#pragma pack(pop) -typedef -struct { +#pragma pack(push, 1) +typedef struct { SVGAFifoEscapeCmdVideoBase videoCmd; struct { uint32 regId; uint32 value; } items[1]; } SVGAFifoEscapeCmdVideoSetRegs; +#pragma pack(pop) -typedef -struct { +#pragma pack(push, 1) +typedef struct { SVGAFifoEscapeCmdVideoBase videoCmd; struct { uint32 regId; uint32 value; } items[SVGA_VIDEO_NUM_REGS]; } SVGAFifoEscapeCmdVideoSetAllRegs; +#pragma pack(pop) - -/* - *---------------------------------------------------------------------- - * - * VMwareVideoGetAttributes -- - * - * Computes the size, pitches and offsets for YUV frames. - * - * Results: - * TRUE on success; otherwise FALSE on failure. - * - * Side effects: - * Pitches and offsets for the given YUV frame are put in 'pitches' - * and 'offsets' respectively. They are both optional though. - * - *---------------------------------------------------------------------- - */ - -static inline Bool -VMwareVideoGetAttributes(const SVGAOverlayFormat format, /* IN */ - uint32 *width, /* IN / OUT */ - uint32 *height, /* IN / OUT */ - uint32 *size, /* OUT */ - uint32 *pitches, /* OUT (optional) */ - uint32 *offsets) /* OUT (optional) */ -{ - int tmp; - - *width = (*width + 1) & ~1; - - if (offsets) { - offsets[0] = 0; - } - - switch (format) { - case VMWARE_FOURCC_YV12: - *height = (*height + 1) & ~1; - *size = (*width) * (*height); - - if (pitches) { - pitches[0] = *width; - } - - if (offsets) { - offsets[1] = *size; - } - - tmp = *width >> 1; - - if (pitches) { - pitches[1] = pitches[2] = tmp; - } - - tmp *= (*height >> 1); - *size += tmp; - - if (offsets) { - offsets[2] = *size; - } - - *size += tmp; - break; - - case VMWARE_FOURCC_YUY2: - case VMWARE_FOURCC_UYVY: - *size = *width * 2; - - if (pitches) { - pitches[0] = *size; - } - - *size *= *height; - break; - - default: - return false; - } - - return true; +#if defined __cplusplus } +#endif -#endif /* _SVGA_OVERLAY_H_ */ +#endif diff --git a/src/gallium/drivers/svga/include/svga_reg.h b/src/gallium/drivers/svga/include/svga_reg.h index dd95343a3cf..9531f33fa15 100644 --- a/src/gallium/drivers/svga/include/svga_reg.h +++ b/src/gallium/drivers/svga/include/svga_reg.h @@ -1,8 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* - * Copyright (c) 1998-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT + * Copyright (c) 1998-2024 Broadcom. All Rights Reserved. The term + * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * */ /* @@ -14,11 +34,8 @@ #ifndef _SVGA_REG_H_ #define _SVGA_REG_H_ -#include "svga_types.h" +#include "vm_basic_types.h" -/* - * SVGA_REG_ENABLE bit definitions. - */ typedef enum { SVGA_REG_ENABLE_DISABLE = 0, SVGA_REG_ENABLE_ENABLE = (1 << 0), @@ -27,82 +44,61 @@ typedef enum { typedef uint32 SVGAMobId; -/* - * Arbitrary and meaningless limits. Please ignore these when writing - * new drivers. - */ -#define SVGA_MAX_WIDTH 2560 -#define SVGA_MAX_HEIGHT 1600 -#define SVGA_MAX_BITS_PER_PIXEL 32 -#define SVGA_MAX_DEPTH 24 -#define SVGA_MAX_DISPLAYS 10 +#define SVGA_MAX_WIDTH 2560 +#define SVGA_MAX_HEIGHT 1600 -/* - * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned - * cursor bypass mode. This is still supported, but no new guest - * drivers should use it. - */ -#define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */ -#define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */ -#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */ -#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ +#define SVGA_MAX_BITS_PER_PIXEL 32 +#define SVGA_MAX_DEPTH 24 +#define SVGA_MAX_DISPLAYS 10 +#define SVGA_MAX_SCREEN_SIZE 8192 +#define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS) -/* - * The maximum framebuffer size that can traced for e.g. guests in VESA mode. - * The changeMap in the monitor is proportional to this number. Therefore, we'd - * like to keep it as small as possible to reduce monitor overhead (using - * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over - * 4k!). - * - * NB: For compatibility reasons, this value must be greater than 0xff0000. - * See bug 335072. - */ -#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 +#define SVGA_CURSOR_ON_HIDE 0x0 +#define SVGA_CURSOR_ON_SHOW 0x1 -#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 -#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) -#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) +#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 -#define SVGA_MAGIC 0x900000UL -#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) +#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 -/* Version 2 let the address of the frame buffer be unsigned on Win32 */ -#define SVGA_VERSION_2 2 -#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2) +#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 -/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so - PALETTE_BASE has moved */ -#define SVGA_VERSION_1 1 -#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1) +#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 +#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) +#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) -/* Version 0 is the initial version */ -#define SVGA_VERSION_0 0 -#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) +#define SVGA_MAGIC 0x900000UL +#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) -/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */ -#define SVGA_ID_INVALID 0xFFFFFFFF +#define SVGA_VERSION_3 3 +#define SVGA_ID_3 SVGA_MAKE_ID(SVGA_VERSION_3) -/* Port offsets, relative to BAR0 */ -#define SVGA_INDEX_PORT 0x0 -#define SVGA_VALUE_PORT 0x1 -#define SVGA_BIOS_PORT 0x2 -#define SVGA_IRQSTATUS_PORT 0x8 +#define SVGA_VERSION_2 2 +#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2) -/* - * Interrupt source flags for IRQSTATUS_PORT and IRQMASK. - * - * Interrupts are only supported when the - * SVGA_CAP_IRQMASK capability is present. - */ -#define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */ -#define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */ -#define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */ -#define SVGA_IRQFLAG_COMMAND_BUFFER 0x8 /* Command buffer completed */ -#define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */ +#define SVGA_VERSION_1 1 +#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1) -/* - * Registers - */ +#define SVGA_VERSION_0 0 +#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) + +#define SVGA_ID_INVALID 0xFFFFFFFF + +#define SVGA_INDEX_PORT 0x0 +#define SVGA_VALUE_PORT 0x1 +#define SVGA_BIOS_PORT 0x2 +#define SVGA_IRQSTATUS_PORT 0x8 + +#define SVGA_IRQFLAG_ANY_FENCE (1 << 0) +#define SVGA_IRQFLAG_FIFO_PROGRESS (1 << 1) +#define SVGA_IRQFLAG_FENCE_GOAL (1 << 2) +#define SVGA_IRQFLAG_COMMAND_BUFFER (1 << 3) +#define SVGA_IRQFLAG_ERROR (1 << 4) +#define SVGA_IRQFLAG_REG_FENCE_GOAL (1 << 5) +#define SVGA_IRQFLAG_MOB_FENCE (1 << 6) +#define SVGA_IRQFLAG_MAX (1 << 7) + +#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024) +#define SVGA_MAX_CURSOR_CMD_DIMENSION 1024 enum { SVGA_REG_ID = 0, @@ -112,301 +108,191 @@ enum { SVGA_REG_MAX_WIDTH = 4, SVGA_REG_MAX_HEIGHT = 5, SVGA_REG_DEPTH = 6, - SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ + SVGA_REG_BITS_PER_PIXEL = 7, SVGA_REG_PSEUDOCOLOR = 8, SVGA_REG_RED_MASK = 9, SVGA_REG_GREEN_MASK = 10, SVGA_REG_BLUE_MASK = 11, SVGA_REG_BYTES_PER_LINE = 12, - SVGA_REG_FB_START = 13, /* (Deprecated) */ + SVGA_REG_FB_START = 13, SVGA_REG_FB_OFFSET = 14, SVGA_REG_VRAM_SIZE = 15, SVGA_REG_FB_SIZE = 16, - /* ID 0 implementation only had the above registers, then the palette */ SVGA_REG_ID_0_TOP = 17, SVGA_REG_CAPABILITIES = 17, - SVGA_REG_MEM_START = 18, /* (Deprecated) */ + SVGA_REG_MEM_START = 18, SVGA_REG_MEM_SIZE = 19, - SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ - SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ - SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ - SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ - SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */ - SVGA_REG_CURSOR_X = 25, /* (Deprecated) */ - SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */ - SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */ - SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */ - SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ - SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ - SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */ - SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ - SVGA_REG_IRQMASK = 33, /* Interrupt mask */ + SVGA_REG_CONFIG_DONE = 20, + SVGA_REG_SYNC = 21, + SVGA_REG_BUSY = 22, + SVGA_REG_GUEST_ID = 23, + SVGA_REG_DEAD = 24, + SVGA_REG_CURSOR_X = 25, + SVGA_REG_CURSOR_Y = 26, + SVGA_REG_CURSOR_ON = 27, + SVGA_REG_HOST_BITS_PER_PIXEL = 28, + SVGA_REG_SCRATCH_SIZE = 29, + SVGA_REG_MEM_REGS = 30, + SVGA_REG_NUM_DISPLAYS = 31, + SVGA_REG_PITCHLOCK = 32, + SVGA_REG_IRQMASK = 33, - /* Legacy multi-monitor support */ - SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */ - SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */ - SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */ - SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */ - SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */ - SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ - SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ + SVGA_REG_NUM_GUEST_DISPLAYS = 34, + SVGA_REG_DISPLAY_ID = 35, + SVGA_REG_DISPLAY_IS_PRIMARY = 36, + SVGA_REG_DISPLAY_POSITION_X = 37, + SVGA_REG_DISPLAY_POSITION_Y = 38, + SVGA_REG_DISPLAY_WIDTH = 39, + SVGA_REG_DISPLAY_HEIGHT = 40, - /* See "Guest memory regions" below. */ SVGA_REG_GMR_ID = 41, SVGA_REG_GMR_DESCRIPTOR = 42, SVGA_REG_GMR_MAX_IDS = 43, SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44, - SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ - SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ - SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ - SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */ - SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */ - SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ - SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */ - SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ + SVGA_REG_TRACES = 45, + SVGA_REG_GMRS_MAX_PAGES = 46, + SVGA_REG_MEMORY_SIZE = 47, + SVGA_REG_COMMAND_LOW = 48, + SVGA_REG_COMMAND_HIGH = 49, + + SVGA_REG_MAX_PRIMARY_MEM = 50, + + SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, + + SVGA_REG_DEV_CAP = 52, SVGA_REG_CMD_PREPEND_LOW = 53, - SVGA_REG_iCMD_PREPEND_HIGH = 54, + SVGA_REG_CMD_PREPEND_HIGH = 54, SVGA_REG_SCREENTARGET_MAX_WIDTH = 55, SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56, SVGA_REG_MOB_MAX_SIZE = 57, SVGA_REG_BLANK_SCREEN_TARGETS = 58, SVGA_REG_CAP2 = 59, - SVGA_REG_TOP = 60, /* Must be 1 more than the last register */ + SVGA_REG_DEVEL_CAP = 60, + + SVGA_REG_GUEST_DRIVER_ID = 61, + SVGA_REG_GUEST_DRIVER_VERSION1 = 62, + SVGA_REG_GUEST_DRIVER_VERSION2 = 63, + SVGA_REG_GUEST_DRIVER_VERSION3 = 64, + + SVGA_REG_CURSOR_MOBID = 65, + SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66, + SVGA_REG_CURSOR_MAX_DIMENSION = 67, + + SVGA_REG_FIFO_CAPS = 68, + SVGA_REG_FENCE = 69, + + SVGA_REG_CURSOR4_ON = 70, + SVGA_REG_CURSOR4_X = 71, + SVGA_REG_CURSOR4_Y = 72, + SVGA_REG_CURSOR4_SCREEN_ID = 73, + SVGA_REG_CURSOR4_SUBMIT = 74, + + SVGA_REG_SCREENDMA = 75, + + SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76, + + SVGA_REG_REGS_START_HIGH32 = 77, + SVGA_REG_REGS_START_LOW32 = 78, + SVGA_REG_FB_START_HIGH32 = 79, + SVGA_REG_FB_START_LOW32 = 80, + + SVGA_REG_MSHINT = 81, + + SVGA_REG_IRQ_STATUS = 82, + + SVGA_REG_DIRTY_TRACKING = 83, + SVGA_REG_FENCE_GOAL = 84, + + SVGA_REG_TOP = 85, + + SVGA_PALETTE_BASE = 1024, - SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ - /* Next 768 (== 256*3) registers exist for colormap */ SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS - /* Base of scratch registers */ - /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: - First 4 are reserved for VESA BIOS Extension; any remaining are for - the use of the current SVGA driver. */ + }; -/* - * Guest memory regions (GMRs): - * - * This is a new memory mapping feature available in SVGA devices - * which have the SVGA_CAP_GMR bit set. Previously, there were two - * fixed memory regions available with which to share data between the - * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs - * are our name for an extensible way of providing arbitrary DMA - * buffers for use between the driver and the SVGA device. They are a - * new alternative to framebuffer memory, usable for both 2D and 3D - * graphics operations. - * - * Since GMR mapping must be done synchronously with guest CPU - * execution, we use a new pair of SVGA registers: - * - * SVGA_REG_GMR_ID -- - * - * Read/write. - * This register holds the 32-bit ID (a small positive integer) - * of a GMR to create, delete, or redefine. Writing this register - * has no side-effects. - * - * SVGA_REG_GMR_DESCRIPTOR -- - * - * Write-only. - * Writing this register will create, delete, or redefine the GMR - * specified by the above ID register. If this register is zero, - * the GMR is deleted. Any pointers into this GMR (including those - * currently being processed by FIFO commands) will be - * synchronously invalidated. - * - * If this register is nonzero, it must be the physical page - * number (PPN) of a data structure which describes the physical - * layout of the memory region this GMR should describe. The - * descriptor structure will be read synchronously by the SVGA - * device when this register is written. The descriptor need not - * remain allocated for the lifetime of the GMR. - * - * The guest driver should write SVGA_REG_GMR_ID first, then - * SVGA_REG_GMR_DESCRIPTOR. - * - * SVGA_REG_GMR_MAX_IDS -- - * - * Read-only. - * The SVGA device may choose to support a maximum number of - * user-defined GMR IDs. This register holds the number of supported - * IDs. (The maximum supported ID plus 1) - * - * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH -- - * - * Read-only. - * The SVGA device may choose to put a limit on the total number - * of SVGAGuestMemDescriptor structures it will read when defining - * a single GMR. - * - * The descriptor structure is an array of SVGAGuestMemDescriptor - * structures. Each structure may do one of three things: - * - * - Terminate the GMR descriptor list. - * (ppn==0, numPages==0) - * - * - Add a PPN or range of PPNs to the GMR's virtual address space. - * (ppn != 0, numPages != 0) - * - * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to - * support multi-page GMR descriptor tables without forcing the - * driver to allocate physically contiguous memory. - * (ppn != 0, numPages == 0) - * - * Note that each physical page of SVGAGuestMemDescriptor structures - * can describe at least 2MB of guest memory. If the driver needs to - * use more than one page of descriptor structures, it must use one of - * its SVGAGuestMemDescriptors to point to an additional page. The - * device will never automatically cross a page boundary. - * - * Once the driver has described a GMR, it is immediately available - * for use via any FIFO command that uses an SVGAGuestPtr structure. - * These pointers include a GMR identifier plus an offset into that - * GMR. - * - * The driver must check the SVGA_CAP_GMR bit before using the GMR - * registers. - */ +typedef enum SVGARegGuestDriverId { + SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0, + SVGA_REG_GUEST_DRIVER_ID_WDDM = 1, + SVGA_REG_GUEST_DRIVER_ID_LINUX = 2, + SVGA_REG_GUEST_DRIVER_ID_MAX, -/* - * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer - * memory as well. In the future, these IDs could even be used to - * allow legacy memory regions to be redefined by the guest as GMRs. - * - * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA - * is being phased out. Please try to use user-defined GMRs whenever - * possible. - */ -#define SVGA_GMR_NULL ((uint32) -1) -#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) // Guest Framebuffer (GFB) + SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32, +} SVGARegGuestDriverId; -typedef -struct SVGAGuestMemDescriptor { +typedef enum SVGARegMSHint { + SVGA_REG_MSHINT_DISABLED = 0, + SVGA_REG_MSHINT_FULL = 1, + SVGA_REG_MSHINT_RESOLVED = 2, +} SVGARegMSHint; + +typedef enum SVGARegDirtyTracking { + SVGA_REG_DIRTY_TRACKING_PER_IMAGE = 0, + SVGA_REG_DIRTY_TRACKING_PER_SURFACE = 1, +} SVGARegDirtyTracking; + +#define SVGA_GMR_NULL ((uint32) - 1) +#define SVGA_GMR_FRAMEBUFFER ((uint32) - 2) + +#pragma pack(push, 1) +typedef struct SVGAGuestMemDescriptor { uint32 ppn; uint32 numPages; } SVGAGuestMemDescriptor; +#pragma pack(pop) -typedef -struct SVGAGuestPtr { +#pragma pack(push, 1) +typedef struct SVGAGuestPtr { uint32 gmrId; uint32 offset; } SVGAGuestPtr; +#pragma pack(pop) -/* - * Register based command buffers -- - * - * Provide an SVGA device interface that allows the guest to submit - * command buffers to the SVGA device through an SVGA device register. - * The metadata for each command buffer is contained in the - * SVGACBHeader structure along with the return status codes. - * - * The SVGA device supports command buffers if - * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The - * fifo must be enabled for command buffers to be submitted. - * - * Command buffers are submitted when the guest writing the 64 byte - * aligned physical address into the SVGA_REG_COMMAND_LOW and - * SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32 - * bits of the physical address. SVGA_REG_COMMAND_LOW contains the - * lower 32 bits of the physical address, since the command buffer - * headers are required to be 64 byte aligned the lower 6 bits are - * used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW - * submits the command buffer to the device and queues it for - * execution. The SVGA device supports at least - * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued - * per context and if that limit is reached the device will write the - * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command - * buffer header synchronously and not raise any IRQs. - * - * It is invalid to submit a command buffer without a valid physical - * address and results are undefined. - * - * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE - * will be supported. If a larger command buffer is submitted results - * are unspecified and the device will either complete the command - * buffer or return an error. - * - * The device guarantees that any individual command in a command - * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is - * enough to fit a 64x64 color-cursor definition. If the command is - * too large the device is allowed to process the command or return an - * error. - * - * The device context is a special SVGACBContext that allows for - * synchronous register like accesses with the flexibility of - * commands. There is a different command set defined by - * SVGADeviceContextCmdId. The commands in each command buffer is not - * allowed to straddle physical pages. - */ - -#define SVGA_CB_MAX_SIZE (512 * 1024) // 512 KB +#define SVGA_CB_MAX_SIZE_DEFAULT (KBYTES_2_BYTES(512)) +#define SVGA_CB_MAX_SIZE_4MB (MBYTES_2_BYTES(4)) +#define SVGA_CB_MAX_SIZE SVGA_CB_MAX_SIZE_4MB #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32 -#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB +#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) #define SVGA_CB_CONTEXT_MASK 0x3f typedef enum { SVGA_CB_CONTEXT_DEVICE = 0x3f, - SVGA_CB_CONTEXT_0 = 0x0, - SVGA_CB_CONTEXT_MAX = 0x1, + SVGA_CB_CONTEXT_0 = 0x0, + SVGA_CB_CONTEXT_1 = 0x1, + SVGA_CB_CONTEXT_MAX = 0x2, } SVGACBContext; - typedef enum { - /* - * The guest is supposed to write SVGA_CB_STATUS_NONE to the status - * field before submitting the command buffer header, the host will - * change the value when it is done with the command buffer. - */ - SVGA_CB_STATUS_NONE = 0, - /* - * Written by the host when a command buffer completes successfully. - * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless - * the SVGA_CB_FLAG_NO_IRQ flag is set. - */ - SVGA_CB_STATUS_COMPLETED = 1, + SVGA_CB_STATUS_NONE = 0, - /* - * Written by the host synchronously with the command buffer - * submission to indicate the command buffer was not submitted. No - * IRQ is raised. - */ - SVGA_CB_STATUS_QUEUE_FULL = 2, + SVGA_CB_STATUS_COMPLETED = 1, - /* - * Written by the host when an error was detected parsing a command - * in the command buffer, errorOffset is written to contain the - * offset to the first byte of the failing command. The device - * raises the IRQ with both SVGA_IRQFLAG_ERROR and - * SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been - * processed. - */ - SVGA_CB_STATUS_COMMAND_ERROR = 3, + SVGA_CB_STATUS_QUEUE_FULL = 2, - /* - * Written by the host if there is an error parsing the command - * buffer header. The device raises the IRQ with both - * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device - * did not processes any of the command buffer. - */ - SVGA_CB_STATUS_CB_HEADER_ERROR = 4, + SVGA_CB_STATUS_COMMAND_ERROR = 3, - /* - * Written by the host if the guest requested the host to preempt - * the command buffer. The device will not raise any IRQs and the - * command buffer was not processed. - */ - SVGA_CB_STATUS_PREEMPTED = 5, + SVGA_CB_STATUS_CB_HEADER_ERROR = 4, + + SVGA_CB_STATUS_PREEMPTED = 5, + + SVGA_CB_STATUS_SUBMISSION_ERROR = 6, + + SVGA_CB_STATUS_PARTIAL_COMPLETE = 7, } SVGACBStatus; typedef enum { - SVGA_CB_FLAG_NONE = 0, - SVGA_CB_FLAG_NO_IRQ = 1 << 0, + SVGA_CB_FLAG_NONE = 0, + SVGA_CB_FLAG_NO_IRQ = 1 << 0, + SVGA_CB_FLAG_DX_CONTEXT = 1 << 1, + SVGA_CB_FLAG_MOB = 1 << 2, } SVGACBFlags; -typedef -struct { +#pragma pack(push, 1) +typedef struct { volatile SVGACBStatus status; volatile uint32 errorOffset; uint64 id; @@ -414,104 +300,68 @@ struct { uint32 length; union { PA pa; + struct { + SVGAMobId mobid; + uint32 mobOffset; + } mob; } ptr; - uint32 mustBeZero[8]; + uint32 offset; + uint32 dxContext; + uint32 mustBeZero[6]; } SVGACBHeader; +#pragma pack(pop) typedef enum { - SVGA_DC_CMD_NOP = 0, - SVGA_DC_CMD_START_STOP_CONTEXT = 1, - SVGA_DC_CMD_PREEMPT = 2, - SVGA_DC_CMD_MAX = 3, - SVGA_DC_CMD_FORCE_UINT = MAX_UINT32, + SVGA_DC_CMD_NOP = 0, + SVGA_DC_CMD_START_STOP_CONTEXT = 1, + SVGA_DC_CMD_PREEMPT = 2, + SVGA_DC_CMD_START_QUEUE = 3, + SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4, + SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5, + SVGA_DC_CMD_MAX = 6 } SVGADeviceContextCmdId; -typedef struct { +typedef struct SVGADCCmdStartStop { uint32 enable; SVGACBContext context; } SVGADCCmdStartStop; -/* - * SVGADCCmdPreempt -- - * - * This command allows the guest to request that all command buffers - * on the specified context be preempted that can be. After execution - * of this command all command buffers that were preempted will - * already have SVGA_CB_STATUS_PREEMPTED written into the status - * field. The device might still be processing a command buffer, - * assuming execution of it started before the preemption request was - * received. Specifying the ignoreIDZero flag to TRUE will cause the - * device to not preempt command buffers with the id field in the - * command buffer header set to zero. - */ - -typedef struct { +typedef struct SVGADCCmdPreempt { SVGACBContext context; uint32 ignoreIDZero; } SVGADCCmdPreempt; +typedef struct SVGADCCmdStartQueue { + SVGACBContext context; +} SVGADCCmdStartQueue; -/* - * SVGAGMRImageFormat -- - * - * This is a packed representation of the source 2D image format - * for a GMR-to-screen blit. Currently it is defined as an encoding - * of the screen's color depth and bits-per-pixel, however, 16 bits - * are reserved for future use to identify other encodings (such as - * RGBA or higher-precision images). - * - * Currently supported formats: - * - * bpp depth Format Name - * --- ----- ----------- - * 32 24 32-bit BGRX - * 24 24 24-bit BGR - * 16 16 RGB 5-6-5 - * 16 15 RGB 5-5-5 - * - */ +typedef struct SVGADCCmdAsyncStopQueue { + SVGACBContext context; +} SVGADCCmdAsyncStopQueue; + +typedef struct SVGADCCmdEmptyQueue { + SVGACBContext context; +} SVGADCCmdEmptyQueue; typedef struct SVGAGMRImageFormat { union { struct { uint32 bitsPerPixel : 8; uint32 colorDepth : 8; - uint32 reserved : 16; /* Must be zero */ + uint32 reserved : 16; }; uint32 value; }; } SVGAGMRImageFormat; -typedef -struct SVGAGuestImage { - SVGAGuestPtr ptr; +#pragma pack(push, 1) +typedef struct SVGAGuestImage { + SVGAGuestPtr ptr; - /* - * A note on interpretation of pitch: This value of pitch is the - * number of bytes between vertically adjacent image - * blocks. Normally this is the number of bytes between the first - * pixel of two adjacent scanlines. With compressed textures, - * however, this may represent the number of bytes between - * compression blocks rather than between rows of pixels. - * - * XXX: Compressed textures currently must be tightly packed in guest memory. - * - * If the image is 1-dimensional, pitch is ignored. - * - * If 'pitch' is zero, the SVGA3D device calculates a pitch value - * assuming each row of blocks is tightly packed. - */ uint32 pitch; } SVGAGuestImage; - -/* - * SVGAColorBGRX -- - * - * A 24-bit color format (BGRX), which does not depend on the - * format of the legacy guest framebuffer (GFB) or the current - * GMRFB state. - */ +#pragma pack(pop) typedef struct SVGAColorBGRX { union { @@ -519,582 +369,183 @@ typedef struct SVGAColorBGRX { uint32 b : 8; uint32 g : 8; uint32 r : 8; - uint32 x : 8; /* Unused */ + uint32 x : 8; }; uint32 value; }; } SVGAColorBGRX; - -/* - * SVGASignedRect -- - * SVGASignedPoint -- - * - * Signed rectangle and point primitives. These are used by the new - * 2D primitives for drawing to Screen Objects, which can occupy a - * signed virtual coordinate space. - * - * SVGASignedRect specifies a half-open interval: the (left, top) - * pixel is part of the rectangle, but the (right, bottom) pixel is - * not. - */ - -typedef -struct { - int32 left; - int32 top; - int32 right; - int32 bottom; +#pragma pack(push, 1) +typedef struct { + int32 left; + int32 top; + int32 right; + int32 bottom; } SVGASignedRect; +#pragma pack(pop) -typedef -struct { - int32 x; - int32 y; +#pragma pack(push, 1) +typedef struct { + int32 x; + int32 y; } SVGASignedPoint; +#pragma pack(pop) -typedef -struct { - uint32 x; - uint32 y; +#pragma pack(push, 1) +typedef struct { + uint32 x; + uint32 y; } SVGAUnsignedPoint; +#pragma pack(pop) -/* - * SVGA Device Capabilities - * - * Note the holes in the bitfield. Missing bits have been deprecated, - * and must not be reused. Those capabilities will never be reported - * by new versions of the SVGA device. - * - * XXX: Add longer descriptions for each capability, including a list - * of the new features that each capability provides. - * - * SVGA_CAP_IRQMASK -- - * Provides device interrupts. Adds device register SVGA_REG_IRQMASK - * to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to - * set/clear pending interrupts. - * - * SVGA_CAP_GMR -- - * Provides synchronous mapping of guest memory regions (GMR). - * Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR, - * SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH. - * - * SVGA_CAP_TRACES -- - * Allows framebuffer trace-based updates even when FIFO is enabled. - * Adds device register SVGA_REG_TRACES. - * - * SVGA_CAP_GMR2 -- - * Provides asynchronous commands to define and remap guest memory - * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and - * SVGA_REG_MEMORY_SIZE. - * - * SVGA_CAP_SCREEN_OBJECT_2 -- - * Allow screen object support, and require backing stores from the - * guest for each screen object. - * - * SVGA_CAP_COMMAND_BUFFERS -- - * Enable register based command buffer submission. - * - * SVGA_CAP_DEAD1 -- - * This cap was incorrectly used by old drivers and should not be - * reused. - * - * SVGA_CAP_CMD_BUFFERS_2 -- - * Enable support for the prepend command buffer submission - * registers. SVGA_REG_CMD_PREPEND_LOW and - * SVGA_REG_CMD_PREPEND_HIGH. - * - * SVGA_CAP_GBOBJECTS -- - * Enable guest-backed objects and surfaces. - * - * SVGA_CAP_CMD_BUFFERS_3 -- - * Enable support for command buffers in a mob. - */ +#define SVGA_CAP_NONE 0x00000000 +#define SVGA_CAP_RECT_COPY 0x00000002 +#define SVGA_CAP_CURSOR 0x00000020 +#define SVGA_CAP_CURSOR_BYPASS 0x00000040 +#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 +#define SVGA_CAP_8BIT_EMULATION 0x00000100 +#define SVGA_CAP_ALPHA_CURSOR 0x00000200 +#define SVGA_CAP_3D 0x00004000 +#define SVGA_CAP_EXTENDED_FIFO 0x00008000 +#define SVGA_CAP_MULTIMON 0x00010000 +#define SVGA_CAP_PITCHLOCK 0x00020000 +#define SVGA_CAP_IRQMASK 0x00040000 +#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 +#define SVGA_CAP_GMR 0x00100000 +#define SVGA_CAP_TRACES 0x00200000 +#define SVGA_CAP_GMR2 0x00400000 +#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 +#define SVGA_CAP_COMMAND_BUFFERS 0x01000000 +#define SVGA_CAP_DEAD1 0x02000000 +#define SVGA_CAP_CMD_BUFFERS_2 0x04000000 +#define SVGA_CAP_GBOBJECTS 0x08000000 +#define SVGA_CAP_DX 0x10000000 +#define SVGA_CAP_HP_CMD_QUEUE 0x20000000 +#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000 +#define SVGA_CAP_CAP2_REGISTER 0x80000000 -#define SVGA_CAP_NONE 0x00000000 -#define SVGA_CAP_RECT_COPY 0x00000002 -#define SVGA_CAP_CURSOR 0x00000020 -#define SVGA_CAP_CURSOR_BYPASS 0x00000040 -#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 -#define SVGA_CAP_8BIT_EMULATION 0x00000100 -#define SVGA_CAP_ALPHA_CURSOR 0x00000200 -#define SVGA_CAP_3D 0x00004000 -#define SVGA_CAP_EXTENDED_FIFO 0x00008000 -#define SVGA_CAP_MULTIMON 0x00010000 -#define SVGA_CAP_PITCHLOCK 0x00020000 -#define SVGA_CAP_IRQMASK 0x00040000 -#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 -#define SVGA_CAP_GMR 0x00100000 -#define SVGA_CAP_TRACES 0x00200000 -#define SVGA_CAP_GMR2 0x00400000 -#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 -#define SVGA_CAP_COMMAND_BUFFERS 0x01000000 -#define SVGA_CAP_DEAD1 0x02000000 -#define SVGA_CAP_CMD_BUFFERS_2 0x04000000 -#define SVGA_CAP_GBOBJECTS 0x08000000 -#define SVGA_CAP_CMD_BUFFERS_3 0x10000000 - -#define SVGA_CAP_CAP2_REGISTER 0x80000000 - - -/* - * The SVGA_REG_CAP2 register is an additional set of SVGA capability bits. - * - * SVGA_CAP2_GROW_OTABLE -- - * Allow the GrowOTable/DXGrowCOTable commands. - * - * SVGA_CAP2_INTRA_SURFACE_COPY -- - * Allow the IntraSurfaceCopy command. - * - * SVGA_CAP2_RESERVED -- - * Reserve the last bit for extending the SVGA capabilities to some - * future mechanisms. - */ -#define SVGA_CAP2_NONE 0x00000000 -#define SVGA_CAP2_GROW_OTABLE 0x00000001 -#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002 -#define SVGA_CAP2_RESERVED 0x80000000 - -/* - * The Guest can optionally read some SVGA device capabilities through - * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before - * the SVGA device is initialized. The type of capability the guest - * is requesting from the SVGABackdoorCapType enum should be placed in - * the upper 16 bits of the backdoor command id (ECX). On success the - * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to - * the requested capability. If the command is not supported then EBX - * will be left unchanged and EAX will be set to -1. Because it is - * possible that -1 is the value of the requested cap the correct way - * to check if the command was successful is to check if EBX was changed - * to BDOOR_MAGIC making sure to initialize the register to something - * else first. - */ +#define SVGA_CAP2_NONE 0x00000000 +#define SVGA_CAP2_GROW_OTABLE 0x00000001 +#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002 +#define SVGA_CAP2_DX2 0x00000004 +#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008 +#define SVGA_CAP2_SCREENDMA_REG 0x00000010 +#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020 +#define SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT 0x00000040 +#define SVGA_CAP2_CURSOR_MOB 0x00000080 +#define SVGA_CAP2_MSHINT 0x00000100 +#define SVGA_CAP2_CB_MAX_SIZE_4MB 0x00000200 +#define SVGA_CAP2_DX3 0x00000400 +#define SVGA_CAP2_FRAME_TYPE 0x00000800 +#define SVGA_CAP2_COTABLE_COPY 0x00001000 +#define SVGA_CAP2_TRACE_FULL_FB 0x00002000 +#define SVGA_CAP2_EXTRA_REGS 0x00004000 +#define SVGA_CAP2_LO_STAGING 0x00008000 +#define SVGA_CAP2_VIDEO_BLT 0x00010000 +#define SVGA_CAP2_MOBFMT_16K_PT64 0x00020000 +#define SVGA_CAP2_MOB_FENCE_WITH_FLAGS 0x00040000 +#define SVGA_CAP2_DIRTY_TRACKING_REG 0x00080000 +#define SVGA_CAP2_CURSOR_MOB_ALPHA3D 0x00100000 +#define SVGA_CAP2_RESERVED 0x80000000 typedef enum { SVGABackdoorCapDeviceCaps = 0, SVGABackdoorCapFifoCaps = 1, SVGABackdoorCap3dHWVersion = 2, - SVGABackdoorCapMax = 3, + SVGABackdoorCapDeviceCaps2 = 3, + SVGABackdoorCapDevelCaps = 4, + SVGABackdoorCapDevCaps = 5, + SVGABackdoorDevelRenderer = 6, + SVGABackdoorDevelUsingISB = 7, + SVGABackdoorCapMax = 8, } SVGABackdoorCapType; - -/* - * FIFO register indices. - * - * The FIFO is a chunk of device memory mapped into guest physmem. It - * is always treated as 32-bit words. - * - * The guest driver gets to decide how to partition it between - * - FIFO registers (there are always at least 4, specifying where the - * following data area is and how much data it contains; there may be - * more registers following these, depending on the FIFO protocol - * version in use) - * - FIFO data, written by the guest and slurped out by the VMX. - * These indices are 32-bit word offsets into the FIFO. - */ - enum { - /* - * Block 1 (basic registers): The originally defined FIFO registers. - * These exist and are valid for all versions of the FIFO protocol. - */ SVGA_FIFO_MIN = 0, - SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ + SVGA_FIFO_MAX, SVGA_FIFO_NEXT_CMD, SVGA_FIFO_STOP, - /* - * Block 2 (extended registers): Mandatory registers for the extended - * FIFO. These exist if the SVGA caps register includes - * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their - * associated capability bit is enabled. - * - * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied - * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE. - * This means that the guest has to test individually (in most cases - * using FIFO caps) for the presence of registers after this; the VMX - * can define "extended FIFO" to mean whatever it wants, and currently - * won't enable it unless there's room for that set and much more. - */ - SVGA_FIFO_CAPABILITIES = 4, SVGA_FIFO_FLAGS, - /* Valid with SVGA_FIFO_CAP_FENCE: */ + SVGA_FIFO_FENCE, - /* - * Block 3a (optional extended registers): Additional registers for the - * extended FIFO, whose presence isn't actually implied by - * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to - * leave room for them. - * - * These in block 3a, the VMX currently considers mandatory for the - * extended FIFO. - */ + SVGA_FIFO_3D_HWVERSION, - /* Valid if exists (i.e. if extended FIFO enabled): */ - SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */ - /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */ SVGA_FIFO_PITCHLOCK, - /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */ - SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ - SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ - SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ - SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */ - SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */ + SVGA_FIFO_CURSOR_ON, + SVGA_FIFO_CURSOR_X, + SVGA_FIFO_CURSOR_Y, + SVGA_FIFO_CURSOR_COUNT, + SVGA_FIFO_CURSOR_LAST_UPDATED, - /* Valid with SVGA_FIFO_CAP_RESERVE: */ - SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */ + SVGA_FIFO_RESERVED, - /* - * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2: - * - * By default this is SVGA_ID_INVALID, to indicate that the cursor - * coordinates are specified relative to the virtual root. If this - * is set to a specific screen ID, cursor position is reinterpreted - * as a signed offset relative to that screen's origin. - */ SVGA_FIFO_CURSOR_SCREEN_ID, - /* - * Valid with SVGA_FIFO_CAP_DEAD - * - * An arbitrary value written by the host, drivers should not use it. - */ SVGA_FIFO_DEAD, - /* - * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED: - * - * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h) - * on platforms that can enforce graphics resource limits. - */ SVGA_FIFO_3D_HWVERSION_REVISED, - /* - * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new - * registers, but this must be done carefully and with judicious use of - * capability bits, since comparisons based on SVGA_FIFO_MIN aren't - * enough to tell you whether the register exists: we've shipped drivers - * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of - * the earlier ones. The actual order of introduction was: - * - PITCHLOCK - * - 3D_CAPS - * - CURSOR_* (cursor bypass 3) - * - RESERVED - * So, code that wants to know whether it can use any of the - * aforementioned registers, or anything else added after PITCHLOCK and - * before 3D_CAPS, needs to reason about something other than - * SVGA_FIFO_MIN. - */ - - /* - * 3D caps block space; valid with 3D hardware version >= - * SVGA3D_HWVERSION_WS6_B1. - */ - SVGA_FIFO_3D_CAPS = 32, + SVGA_FIFO_3D_CAPS = 32, SVGA_FIFO_3D_CAPS_LAST = 32 + 255, - /* - * End of VMX's current definition of "extended-FIFO registers". - * Registers before here are always enabled/disabled as a block; either - * the extended FIFO is enabled and includes all preceding registers, or - * it's disabled entirely. - * - * Block 3b (truly optional extended registers): Additional registers for - * the extended FIFO, which the VMX already knows how to enable and - * disable with correct granularity. - * - * Registers after here exist if and only if the guest SVGA driver - * sets SVGA_FIFO_MIN high enough to leave room for them. - */ + SVGA_FIFO_GUEST_3D_HWVERSION, + SVGA_FIFO_FENCE_GOAL, + SVGA_FIFO_BUSY, - /* Valid if register exists: */ - SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */ - SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */ - SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */ - - /* - * Always keep this last. This defines the maximum number of - * registers we know about. At power-on, this value is placed in - * the SVGA_REG_MEM_REGS register, and we expect the guest driver - * to allocate this much space in FIFO memory for registers. - */ - SVGA_FIFO_NUM_REGS + SVGA_FIFO_NUM_REGS }; +#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - SVGA_FIFO_3D_CAPS + 1) -/* - * Definition of registers included in extended FIFO support. - * - * The guest SVGA driver gets to allocate the FIFO between registers - * and data. It must always allocate at least 4 registers, but old - * drivers stopped there. - * - * The VMX will enable extended FIFO support if and only if the guest - * left enough room for all registers defined as part of the mandatory - * set for the extended FIFO. - * - * Note that the guest drivers typically allocate the FIFO only at - * initialization time, not at mode switches, so it's likely that the - * number of FIFO registers won't change without a reboot. - * - * All registers less than this value are guaranteed to be present if - * svgaUser->fifo.extended is set. Any later registers must be tested - * individually for compatibility at each use (in the VMX). - * - * This value is used only by the VMX, so it can change without - * affecting driver compatibility; keep it that way? - */ -#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1) +#define SVGA3D_FIFO_CAPS_RECORD_DEVCAPS 0x100 +typedef uint32 SVGA3dFifoCapsRecordType; +typedef uint32 SVGA3dFifoCapPair[2]; -/* - * FIFO Synchronization Registers - * - * This explains the relationship between the various FIFO - * sync-related registers in IOSpace and in FIFO space. - * - * SVGA_REG_SYNC -- - * - * The SYNC register can be used in two different ways by the guest: - * - * 1. If the guest wishes to fully sync (drain) the FIFO, - * it will write once to SYNC then poll on the BUSY - * register. The FIFO is synced once BUSY is zero. - * - * 2. If the guest wants to asynchronously wake up the host, - * it will write once to SYNC without polling on BUSY. - * Ideally it will do this after some new commands have - * been placed in the FIFO, and after reading a zero - * from SVGA_FIFO_BUSY. - * - * (1) is the original behaviour that SYNC was designed to - * support. Originally, a write to SYNC would implicitly - * trigger a read from BUSY. This causes us to synchronously - * process the FIFO. - * - * This behaviour has since been changed so that writing SYNC - * will *not* implicitly cause a read from BUSY. Instead, it - * makes a channel call which asynchronously wakes up the MKS - * thread. - * - * New guests can use this new behaviour to implement (2) - * efficiently. This lets guests get the host's attention - * without waiting for the MKS to poll, which gives us much - * better CPU utilization on SMP hosts and on UP hosts while - * we're blocked on the host GPU. - * - * Old guests shouldn't notice the behaviour change. SYNC was - * never guaranteed to process the entire FIFO, since it was - * bounded to a particular number of CPU cycles. Old guests will - * still loop on the BUSY register until the FIFO is empty. - * - * Writing to SYNC currently has the following side-effects: - * - * - Sets SVGA_REG_BUSY to TRUE (in the monitor) - * - Asynchronously wakes up the MKS thread for FIFO processing - * - The value written to SYNC is recorded as a "reason", for - * stats purposes. - * - * If SVGA_FIFO_BUSY is available, drivers are advised to only - * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set - * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will - * eventually set SVGA_FIFO_BUSY on its own, but this approach - * lets the driver avoid sending multiple asynchronous wakeup - * messages to the MKS thread. - * - * SVGA_REG_BUSY -- - * - * This register is set to TRUE when SVGA_REG_SYNC is written, - * and it reads as FALSE when the FIFO has been completely - * drained. - * - * Every read from this register causes us to synchronously - * process FIFO commands. There is no guarantee as to how many - * commands each read will process. - * - * CPU time spent processing FIFO commands will be billed to - * the guest. - * - * New drivers should avoid using this register unless they - * need to guarantee that the FIFO is completely drained. It - * is overkill for performing a sync-to-fence. Older drivers - * will use this register for any type of synchronization. - * - * SVGA_FIFO_BUSY -- - * - * This register is a fast way for the guest driver to check - * whether the FIFO is already being processed. It reads and - * writes at normal RAM speeds, with no monitor intervention. - * - * If this register reads as TRUE, the host is guaranteeing that - * any new commands written into the FIFO will be noticed before - * the MKS goes back to sleep. - * - * If this register reads as FALSE, no such guarantee can be - * made. - * - * The guest should use this register to quickly determine - * whether or not it needs to wake up the host. If the guest - * just wrote a command or group of commands that it would like - * the host to begin processing, it should: - * - * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further - * action is necessary. - * - * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest - * code that we've already sent a SYNC to the host and we - * don't need to send a duplicate. - * - * 3. Write a reason to SVGA_REG_SYNC. This will send an - * asynchronous wakeup to the MKS thread. - */ +#pragma pack(push, 1) +typedef struct SVGA3dFifoCapsRecordHeader { + uint32 length; + SVGA3dFifoCapsRecordType type; +} SVGA3dFifoCapsRecordHeader; +#pragma pack(pop) -/* - * FIFO Capabilities - * - * Fence -- Fence register and command are supported - * Accel Front -- Front buffer only commands are supported - * Pitch Lock -- Pitch lock register is supported - * Video -- SVGA Video overlay units are supported - * Escape -- Escape command is supported - * - * XXX: Add longer descriptions for each capability, including a list - * of the new features that each capability provides. - * - * SVGA_FIFO_CAP_SCREEN_OBJECT -- - * - * Provides dynamic multi-screen rendering, for improved Unity and - * multi-monitor modes. With Screen Object, the guest can - * dynamically create and destroy 'screens', which can represent - * Unity windows or virtual monitors. Screen Object also provides - * strong guarantees that DMA operations happen only when - * guest-initiated. Screen Object deprecates the BAR1 guest - * framebuffer (GFB) and all commands that work only with the GFB. - * - * New registers: - * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID - * - * New 2D commands: - * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN, - * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY - * - * New 3D commands: - * BLIT_SURFACE_TO_SCREEN - * - * New guarantees: - * - * - The host will not read or write guest memory, including the GFB, - * except when explicitly initiated by a DMA command. - * - * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK, - * is guaranteed to complete before any subsequent FENCEs. - * - * - All legacy commands which affect a Screen (UPDATE, PRESENT, - * PRESENT_READBACK) as well as new Screen blit commands will - * all behave consistently as blits, and memory will be read - * or written in FIFO order. - * - * For example, if you PRESENT from one SVGA3D surface to multiple - * places on the screen, the data copied will always be from the - * SVGA3D surface at the time the PRESENT was issued in the FIFO. - * This was not necessarily true on devices without Screen Object. - * - * This means that on devices that support Screen Object, the - * PRESENT_READBACK command should not be necessary unless you - * actually want to read back the results of 3D rendering into - * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB - * command provides a strict superset of functionality.) - * - * - When a screen is resized, either using Screen Object commands or - * legacy multimon registers, its contents are preserved. - * - * SVGA_FIFO_CAP_GMR2 -- - * - * Provides new commands to define and remap guest memory regions (GMR). - * - * New 2D commands: - * DEFINE_GMR2, REMAP_GMR2. - * - * SVGA_FIFO_CAP_3D_HWVERSION_REVISED -- - * - * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists. - * This register may replace SVGA_FIFO_3D_HWVERSION on platforms - * that enforce graphics resource limits. This allows the platform - * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest - * drivers that do not limit their resources. - * - * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators - * are codependent (and thus we use a single capability bit). - * - * SVGA_FIFO_CAP_SCREEN_OBJECT_2 -- - * - * Modifies the DEFINE_SCREEN command to include a guest provided - * backing store in GMR memory and the bytesPerLine for the backing - * store. This capability requires the use of a backing store when - * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT - * is present then backing stores are optional. - * - * SVGA_FIFO_CAP_DEAD -- - * - * Drivers should not use this cap bit. This cap bit can not be - * reused since some hosts already expose it. - */ +#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1) -#define SVGA_FIFO_CAP_NONE 0 -#define SVGA_FIFO_CAP_FENCE (1<<0) -#define SVGA_FIFO_CAP_ACCELFRONT (1<<1) -#define SVGA_FIFO_CAP_PITCHLOCK (1<<2) -#define SVGA_FIFO_CAP_VIDEO (1<<3) -#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4) -#define SVGA_FIFO_CAP_ESCAPE (1<<5) -#define SVGA_FIFO_CAP_RESERVE (1<<6) -#define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7) -#define SVGA_FIFO_CAP_GMR2 (1<<8) -#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2 -#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9) -#define SVGA_FIFO_CAP_DEAD (1<<10) +#define SVGA_FIFO_CAP_NONE 0 +#define SVGA_FIFO_CAP_FENCE (1 << 0) +#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) +#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) +#define SVGA_FIFO_CAP_VIDEO (1 << 3) +#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1 << 4) +#define SVGA_FIFO_CAP_ESCAPE (1 << 5) +#define SVGA_FIFO_CAP_RESERVE (1 << 6) +#define SVGA_FIFO_CAP_SCREEN_OBJECT (1 << 7) +#define SVGA_FIFO_CAP_GMR2 (1 << 8) +#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2 +#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1 << 9) +#define SVGA_FIFO_CAP_DEAD (1 << 10) +#define SVGA_FIFO_FLAG_NONE 0 +#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) +#define SVGA_FIFO_FLAG_RESERVED (1 << 31) -/* - * FIFO Flags - * - * Accel Front -- Driver should use front buffer only commands - */ +#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff -#define SVGA_FIFO_FLAG_NONE 0 -#define SVGA_FIFO_FLAG_ACCELFRONT (1<<0) -#define SVGA_FIFO_FLAG_RESERVED (1<<31) /* Internal use only */ - -/* - * FIFO reservation sentinel value - */ - -#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff - - -/* - * Video overlay support - */ +#define SVGA_SCREENDMA_REG_UNDEFINED 0 +#define SVGA_SCREENDMA_REG_NOT_PRESENT 1 +#define SVGA_SCREENDMA_REG_PRESENT 2 +#define SVGA_SCREENDMA_REG_MAX 3 #define SVGA_NUM_OVERLAY_UNITS 32 - -/* - * Video capabilities that the guest is currently using - */ - -#define SVGA_VIDEO_FLAG_COLORKEY 0x0001 - - -/* - * Offsets for the video overlay registers - */ +#define SVGA_VIDEO_FLAG_COLORKEY 0x0001 enum { SVGA_VIDEO_ENABLED = 0, @@ -1102,35 +553,26 @@ enum { SVGA_VIDEO_DATA_OFFSET, SVGA_VIDEO_FORMAT, SVGA_VIDEO_COLORKEY, - SVGA_VIDEO_SIZE, /* Deprecated */ + SVGA_VIDEO_SIZE, SVGA_VIDEO_WIDTH, SVGA_VIDEO_HEIGHT, SVGA_VIDEO_SRC_X, SVGA_VIDEO_SRC_Y, SVGA_VIDEO_SRC_WIDTH, SVGA_VIDEO_SRC_HEIGHT, - SVGA_VIDEO_DST_X, /* Signed int32 */ - SVGA_VIDEO_DST_Y, /* Signed int32 */ + SVGA_VIDEO_DST_X, + SVGA_VIDEO_DST_Y, SVGA_VIDEO_DST_WIDTH, SVGA_VIDEO_DST_HEIGHT, SVGA_VIDEO_PITCH_1, SVGA_VIDEO_PITCH_2, SVGA_VIDEO_PITCH_3, - SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */ - SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */ - /* (SVGA_ID_INVALID) */ + SVGA_VIDEO_DATA_GMRID, + SVGA_VIDEO_DST_SCREEN_ID, SVGA_VIDEO_NUM_REGS }; - -/* - * SVGA Overlay Units - * - * width and height relate to the entire source video frame. - * srcX, srcY, srcWidth and srcHeight represent subset of the source - * video frame to be displayed. - */ - +#pragma pack(push, 1) typedef struct SVGAOverlayUnit { uint32 enabled; uint32 flags; @@ -1144,23 +586,17 @@ typedef struct SVGAOverlayUnit { uint32 srcY; uint32 srcWidth; uint32 srcHeight; - int32 dstX; - int32 dstY; + int32 dstX; + int32 dstY; uint32 dstWidth; uint32 dstHeight; uint32 pitches[3]; uint32 dataGMRId; uint32 dstScreenId; } SVGAOverlayUnit; +#pragma pack(pop) - -/* - * Guest display topology - * - * XXX: This structure is not part of the SVGA device's interface, and - * doesn't really belong here. - */ -#define SVGA_INVALID_DISPLAY_ID ((uint32)-1) +#define SVGA_INVALID_DISPLAY_ID ((uint32) - 1) typedef struct SVGADisplayTopology { uint16 displayId; @@ -1171,67 +607,18 @@ typedef struct SVGADisplayTopology { uint32 positionY; } SVGADisplayTopology; - -/* - * SVGAScreenObject -- - * - * This is a new way to represent a guest's multi-monitor screen or - * Unity window. Screen objects are only supported if the - * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set. - * - * If Screen Objects are supported, they can be used to fully - * replace the functionality provided by the framebuffer registers - * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY. - * - * The screen object is a struct with guaranteed binary - * compatibility. New flags can be added, and the struct may grow, - * but existing fields must retain their meaning. - * - * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of - * a SVGAGuestPtr that is used to back the screen contents. This - * memory must come from the GFB. The guest is not allowed to - * access the memory and doing so will have undefined results. The - * backing store is required to be page aligned and the size is - * padded to the next page boundary. The number of pages is: - * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE - * - * The pitch in the backingStore is required to be at least large - * enough to hold a 32bbp scanline. It is recommended that the - * driver pad bytesPerLine for a potential performance win. - * - * The cloneCount field is treated as a hint from the guest that - * the user wants this display to be cloned, countCount times. A - * value of zero means no cloning should happen. - */ - #define SVGA_SCREEN_MUST_BE_SET (1 << 0) -#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */ +#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET #define SVGA_SCREEN_IS_PRIMARY (1 << 1) #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) -/* - * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is - * deactivated the base layer is defined to lose all contents and - * become black. When a screen is deactivated the backing store is - * optional. When set backingPtr and bytesPerLine will be ignored. - */ -#define SVGA_SCREEN_DEACTIVATE (1 << 3) +#define SVGA_SCREEN_DEACTIVATE (1 << 3) -/* - * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set - * the screen contents will be outputted as all black to the user - * though the base layer contents is preserved. The screen base layer - * can still be read and written to like normal though the no visible - * effect will be seen by the user. When the flag is changed the - * screen will be blanked or redrawn to the current contents as needed - * without any extra commands from the driver. This flag only has an - * effect when the screen is not deactivated. - */ #define SVGA_SCREEN_BLANKING (1 << 4) -typedef -struct { - uint32 structSize; /* sizeof(SVGAScreenObject) */ +#pragma pack(push, 1) +typedef struct { + uint32 structSize; uint32 id; uint32 flags; struct { @@ -1243,120 +630,53 @@ struct { int32 y; } root; - /* - * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional - * with SVGA_FIFO_CAP_SCREEN_OBJECT. - */ SVGAGuestImage backingStore; - /* - * The cloneCount field is treated as a hint from the guest that - * the user wants this display to be cloned, cloneCount times. - * - * A value of zero means no cloning should happen. - */ uint32 cloneCount; } SVGAScreenObject; - - -/* - * Commands in the command FIFO: - * - * Command IDs defined below are used for the traditional 2D FIFO - * communication (not all commands are available for all versions of the - * SVGA FIFO protocol). - * - * Note the holes in the command ID numbers: These commands have been - * deprecated, and the old IDs must not be reused. - * - * Command IDs from 1000 to 2999 are reserved for use by the SVGA3D - * protocol. - * - * Each command's parameters are described by the comments and - * structs below. - */ +#pragma pack(pop) typedef enum { - SVGA_CMD_INVALID_CMD = 0, - SVGA_CMD_UPDATE = 1, - SVGA_CMD_RECT_COPY = 3, - SVGA_CMD_RECT_ROP_COPY = 14, - SVGA_CMD_DEFINE_CURSOR = 19, - SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, - SVGA_CMD_UPDATE_VERBOSE = 25, - SVGA_CMD_FRONT_ROP_FILL = 29, - SVGA_CMD_FENCE = 30, - SVGA_CMD_ESCAPE = 33, - SVGA_CMD_DEFINE_SCREEN = 34, - SVGA_CMD_DESTROY_SCREEN = 35, - SVGA_CMD_DEFINE_GMRFB = 36, - SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, - SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, - SVGA_CMD_ANNOTATION_FILL = 39, - SVGA_CMD_ANNOTATION_COPY = 40, - SVGA_CMD_DEFINE_GMR2 = 41, - SVGA_CMD_REMAP_GMR2 = 42, - SVGA_CMD_DEAD = 43, - SVGA_CMD_DEAD_2 = 44, - SVGA_CMD_NOP = 45, - SVGA_CMD_NOP_ERROR = 46, + SVGA_CMD_INVALID_CMD = 0, + SVGA_CMD_UPDATE = 1, + SVGA_CMD_RECT_COPY = 3, + SVGA_CMD_RECT_ROP_COPY = 14, + SVGA_CMD_DEFINE_CURSOR = 19, + SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, + SVGA_CMD_UPDATE_VERBOSE = 25, + SVGA_CMD_FRONT_ROP_FILL = 29, + SVGA_CMD_FENCE = 30, + SVGA_CMD_ESCAPE = 33, + SVGA_CMD_DEFINE_SCREEN = 34, + SVGA_CMD_DESTROY_SCREEN = 35, + SVGA_CMD_DEFINE_GMRFB = 36, + SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, + SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, + SVGA_CMD_ANNOTATION_FILL = 39, + SVGA_CMD_ANNOTATION_COPY = 40, + SVGA_CMD_DEFINE_GMR2 = 41, + SVGA_CMD_REMAP_GMR2 = 42, + SVGA_CMD_DEAD = 43, + SVGA_CMD_DEAD_2 = 44, + SVGA_CMD_NOP = 45, + SVGA_CMD_NOP_ERROR = 46, SVGA_CMD_MAX } SVGAFifoCmdId; -#define SVGA_CMD_MAX_DATASIZE (256 * 1024) -#define SVGA_CMD_MAX_ARGS 64 -#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB +#define SVGA_CMD_MAX_DATASIZE (256 * 1024) +#define SVGA_CMD_MAX_ARGS 64 - -/* - * SVGA_CMD_UPDATE -- - * - * This is a DMA transfer which copies from the Guest Framebuffer - * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which - * intersect with the provided virtual rectangle. - * - * This command does not support using arbitrary guest memory as a - * data source- it only works with the pre-defined GFB memory. - * This command also does not support signed virtual coordinates. - * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with - * negative root x/y coordinates, the negative portion of those - * screens will not be reachable by this command. - * - * This command is not necessary when using framebuffer - * traces. Traces are automatically enabled if the SVGA FIFO is - * disabled, and you may explicitly enable/disable traces using - * SVGA_REG_TRACES. With traces enabled, any write to the GFB will - * automatically act as if a subsequent SVGA_CMD_UPDATE was issued. - * - * Traces and SVGA_CMD_UPDATE are the only supported ways to render - * pseudocolor screen updates. The newer Screen Object commands - * only support true color formats. - * - * Availability: - * Always available. - */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 x; uint32 y; uint32 width; uint32 height; } SVGAFifoCmdUpdate; +#pragma pack(pop) - -/* - * SVGA_CMD_RECT_COPY -- - * - * Perform a rectangular DMA transfer from one area of the GFB to - * another, and copy the result to any screens which intersect it. - * - * Availability: - * SVGA_CAP_RECT_COPY - */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 srcX; uint32 srcY; uint32 destX; @@ -1364,22 +684,10 @@ struct { uint32 width; uint32 height; } SVGAFifoCmdRectCopy; +#pragma pack(pop) - -/* - * SVGA_CMD_RECT_ROP_COPY -- - * - * Perform a rectangular DMA transfer from one area of the GFB to - * another, and copy the result to any screens which intersect it. - * The value of ROP may only be SVGA_ROP_COPY, and this command is - * only supported for backwards compatibility reasons. - * - * Availability: - * SVGA_CAP_RECT_COPY - */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 srcX; uint32 srcY; uint32 destX; @@ -1388,509 +696,231 @@ struct { uint32 height; uint32 rop; } SVGAFifoCmdRectRopCopy; +#pragma pack(pop) - -/* - * SVGA_CMD_DEFINE_CURSOR -- - * - * Provide a new cursor image, as an AND/XOR mask. - * - * The recommended way to position the cursor overlay is by using - * the SVGA_FIFO_CURSOR_* registers, supported by the - * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. - * - * Availability: - * SVGA_CAP_CURSOR - */ - -typedef -struct { - uint32 id; /* Reserved, must be zero. */ +#pragma pack(push, 1) +typedef struct { + uint32 id; uint32 hotspotX; uint32 hotspotY; uint32 width; uint32 height; - uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ - uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ - /* - * Followed by scanline data for AND mask, then XOR mask. - * Each scanline is padded to a 32-bit boundary. - */ + uint32 andMaskDepth; + uint32 xorMaskDepth; + } SVGAFifoCmdDefineCursor; +#pragma pack(pop) - -/* - * SVGA_CMD_DEFINE_ALPHA_CURSOR -- - * - * Provide a new cursor image, in 32-bit BGRA format. - * - * The recommended way to position the cursor overlay is by using - * the SVGA_FIFO_CURSOR_* registers, supported by the - * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. - * - * Availability: - * SVGA_CAP_ALPHA_CURSOR - */ - -typedef -struct { - uint32 id; /* Reserved, must be zero. */ +#pragma pack(push, 1) +typedef struct { + uint32 id; uint32 hotspotX; uint32 hotspotY; uint32 width; uint32 height; - /* Followed by scanline data */ + } SVGAFifoCmdDefineAlphaCursor; +#pragma pack(pop) +#pragma pack(push, 1) +typedef struct { + uint32 hotspotX; + uint32 hotspotY; + uint32 width; + uint32 height; + uint32 andMaskDepth; + uint32 xorMaskDepth; -/* - * SVGA_CMD_UPDATE_VERBOSE -- - * - * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle - * 'reason' value, an opaque cookie which is used by internal - * debugging tools. Third party drivers should not use this - * command. - * - * Availability: - * SVGA_CAP_EXTENDED_FIFO - */ +} SVGAGBColorCursorHeader; +#pragma pack(pop) -typedef -struct { +#pragma pack(push, 1) +typedef struct { + uint32 hotspotX; + uint32 hotspotY; + uint32 width; + uint32 height; + +} SVGAGBAlphaCursorHeader; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { + uint32 hotspotX; + uint32 hotspotY; + uint32 width; + uint32 height; +} SVGAGBAlpha3dCursorHeader; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { + uint32 srcx; + uint32 srcy; + uint32 sid; + uint32 face; + uint32 mipmap; +} SVGAGBAlpha3dCursorData; +#pragma pack(pop) + +typedef enum { + SVGA_COLOR_CURSOR = 0, + SVGA_ALPHA_CURSOR = 1, + SVGA_ALPHA3D_CURSOR = 2, +} SVGAGBCursorType; + +#pragma pack(push, 1) +typedef struct { + SVGAGBCursorType type; + union { + SVGAGBColorCursorHeader colorHeader; + SVGAGBAlphaCursorHeader alphaHeader; + SVGAGBAlpha3dCursorHeader alpha3dHeader; + } header; + uint32 sizeInBytes; + +} SVGAGBCursorHeader; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct { uint32 x; uint32 y; uint32 width; uint32 height; uint32 reason; } SVGAFifoCmdUpdateVerbose; +#pragma pack(pop) - -/* - * SVGA_CMD_FRONT_ROP_FILL -- - * - * This is a hint which tells the SVGA device that the driver has - * just filled a rectangular region of the GFB with a solid - * color. Instead of reading these pixels from the GFB, the device - * can assume that they all equal 'color'. This is primarily used - * for remote desktop protocols. - * - * Availability: - * SVGA_FIFO_CAP_ACCELFRONT - */ - -#define SVGA_ROP_COPY 0x03 - -typedef -struct { - uint32 color; /* In the same format as the GFB */ +#pragma pack(push, 1) +typedef struct { + uint32 color; uint32 x; uint32 y; uint32 width; uint32 height; - uint32 rop; /* Must be SVGA_ROP_COPY */ + uint32 rop; } SVGAFifoCmdFrontRopFill; +#pragma pack(pop) - -/* - * SVGA_CMD_FENCE -- - * - * Insert a synchronization fence. When the SVGA device reaches - * this command, it will copy the 'fence' value into the - * SVGA_FIFO_FENCE register. It will also compare the fence against - * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the - * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will - * raise this interrupt. - * - * Availability: - * SVGA_FIFO_FENCE for this command, - * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL. - */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 fence; } SVGAFifoCmdFence; +#pragma pack(pop) - -/* - * SVGA_CMD_ESCAPE -- - * - * Send an extended or vendor-specific variable length command. - * This is used for video overlay, third party plugins, and - * internal debugging tools. See svga_escape.h - * - * Availability: - * SVGA_FIFO_CAP_ESCAPE - */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 nsid; uint32 size; - /* followed by 'size' bytes of data */ + } SVGAFifoCmdEscape; +#pragma pack(pop) - -/* - * SVGA_CMD_DEFINE_SCREEN -- - * - * Define or redefine an SVGAScreenObject. See the description of - * SVGAScreenObject above. The video driver is responsible for - * generating new screen IDs. They should be small positive - * integers. The virtual device will have an implementation - * specific upper limit on the number of screen IDs - * supported. Drivers are responsible for recycling IDs. The first - * valid ID is zero. - * - * - Interaction with other registers: - * - * For backwards compatibility, when the GFB mode registers (WIDTH, - * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device - * deletes all screens other than screen #0, and redefines screen - * #0 according to the specified mode. Drivers that use - * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0. - * - * If you use screen objects, do not use the legacy multi-mon - * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*). - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 - */ - -typedef -struct { - SVGAScreenObject screen; /* Variable-length according to version */ +#pragma pack(push, 1) +typedef struct { + SVGAScreenObject screen; } SVGAFifoCmdDefineScreen; +#pragma pack(pop) - -/* - * SVGA_CMD_DESTROY_SCREEN -- - * - * Destroy an SVGAScreenObject. Its ID is immediately available for - * re-use. - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 - */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 screenId; } SVGAFifoCmdDestroyScreen; +#pragma pack(pop) - -/* - * SVGA_CMD_DEFINE_GMRFB -- - * - * This command sets a piece of SVGA device state called the - * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a - * piece of light-weight state which identifies the location and - * format of an image in guest memory or in BAR1. The GMRFB has - * an arbitrary size, and it doesn't need to match the geometry - * of the GFB or any screen object. - * - * The GMRFB can be redefined as often as you like. You could - * always use the same GMRFB, you could redefine it before - * rendering from a different guest screen, or you could even - * redefine it before every blit. - * - * There are multiple ways to use this command. The simplest way is - * to use it to move the framebuffer either to elsewhere in the GFB - * (BAR1) memory region, or to a user-defined GMR. This lets a - * driver use a framebuffer allocated entirely out of normal system - * memory, which we encourage. - * - * Another way to use this command is to set up a ring buffer of - * updates in GFB memory. If a driver wants to ensure that no - * frames are skipped by the SVGA device, it is important that the - * driver not modify the source data for a blit until the device is - * done processing the command. One efficient way to accomplish - * this is to use a ring of small DMA buffers. Each buffer is used - * for one blit, then we move on to the next buffer in the - * ring. The FENCE mechanism is used to protect each buffer from - * re-use until the device is finished with that buffer's - * corresponding blit. - * - * This command does not affect the meaning of SVGA_CMD_UPDATE. - * UPDATEs always occur from the legacy GFB memory area. This - * command has no support for pseudocolor GMRFBs. Currently only - * true-color 15, 16, and 24-bit depths are supported. Future - * devices may expose capabilities for additional framebuffer - * formats. - * - * The default GMRFB value is undefined. Drivers must always send - * this command at least once before performing any blit from the - * GMRFB. - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 - */ - -typedef -struct { - SVGAGuestPtr ptr; - uint32 bytesPerLine; - SVGAGMRImageFormat format; +#pragma pack(push, 1) +typedef struct { + SVGAGuestPtr ptr; + uint32 bytesPerLine; + SVGAGMRImageFormat format; } SVGAFifoCmdDefineGMRFB; +#pragma pack(pop) - -/* - * SVGA_CMD_BLIT_GMRFB_TO_SCREEN -- - * - * This is a guest-to-host blit. It performs a DMA operation to - * copy a rectangular region of pixels from the current GMRFB to - * one or more Screen Objects. - * - * The destination coordinate may be specified relative to a - * screen's origin (if a screen ID is specified) or relative to the - * virtual coordinate system's origin (if the screen ID is - * SVGA_ID_INVALID). The actual destination may span zero or more - * screens, in the case of a virtual destination rect or a rect - * which extends off the edge of the specified screen. - * - * This command writes to the screen's "base layer": the underlying - * framebuffer which exists below any cursor or video overlays. No - * action is necessary to explicitly hide or update any overlays - * which exist on top of the updated region. - * - * The SVGA device is guaranteed to finish reading from the GMRFB - * by the time any subsequent FENCE commands are reached. - * - * This command consumes an annotation. See the - * SVGA_CMD_ANNOTATION_* commands for details. - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 - */ - -typedef -struct { - SVGASignedPoint srcOrigin; - SVGASignedRect destRect; - uint32 destScreenId; +#pragma pack(push, 1) +typedef struct { + SVGASignedPoint srcOrigin; + SVGASignedRect destRect; + uint32 destScreenId; } SVGAFifoCmdBlitGMRFBToScreen; +#pragma pack(pop) - -/* - * SVGA_CMD_BLIT_SCREEN_TO_GMRFB -- - * - * This is a host-to-guest blit. It performs a DMA operation to - * copy a rectangular region of pixels from a single Screen Object - * back to the current GMRFB. - * - * Usage note: This command should be used rarely. It will - * typically be inefficient, but it is necessary for some types of - * synchronization between 3D (GPU) and 2D (CPU) rendering into - * overlapping areas of a screen. - * - * The source coordinate is specified relative to a screen's - * origin. The provided screen ID must be valid. If any parameters - * are invalid, the resulting pixel values are undefined. - * - * This command reads the screen's "base layer". Overlays like - * video and cursor are not included, but any data which was sent - * using a blit-to-screen primitive will be available, no matter - * whether the data's original source was the GMRFB or the 3D - * acceleration hardware. - * - * Note that our guest-to-host blits and host-to-guest blits aren't - * symmetric in their current implementation. While the parameters - * are identical, host-to-guest blits are a lot less featureful. - * They do not support clipping: If the source parameters don't - * fully fit within a screen, the blit fails. They must originate - * from exactly one screen. Virtual coordinates are not directly - * supported. - * - * Host-to-guest blits do support the same set of GMRFB formats - * offered by guest-to-host blits. - * - * The SVGA device is guaranteed to finish writing to the GMRFB by - * the time any subsequent FENCE commands are reached. - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 - */ - -typedef -struct { - SVGASignedPoint destOrigin; - SVGASignedRect srcRect; - uint32 srcScreenId; +#pragma pack(push, 1) +typedef struct { + SVGASignedPoint destOrigin; + SVGASignedRect srcRect; + uint32 srcScreenId; } SVGAFifoCmdBlitScreenToGMRFB; +#pragma pack(pop) - -/* - * SVGA_CMD_ANNOTATION_FILL -- - * - * This is a blit annotation. This command stores a small piece of - * device state which is consumed by the next blit-to-screen - * command. The state is only cleared by commands which are - * specifically documented as consuming an annotation. Other - * commands (such as ESCAPEs for debugging) may intervene between - * the annotation and its associated blit. - * - * This annotation is a promise about the contents of the next - * blit: The video driver is guaranteeing that all pixels in that - * blit will have the same value, specified here as a color in - * SVGAColorBGRX format. - * - * The SVGA device can still render the blit correctly even if it - * ignores this annotation, but the annotation may allow it to - * perform the blit more efficiently, for example by ignoring the - * source data and performing a fill in hardware. - * - * This annotation is most important for performance when the - * user's display is being remoted over a network connection. - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 - */ - -typedef -struct { - SVGAColorBGRX color; +#pragma pack(push, 1) +typedef struct { + SVGAColorBGRX color; } SVGAFifoCmdAnnotationFill; +#pragma pack(pop) - -/* - * SVGA_CMD_ANNOTATION_COPY -- - * - * This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more - * information about annotations. - * - * This annotation is a promise about the contents of the next - * blit: The video driver is guaranteeing that all pixels in that - * blit will have the same value as those which already exist at an - * identically-sized region on the same or a different screen. - * - * Note that the source pixels for the COPY in this annotation are - * sampled before applying the annotation's associated blit. They - * are allowed to overlap with the blit's destination pixels. - * - * The copy source rectangle is specified the same way as the blit - * destination: it can be a rectangle which spans zero or more - * screens, specified relative to either a screen or to the virtual - * coordinate system's origin. If the source rectangle includes - * pixels which are not from exactly one screen, the results are - * undefined. - * - * Availability: - * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 - */ - -typedef -struct { - SVGASignedPoint srcOrigin; - uint32 srcScreenId; +#pragma pack(push, 1) +typedef struct { + SVGASignedPoint srcOrigin; + uint32 srcScreenId; } SVGAFifoCmdAnnotationCopy; +#pragma pack(pop) - -/* - * SVGA_CMD_DEFINE_GMR2 -- - * - * Define guest memory region v2. See the description of GMRs above. - * - * Availability: - * SVGA_CAP_GMR2 - */ - -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 gmrId; uint32 numPages; } SVGAFifoCmdDefineGMR2; - - -/* - * SVGA_CMD_REMAP_GMR2 -- - * - * Remap guest memory region v2. See the description of GMRs above. - * - * This command allows guest to modify a portion of an existing GMR by - * invalidating it or reassigning it to different guest physical pages. - * The pages are identified by physical page number (PPN). The pages - * are assumed to be pinned and valid for DMA operations. - * - * Description of command flags: - * - * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR. - * The PPN list must not overlap with the remap region (this can be - * handled trivially by referencing a separate GMR). If flag is - * disabled, PPN list is appended to SVGARemapGMR command. - * - * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise - * it is in PPN32 format. - * - * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry. - * A single PPN can be used to invalidate a portion of a GMR or - * map it to to a single guest scratch page. - * - * Availability: - * SVGA_CAP_GMR2 - */ +#pragma pack(pop) typedef enum { - SVGA_REMAP_GMR2_PPN32 = 0, - SVGA_REMAP_GMR2_VIA_GMR = (1 << 0), - SVGA_REMAP_GMR2_PPN64 = (1 << 1), - SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2), + SVGA_REMAP_GMR2_PPN32 = 0, + SVGA_REMAP_GMR2_VIA_GMR = (1 << 0), + SVGA_REMAP_GMR2_PPN64 = (1 << 1), + SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2), } SVGARemapGMR2Flags; -typedef -struct { +#pragma pack(push, 1) +typedef struct { uint32 gmrId; SVGARemapGMR2Flags flags; - uint32 offsetPages; /* offset in pages to begin remap */ - uint32 numPages; /* number of pages to remap */ - /* - * Followed by additional data depending on SVGARemapGMR2Flags. - * - * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows. - * Otherwise an array of page descriptors in PPN32 or PPN64 format - * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag - * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry. - */ + uint32 offsetPages; + uint32 numPages; + } SVGAFifoCmdRemapGMR2; +#pragma pack(pop) +#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) +#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024) +#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024) +#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024) +#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024) +#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024) +#define SVGA_GRAPHICS_MEMORY_KB_MAX_2GB (2 * 1024 * 1024) +#define SVGA_GRAPHICS_MEMORY_KB_MAX_3GB (3 * 1024 * 1024) +#define SVGA_GRAPHICS_MEMORY_KB_MAX_4GB (4 * 1024 * 1024) +#define SVGA_GRAPHICS_MEMORY_KB_MAX_8GB (8 * 1024 * 1024) +#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024) -/* - * Size of SVGA device memory such as frame buffer and FIFO. - */ -#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */ -#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024) -#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024) -#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024) -#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024) -#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024) -#define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024) -#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024) - -#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */ - -/* - * To simplify autoDetect display configuration, support a minimum of - * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated: - * numDisplays = 2 - * maxWidth = numDisplay * 1920 = 3840 - * maxHeight = rotated width of single monitor = 1920 - * vramSize = maxWidth * maxHeight * 4 = 29491200 - */ -#define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024) +#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) #if defined(VMX86_SERVER) -#define SVGA_VRAM_SIZE (4 * 1024 * 1024) -#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024) -#define SVGA_FIFO_SIZE (256 * 1024) -#define SVGA_FIFO_SIZE_3D (516 * 1024) -#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024) -#define SVGA_AUTODETECT_DEFAULT FALSE +#define SVGA_VRAM_SIZE (4 * 1024 * 1024) +#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024) +#define SVGA_FIFO_SIZE (256 * 1024) +#define SVGA_FIFO_SIZE_3D (516 * 1024) +#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024) +#define SVGA_AUTODETECT_DEFAULT FALSE #else -#define SVGA_VRAM_SIZE (16 * 1024 * 1024) -#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE -#define SVGA_FIFO_SIZE (2 * 1024 * 1024) -#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE -#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024) -#define SVGA_AUTODETECT_DEFAULT TRUE +#define SVGA_VRAM_SIZE (16 * 1024 * 1024) +#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE +#define SVGA_FIFO_SIZE (2 * 1024 * 1024) +#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE +#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024) +#define SVGA_AUTODETECT_DEFAULT TRUE #endif +#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024) +#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024) + #endif diff --git a/src/gallium/drivers/svga/include/svga_types.h b/src/gallium/drivers/svga/include/svga_types.h deleted file mode 100644 index bc22dff27b7..00000000000 --- a/src/gallium/drivers/svga/include/svga_types.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 1998-2024 Broadcom. All Rights Reserved. - * The term “Broadcom” refers to Broadcom Inc. - * and/or its subsidiaries. - * SPDX-License-Identifier: GPL-2.0 OR MIT - */ - -#ifndef _SVGA_TYPES_H_ -#define _SVGA_TYPES_H_ - -#include "util/compiler.h" - -#ifndef __HAIKU__ -typedef int64_t int64; -typedef uint64_t uint64; - -typedef int32_t int32; -typedef uint32_t uint32; - -typedef int16_t int16; -typedef uint16_t uint16; - -typedef int8_t int8; -typedef uint8_t uint8; -#else -#include -#endif /* HAIKU */ - -typedef uint8_t Bool; - -typedef uint64 PA; -typedef uint32 PPN; -typedef uint64 PPN64; - -#undef MAX_UINT32 -#define MAX_UINT32 0xffffffffU - -#endif /* _SVGA_TYPES_H_ */ - diff --git a/src/gallium/drivers/svga/include/vm_basic_types.h b/src/gallium/drivers/svga/include/vm_basic_types.h new file mode 100644 index 00000000000..e1f77b08dc6 --- /dev/null +++ b/src/gallium/drivers/svga/include/vm_basic_types.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/********************************************************** + * + * Copyright (c) 2024 Broadcom. + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + **********************************************************/ +#ifndef VM_BASIC_TYPES_H +#define VM_BASIC_TYPES_H + +#include +#include + +typedef uint32_t uint32; +typedef int32_t int32; +typedef uint64_t uint64; +typedef uint16_t uint16; +typedef int16_t int16; +typedef uint8_t uint8; +typedef int8_t int8; + +typedef uint64 PA; +typedef uint32 PPN; +typedef uint32 PPN32; +typedef uint64 PPN64; + +typedef bool Bool; + +#define MAX_UINT64 UINT64_MAX +#define MAX_UINT32 UINT32_MAX +#define MAX_UINT16 UINT16_MAX + +#define CONST64U(x) x##ULL + +#ifndef MBYTES_SHIFT +#define MBYTES_SHIFT 20 +#endif +#ifndef MBYTES_2_BYTES +#define MBYTES_2_BYTES(_nbytes) ((uint64)(_nbytes) << MBYTES_SHIFT) +#endif + +#define INLINE inline + +#endif diff --git a/src/gallium/drivers/svga/include/vmw_surf_defs.h b/src/gallium/drivers/svga/include/vmw_surf_defs.h new file mode 100644 index 00000000000..d1065b0a0a0 --- /dev/null +++ b/src/gallium/drivers/svga/include/vmw_surf_defs.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/********************************************************** + * + * Copyright (c) 2024 Broadcom. + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + **********************************************************/ +#ifndef VMW_SURF_DEFS_H +#define VMW_SURF_DEFS_H + +#include "util/macros.h" +#include "svga3d_surfacedefs.h" +#include "svga3d_types.h" + +static inline uint32 +clamped_umul32(uint32 a, uint32 b) +{ + uint64_t tmp = (uint64_t)a * b; + return (tmp > (uint64_t)((uint32)-1)) ? (uint32)-1 : tmp; +} + +static inline uint32 +clamped_uadd32(uint32 a, uint32 b) +{ + uint32 c = a + b; + if (c < a || c < b) { + return MAX_UINT32; + } + return c; +} + +static inline const struct SVGA3dSurfaceDesc * +vmw_surf_get_desc(SVGA3dSurfaceFormat format) +{ + if (format < ARRAY_SIZE(g_SVGA3dSurfaceDescs)) + return &g_SVGA3dSurfaceDescs[format]; + + return &g_SVGA3dSurfaceDescs[SVGA3D_FORMAT_INVALID]; +} + +static inline SVGA3dSize +vmw_surf_get_mip_size(SVGA3dSize base_level, uint32 mip_level) +{ + SVGA3dSize size; + + size.width = MAX2(base_level.width >> mip_level, 1); + size.height = MAX2(base_level.height >> mip_level, 1); + size.depth = MAX2(base_level.depth >> mip_level, 1); + return size; +} + +static inline void +vmw_surf_get_size_in_blocks(const struct SVGA3dSurfaceDesc *desc, + const SVGA3dSize *pixel_size, + SVGA3dSize *block_size) +{ + block_size->width = DIV_ROUND_UP(pixel_size->width, desc->blockSize.width); + block_size->height = + DIV_ROUND_UP(pixel_size->height, desc->blockSize.height); + block_size->depth = DIV_ROUND_UP(pixel_size->depth, desc->blockSize.depth); +} + +static inline bool +vmw_surf_is_planar_surface(const struct SVGA3dSurfaceDesc *desc) +{ + return (desc->blockDesc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0; +} + +static inline uint32 +vmw_surf_calculate_pitch(const struct SVGA3dSurfaceDesc *desc, + const SVGA3dSize *size) +{ + uint32 pitch; + SVGA3dSize blocks; + + vmw_surf_get_size_in_blocks(desc, size, &blocks); + + pitch = blocks.width * desc->pitchBytesPerBlock; + + return pitch; +} + +static inline uint32 +vmw_surf_get_image_buffer_size(const struct SVGA3dSurfaceDesc *desc, + const SVGA3dSize *size, uint32 pitch) +{ + SVGA3dSize image_blocks; + uint32 slice_size, total_size; + + vmw_surf_get_size_in_blocks(desc, size, &image_blocks); + + if (vmw_surf_is_planar_surface(desc)) { + total_size = clamped_umul32(image_blocks.width, image_blocks.height); + total_size = clamped_umul32(total_size, image_blocks.depth); + total_size = clamped_umul32(total_size, desc->bytesPerBlock); + return total_size; + } + + if (pitch == 0) + pitch = vmw_surf_calculate_pitch(desc, size); + + slice_size = clamped_umul32(image_blocks.height, pitch); + total_size = clamped_umul32(slice_size, image_blocks.depth); + + return total_size; +} + +static inline uint32 +vmw_surf_get_serialized_size(SVGA3dSurfaceFormat format, + SVGA3dSize base_level_size, uint32 num_mip_levels, + uint32 num_layers) +{ + const struct SVGA3dSurfaceDesc *desc = vmw_surf_get_desc(format); + uint64_t total_size = 0; + uint32 mip; + + for (mip = 0; mip < num_mip_levels; mip++) { + SVGA3dSize size = vmw_surf_get_mip_size(base_level_size, mip); + total_size += vmw_surf_get_image_buffer_size(desc, &size, 0); + } + + total_size *= num_layers; + + return (total_size > (uint64_t)MAX_UINT32) ? MAX_UINT32 : (uint32)total_size; +} + +/** + * vmw_surf_get_serialized_size_extended - Returns the number of bytes + * required for a surface with given parameters. Support for sample count. + * + */ +static inline uint32 +vmw_surf_get_serialized_size_extended(SVGA3dSurfaceFormat format, + SVGA3dSize base_level_size, + uint32 num_mip_levels, uint32 num_layers, + uint32 num_samples) +{ + uint64_t total_size = vmw_surf_get_serialized_size( + format, base_level_size, num_mip_levels, num_layers); + + total_size *= (num_samples > 1 ? num_samples : 1); + + return (total_size > (uint64_t)MAX_UINT32) ? MAX_UINT32 : (uint32)total_size; +} + +static inline uint32 +vmw_surf_get_image_offset(SVGA3dSurfaceFormat format, SVGA3dSize baseLevelSize, + uint32 numMipLevels, uint32 layer, uint32 mip) + +{ + uint32 offset; + uint32 mipChainBytes; + uint32 mipChainBytesToLevel; + uint32 i; + const struct SVGA3dSurfaceDesc *desc; + SVGA3dSize mipSize; + uint32 bytes; + + desc = vmw_surf_get_desc(format); + + mipChainBytes = 0; + mipChainBytesToLevel = 0; + for (i = 0; i < numMipLevels; i++) { + mipSize = vmw_surf_get_mip_size(baseLevelSize, i); + bytes = vmw_surf_get_image_buffer_size(desc, &mipSize, 0); + mipChainBytes += bytes; + if (i < mip) { + mipChainBytesToLevel += bytes; + } + } + + offset = mipChainBytes * layer + mipChainBytesToLevel; + + return offset; +} + +/** + * Compute the offset (in bytes) to a pixel in an image (or volume). + * 'width' is the image width in pixels + * 'height' is the image height in pixels + */ +static inline uint32 +vmw_surf_get_pixel_offset(SVGA3dSurfaceFormat format, uint32 width, + uint32 height, uint32 x, uint32 y, uint32 z) +{ + const struct SVGA3dSurfaceDesc *desc = vmw_surf_get_desc(format); + const uint32 bw = desc->blockSize.width, bh = desc->blockSize.height; + const uint32 bd = desc->blockSize.depth; + const uint32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytesPerBlock; + const uint32 imgstride = DIV_ROUND_UP(height, bh) * rowstride; + const uint32 offset = + (z / bd * imgstride + y / bh * rowstride + x / bw * desc->bytesPerBlock); + return offset; +} + +#endif /* VMW_SURF_DEFS_H */ diff --git a/src/gallium/drivers/svga/include/vmware_pack_begin.h b/src/gallium/drivers/svga/include/vmware_pack_begin.h deleted file mode 100644 index f1839f03c8e..00000000000 --- a/src/gallium/drivers/svga/include/vmware_pack_begin.h +++ /dev/null @@ -1 +0,0 @@ -/* dummy file */ diff --git a/src/gallium/drivers/svga/include/vmware_pack_end.h b/src/gallium/drivers/svga/include/vmware_pack_end.h deleted file mode 100644 index f1839f03c8e..00000000000 --- a/src/gallium/drivers/svga/include/vmware_pack_end.h +++ /dev/null @@ -1 +0,0 @@ -/* dummy file */ diff --git a/src/gallium/drivers/svga/svga_cmd.h b/src/gallium/drivers/svga/svga_cmd.h index a9ad6a4d780..8ecf4ee5a36 100644 --- a/src/gallium/drivers/svga/svga_cmd.h +++ b/src/gallium/drivers/svga/svga_cmd.h @@ -16,7 +16,6 @@ #define __SVGA3D_H__ -#include "svga_types.h" #include "svga_winsys.h" #include "svga_reg.h" #include "svga3d_reg.h" diff --git a/src/gallium/drivers/svga/svga_cmd_vgpu10.c b/src/gallium/drivers/svga/svga_cmd_vgpu10.c index e561f356ca7..62f73b54759 100644 --- a/src/gallium/drivers/svga/svga_cmd_vgpu10.c +++ b/src/gallium/drivers/svga/svga_cmd_vgpu10.c @@ -872,7 +872,7 @@ SVGA3D_vgpu10_DefineBlendState(struct svga_winsys_context *swc, SVGA3D_CREATE_COMMAND(DefineBlendState, DEFINE_BLEND_STATE); - for (i = 0; i < SVGA3D_MAX_RENDER_TARGETS; i++) { + for (i = 0; i < SVGA3D_DX_MAX_RENDER_TARGETS; i++) { /* At most, one of blend or logicop can be enabled */ assert(perRT[i].blendEnable == 0 || perRT[i].logicOpEnable == 0); } diff --git a/src/gallium/drivers/svga/svga_context.h b/src/gallium/drivers/svga/svga_context.h index 38292693173..732b1f55c75 100644 --- a/src/gallium/drivers/svga/svga_context.h +++ b/src/gallium/drivers/svga/svga_context.h @@ -18,6 +18,7 @@ #include "util/u_blitter.h" #include "util/list.h" +#include "vm_basic_types.h" #include "svga_screen.h" #include "svga_state.h" #include "svga_winsys.h" @@ -82,9 +83,9 @@ enum svga_hud { #define CONST0_UPLOAD_ALIGNMENT 256 #define SVGA_MAX_UAVIEWS SVGA3D_DX11_1_MAX_UAVIEWS -#define SVGA_MAX_IMAGES SVGA3D_MAX_UAVIEWS -#define SVGA_MAX_SHADER_BUFFERS SVGA3D_MAX_UAVIEWS -#define SVGA_MAX_ATOMIC_BUFFERS SVGA3D_MAX_UAVIEWS +#define SVGA_MAX_IMAGES SVGA3D_DX11_MAX_UAVIEWS +#define SVGA_MAX_SHADER_BUFFERS SVGA3D_DX11_MAX_UAVIEWS +#define SVGA_MAX_ATOMIC_BUFFERS SVGA3D_DX11_MAX_UAVIEWS enum svga_surface_state { @@ -387,7 +388,7 @@ struct svga_hw_clear_state unsigned num_prescale; unsigned num_rendertargets; - struct pipe_surface *rtv[SVGA3D_MAX_RENDER_TARGETS]; + struct pipe_surface *rtv[SVGA3D_DX_MAX_RENDER_TARGETS]; struct pipe_surface *dsv; }; diff --git a/src/gallium/drivers/svga/svga_format.h b/src/gallium/drivers/svga/svga_format.h index 986c0f6103d..9006fc1e821 100644 --- a/src/gallium/drivers/svga/svga_format.h +++ b/src/gallium/drivers/svga/svga_format.h @@ -11,7 +11,6 @@ #include "util/format/u_formats.h" #include "svga_context.h" -#include "svga_types.h" #include "svga_reg.h" #include "svga3d_reg.h" diff --git a/src/gallium/drivers/svga/svga_hw_reg.h b/src/gallium/drivers/svga/svga_hw_reg.h index 5d670853a57..ee02fba96d2 100644 --- a/src/gallium/drivers/svga/svga_hw_reg.h +++ b/src/gallium/drivers/svga/svga_hw_reg.h @@ -10,8 +10,6 @@ #include "util/compiler.h" -#include "svga_types.h" - #include "svga3d_reg.h" diff --git a/src/gallium/drivers/svga/svga_pipe_blend.c b/src/gallium/drivers/svga/svga_pipe_blend.c index 2c249977be5..0414b39a6a9 100644 --- a/src/gallium/drivers/svga/svga_pipe_blend.c +++ b/src/gallium/drivers/svga/svga_pipe_blend.c @@ -126,7 +126,7 @@ static void define_blend_state_object(struct svga_context *svga, struct svga_blend_state *bs) { - SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS]; + SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS]; int i; assert(svga_have_vgpu10(svga)); diff --git a/src/gallium/drivers/svga/svga_resource_texture.c b/src/gallium/drivers/svga/svga_resource_texture.c index d367b77c122..2b937574061 100644 --- a/src/gallium/drivers/svga/svga_resource_texture.c +++ b/src/gallium/drivers/svga/svga_resource_texture.c @@ -6,8 +6,9 @@ */ #include "svga3d_reg.h" -#include "svga3d_surfacedefs.h" +#include "vmw_surf_defs.h" +#include "include/svga3d_surfacedefs.h" #include "pipe/p_state.h" #include "pipe/p_defines.h" #include "util/u_thread.h" @@ -422,13 +423,13 @@ svga_texture_transfer_map_direct(struct svga_context *svga, (tex->b.target == PIPE_TEXTURE_2D_ARRAY) || (tex->b.target == PIPE_TEXTURE_CUBE_ARRAY)) { st->base.layer_stride = - svga3dsurface_get_image_offset(tex->key.format, baseLevelSize, - tex->b.last_level + 1, 1, 0); + vmw_surf_get_image_offset(tex->key.format, baseLevelSize, + tex->b.last_level + 1, 1, 0); } - offset = svga3dsurface_get_image_offset(tex->key.format, baseLevelSize, - tex->b.last_level + 1, /* numMips */ - st->slice, level); + offset = vmw_surf_get_image_offset(tex->key.format, baseLevelSize, + tex->b.last_level + 1, /* numMips */ + st->slice, level); if (level > 0) { assert(offset > 0); } @@ -436,11 +437,11 @@ svga_texture_transfer_map_direct(struct svga_context *svga, mip_width = u_minify(tex->b.width0, level); mip_height = u_minify(tex->b.height0, level); - offset += svga3dsurface_get_pixel_offset(tex->key.format, - mip_width, mip_height, - st->box.x, - st->box.y, - st->box.z); + offset += vmw_surf_get_pixel_offset(tex->key.format, + mip_width, mip_height, + st->box.x, + st->box.y, + st->box.z); return (void *) (map + offset); } @@ -1541,10 +1542,10 @@ svga_texture_device_format_has_alpha(struct pipe_resource *texture) /* the svga_texture() call below is invalid for PIPE_BUFFER resources */ assert(texture->target != PIPE_BUFFER); - const struct svga3d_surface_desc *surf_desc = - svga3dsurface_get_desc(svga_texture(texture)->key.format); + const struct SVGA3dSurfaceDesc *surf_desc = + vmw_surf_get_desc(svga_texture(texture)->key.format); - enum svga3d_block_desc block_desc = surf_desc->block_desc; + enum SVGA3dBlockDesc block_desc = surf_desc->blockDesc; return !!((block_desc & SVGA3DBLOCKDESC_ALPHA) || ((block_desc == SVGA3DBLOCKDESC_TYPELESS) && diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index 8c0d0d81f39..6fdea8fffdb 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -25,6 +25,7 @@ #include "svga_resource.h" #include "svga_debug.h" +#include "vm_basic_types.h" #include "svga3d_shaderdefs.h" #include "VGPU10ShaderTokens.h" @@ -350,7 +351,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param) /* According to the spec, max varyings does not include the components * for position, so remove one count from the max for position. */ - return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS-1 : 10; + return sws->have_vgpu10 ? VGPU10_MAX_PS_INPUTS-1 : 10; case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: return sws->have_coherent; @@ -632,7 +633,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen, return 64; case PIPE_SHADER_CAP_MAX_INPUTS: if (shader == PIPE_SHADER_FRAGMENT) - return VGPU10_MAX_FS_INPUTS; + return VGPU10_MAX_PS_INPUTS; else if (shader == PIPE_SHADER_GEOMETRY) return svgascreen->max_gs_inputs; else if (shader == PIPE_SHADER_TESS_CTRL) @@ -643,7 +644,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen, return svgascreen->max_vs_inputs; case PIPE_SHADER_CAP_MAX_OUTPUTS: if (shader == PIPE_SHADER_FRAGMENT) - return VGPU10_MAX_FS_OUTPUTS; + return VGPU10_MAX_PS_OUTPUTS; else if (shader == PIPE_SHADER_GEOMETRY) return VGPU10_MAX_GS_OUTPUTS; else if (shader == PIPE_SHADER_TESS_CTRL) diff --git a/src/gallium/drivers/svga/svga_screen_cache.h b/src/gallium/drivers/svga/svga_screen_cache.h index 1bfa30ee896..42924b89057 100644 --- a/src/gallium/drivers/svga/svga_screen_cache.h +++ b/src/gallium/drivers/svga/svga_screen_cache.h @@ -8,8 +8,6 @@ #ifndef SVGA_SCREEN_CACHE_H_ #define SVGA_SCREEN_CACHE_H_ - -#include "svga_types.h" #include "svga_reg.h" #include "svga3d_reg.h" diff --git a/src/gallium/drivers/svga/svga_state_constants.c b/src/gallium/drivers/svga/svga_state_constants.c index a6c233a44a9..3cef4558d51 100644 --- a/src/gallium/drivers/svga/svga_state_constants.c +++ b/src/gallium/drivers/svga/svga_state_constants.c @@ -28,7 +28,7 @@ static unsigned svga_get_image_size_constant(const struct svga_context *svga, float **dest, enum pipe_shader_type shader, unsigned num_image_views, - const struct svga_image_view images[PIPE_SHADER_TYPES][SVGA3D_MAX_UAVIEWS]) + const struct svga_image_view images[PIPE_SHADER_TYPES][SVGA_MAX_IMAGES]) { uint32_t *dest_u = (uint32_t *) *dest; diff --git a/src/gallium/drivers/svga/svga_state_framebuffer.c b/src/gallium/drivers/svga/svga_state_framebuffer.c index 2f611ae1345..41357e5078a 100644 --- a/src/gallium/drivers/svga/svga_state_framebuffer.c +++ b/src/gallium/drivers/svga/svga_state_framebuffer.c @@ -166,7 +166,7 @@ static enum pipe_error emit_fb_vgpu10(struct svga_context *svga) { const struct svga_screen *ss = svga_screen(svga->pipe.screen); - struct pipe_surface *rtv[SVGA3D_MAX_RENDER_TARGETS]; + struct pipe_surface *rtv[SVGA3D_DX_MAX_RENDER_TARGETS]; struct pipe_surface *dsv; struct pipe_framebuffer_state *curr = &svga->curr.framebuffer; struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer; diff --git a/src/gallium/drivers/svga/svga_swtnl_backend.c b/src/gallium/drivers/svga/svga_swtnl_backend.c index 45b3f3c8fc6..51525b0c021 100644 --- a/src/gallium/drivers/svga/svga_swtnl_backend.c +++ b/src/gallium/drivers/svga/svga_swtnl_backend.c @@ -18,7 +18,6 @@ #include "svga_state.h" #include "svga_swtnl.h" -#include "svga_types.h" #include "svga_reg.h" #include "svga3d_reg.h" #include "svga_draw.h" diff --git a/src/gallium/drivers/svga/svga_swtnl_private.h b/src/gallium/drivers/svga/svga_swtnl_private.h index d3727583612..acdad81911c 100644 --- a/src/gallium/drivers/svga/svga_swtnl_private.h +++ b/src/gallium/drivers/svga/svga_swtnl_private.h @@ -11,7 +11,6 @@ #include "svga_swtnl.h" #include "draw/draw_vertex.h" -#include "svga_types.h" #include "svga3d_reg.h" /** diff --git a/src/gallium/drivers/svga/svga_tgsi_emit.h b/src/gallium/drivers/svga/svga_tgsi_emit.h index c424b2f06f5..2eb2618eb0a 100644 --- a/src/gallium/drivers/svga/svga_tgsi_emit.h +++ b/src/gallium/drivers/svga/svga_tgsi_emit.h @@ -12,6 +12,7 @@ #include "svga_hw_reg.h" #include "svga_shader.h" #include "svga_tgsi.h" +#include "vm_basic_types.h" #include "svga3d_shaderdefs.h" struct src_register diff --git a/src/gallium/drivers/svga/svga_tgsi_insn.c b/src/gallium/drivers/svga/svga_tgsi_insn.c index 2118086c56d..97f82183f5c 100644 --- a/src/gallium/drivers/svga/svga_tgsi_insn.c +++ b/src/gallium/drivers/svga/svga_tgsi_insn.c @@ -1039,7 +1039,7 @@ emit_if(struct svga_shader_emitter *emit, struct src_register zero = get_zero_immediate(emit); SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC ); - if_token.control = SVGA3DOPCOMPC_NE; + if_token.control = SVGA3DOPCOMP_NE; if (SVGA3dShaderGetRegType(src0.base.value) == SVGA3DREG_CONST) { /* @@ -1444,7 +1444,7 @@ emit_conditional(struct svga_shader_emitter *emit, setp_token = inst_token_setp(SVGA3DOPCOMP_GT); break; case PIPE_FUNC_NOTEQUAL: - setp_token = inst_token_setp(SVGA3DOPCOMPC_NE); + setp_token = inst_token_setp(SVGA3DOPCOMP_NE); break; case PIPE_FUNC_GEQUAL: setp_token = inst_token_setp(SVGA3DOPCOMP_GE); diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c index e3b842f07eb..53cb3acf4e9 100644 --- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c +++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c @@ -664,7 +664,7 @@ check_register_index(struct svga_shader_emitter_v10 *emit, (emit->unit == PIPE_SHADER_GEOMETRY && index >= emit->max_gs_inputs) || (emit->unit == PIPE_SHADER_FRAGMENT && - index >= VGPU10_MAX_FS_INPUTS) || + index >= VGPU10_MAX_PS_INPUTS) || (emit->unit == PIPE_SHADER_TESS_CTRL && index >= VGPU11_MAX_HS_INPUT_CONTROL_POINTS) || (emit->unit == PIPE_SHADER_TESS_EVAL && @@ -687,7 +687,7 @@ check_register_index(struct svga_shader_emitter_v10 *emit, (emit->unit == PIPE_SHADER_GEOMETRY && index >= VGPU10_MAX_GS_OUTPUTS) || (emit->unit == PIPE_SHADER_FRAGMENT && - index >= VGPU10_MAX_FS_OUTPUTS) || + index >= VGPU10_MAX_PS_OUTPUTS) || (emit->unit == PIPE_SHADER_TESS_CTRL && index >= VGPU11_MAX_HS_OUTPUTS + 2) || (emit->unit == PIPE_SHADER_TESS_EVAL && diff --git a/src/gallium/drivers/svga/svga_winsys.h b/src/gallium/drivers/svga/svga_winsys.h index 31c44a8df9d..95a509d95c5 100644 --- a/src/gallium/drivers/svga/svga_winsys.h +++ b/src/gallium/drivers/svga/svga_winsys.h @@ -17,7 +17,6 @@ #ifndef SVGA_WINSYS_H_ #define SVGA_WINSYS_H_ -#include "svga_types.h" #include "svga3d_types.h" #include "svga_reg.h" #include "svga3d_reg.h" diff --git a/src/gallium/drivers/svga/svgadump/svga_dump.c b/src/gallium/drivers/svga/svgadump/svga_dump.c index 46c0d865c14..c8c96221b05 100644 --- a/src/gallium/drivers/svga/svgadump/svga_dump.c +++ b/src/gallium/drivers/svga/svgadump/svga_dump.c @@ -13,7 +13,6 @@ */ #include "../svga_format.h" -#include "svga_types.h" #include "svga_shader_dump.h" #include "svga3d_reg.h" diff --git a/src/gallium/drivers/svga/svgadump/svga_dump.py b/src/gallium/drivers/svga/svgadump/svga_dump.py index 4adf1f7561c..b29650b8f7b 100644 --- a/src/gallium/drivers/svga/svgadump/svga_dump.py +++ b/src/gallium/drivers/svga/svgadump/svga_dump.py @@ -300,7 +300,6 @@ def main(): print ' * Generated automatically from svga3d_reg.h by svga_dump.py.' print ' */' print - print '#include "svga_types.h"' print '#include "svga_shader_dump.h"' print '#include "svga3d_reg.h"' print @@ -314,8 +313,7 @@ def main(): ) headers = [ - 'svga_types.h', - 'svga3d_reg.h', + 'svga3d_reg.h', ] decls = parser.parse(headers, config, parser.COMPILATION_MODE.ALL_AT_ONCE) diff --git a/src/gallium/drivers/svga/svgadump/svga_shader_dump.c b/src/gallium/drivers/svga/svgadump/svga_shader_dump.c index ec74d6f3bbf..07f0f153a60 100644 --- a/src/gallium/drivers/svga/svgadump/svga_shader_dump.c +++ b/src/gallium/drivers/svga/svgadump/svga_shader_dump.c @@ -95,7 +95,7 @@ static void dump_op( struct sh_op op, const char *mnemonic ) case SVGA3DOPCOMP_LT: _debug_printf("_lt"); break; - case SVGA3DOPCOMPC_NE: + case SVGA3DOPCOMP_NE: _debug_printf("_ne"); break; case SVGA3DOPCOMP_LE: diff --git a/src/gallium/winsys/svga/drm/vmw_screen_dri.c b/src/gallium/winsys/svga/drm/vmw_screen_dri.c index f79a9071d99..2b24cefbc24 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_dri.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_dri.c @@ -15,7 +15,7 @@ #include "vmw_surface.h" #include "vmw_buffer.h" #include "svga_drm_public.h" -#include "svga3d_surfacedefs.h" +#include "vmw_surf_defs.h" #include "frontend/drm_driver.h" @@ -290,9 +290,9 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws, base_size.width = size.width; base_size.height = size.height; base_size.depth = size.depth; - vsrf->size = svga3dsurface_get_serialized_size(rep->format, base_size, - rep->mip_levels[0], - false); + vsrf->size = vmw_surf_get_serialized_size(rep->format, base_size, + rep->mip_levels[0], + false); return ssrf; diff --git a/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c b/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c index 895bfdc0559..971a40af947 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c @@ -25,7 +25,7 @@ #include "vmw_fence.h" #include "xf86drm.h" #include "vmwgfx_drm.h" -#include "svga3d_caps.h" +#include "svga3d_devcaps.h" #include "svga3d_reg.h" #include "util/os_mman.h" @@ -902,6 +902,11 @@ vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid) } +struct svga_3d_compat_cap { + SVGA3dFifoCapsRecordHeader header; + SVGA3dFifoCapPair pairs[SVGA3D_DEVCAP_MAX]; +}; + static int vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws, const uint32_t *cap_buffer) @@ -916,9 +921,9 @@ vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws, return 0; } else { const uint32 *capsBlock; - const SVGA3dCapsRecord *capsRecord = NULL; + const struct svga_3d_compat_cap *capsRecord = NULL; uint32 offset; - const SVGA3dCapPair *capArray; + const SVGA3dFifoCapPair *capArray; int numCaps, index; /* @@ -926,11 +931,11 @@ vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws, */ capsBlock = cap_buffer; for (offset = 0; capsBlock[offset] != 0; offset += capsBlock[offset]) { - const SVGA3dCapsRecord *record; + const struct svga_3d_compat_cap *record; assert(offset < SVGA_FIFO_3D_CAPS_SIZE); - record = (const SVGA3dCapsRecord *) (capsBlock + offset); - if ((record->header.type >= SVGA3DCAPS_RECORD_DEVCAPS_MIN) && - (record->header.type <= SVGA3DCAPS_RECORD_DEVCAPS_MAX) && + record = (const struct svga_3d_compat_cap *) (capsBlock + offset); + if ((record->header.type >= 0) && + (record->header.type <= SVGA3D_DEVCAP_MAX) && (!capsRecord || (record->header.type > capsRecord->header.type))) { capsRecord = record; } @@ -942,7 +947,7 @@ vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws, /* * Calculate the number of caps from the size of the record. */ - capArray = (const SVGA3dCapPair *) capsRecord->data; + capArray = (const SVGA3dFifoCapPair *) capsRecord->pairs; numCaps = (int) ((capsRecord->header.length * sizeof(uint32) - sizeof capsRecord->header) / (2 * sizeof(uint32))); diff --git a/src/gallium/winsys/svga/drm/vmw_screen_svga.c b/src/gallium/winsys/svga/drm/vmw_screen_svga.c index 606e51ee68f..ae0bd6ac5be 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_svga.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_svga.c @@ -20,7 +20,8 @@ #include #include "svga_cmd.h" -#include "svga3d_caps.h" +#include "svga3d_devcaps.h" +#include "vmw_surf_defs.h" #include "c11/threads.h" #include "util/os_file.h" @@ -39,7 +40,6 @@ #include "vmw_shader.h" #include "vmw_query.h" #include "vmwgfx_drm.h" -#include "svga3d_surfacedefs.h" #include "xf86drm.h" /** @@ -505,10 +505,10 @@ vmw_svga_winsys_surface_create(struct svga_winsys_screen *sws, * Used for the backing buffer GB surfaces, and to approximate * when to flush on non-GB hosts. */ - buffer_size = svga3dsurface_get_serialized_size_extended(format, size, - numMipLevels, - numLayers, - num_samples); + buffer_size = vmw_surf_get_serialized_size_extended(format, size, + numMipLevels, + numLayers, + num_samples); if (flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT) buffer_size += sizeof(SVGA3dDXSOState); @@ -578,9 +578,9 @@ vmw_svga_winsys_surface_can_create(struct svga_winsys_screen *sws, struct vmw_winsys_screen *vws = vmw_winsys_screen(sws); uint32_t buffer_size; - buffer_size = svga3dsurface_get_serialized_size(format, size, - numMipLevels, - numLayers); + buffer_size = vmw_surf_get_serialized_size(format, size, + numMipLevels, + numLayers); if (numSamples > 1) buffer_size *= numSamples;