nvk: Convert shader addresses to offsets in nvk_shader.c

Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>

src/nouveau/vulkan/nvk_cmd_buffer.c

@@ -778,7 +778,7 @@ nvk_cmd_buffer_get_cbuf_descriptor(struct nvk_cmd_buffer *cmd,
 
    case NVK_CBUF_TYPE_SHADER_DATA:
       *desc_out = (struct nvk_buffer_address) {
-         .base_addr = nvk_shader_data_address(shader),
+         .base_addr = shader->data_addr,
          .size = shader->data_size,
       };
       return true;

src/nouveau/vulkan/nvk_compute_pipeline.c

@@ -86,7 +86,7 @@ nva0c0_compute_setup_launch_desc_template(uint32_t *qmd,
    else
       unreachable("Invalid shared memory size");
 
-   uint64_t addr = nvk_shader_address(shader);
+   uint64_t addr = shader->hdr_addr;
    assert(addr < 0xffffffff);
    NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET, addr);
    NVA0C0_QMDV00_06_VAL_SET(qmd, REGISTER_COUNT, shader->info.num_gprs);
@@ -99,7 +99,7 @@ nvc0c0_compute_setup_launch_desc_template(uint32_t *qmd,
 {
    base_compute_setup_launch_desc_template(qmd, shader, C0C0, 02, 01);
 
-   uint64_t addr = nvk_shader_address(shader);
+   uint64_t addr = shader->hdr_addr;
    assert(addr < 0xffffffff);
 
    NVC0C0_QMDV02_01_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);
@@ -124,7 +124,7 @@ nvc3c0_compute_setup_launch_desc_template(uint32_t *qmd,
 
    NVC3C0_QMDV02_02_VAL_SET(qmd, REGISTER_COUNT_V, shader->info.num_gprs);
 
-   uint64_t addr = nvk_shader_address(shader);
+   uint64_t addr = shader->hdr_addr;
    NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_LOWER, addr & 0xffffffff);
    NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_UPPER, addr >> 32);
 }
@@ -146,7 +146,7 @@ nvc6c0_compute_setup_launch_desc_template(uint32_t *qmd,
 
    NVC6C0_QMDV03_00_VAL_SET(qmd, REGISTER_COUNT_V, shader->info.num_gprs);
 
-   uint64_t addr = nvk_shader_address(shader);
+   uint64_t addr = shader->hdr_addr;
    NVC6C0_QMDV03_00_VAL_SET(qmd, PROGRAM_ADDRESS_LOWER, addr & 0xffffffff);
    NVC6C0_QMDV03_00_VAL_SET(qmd, PROGRAM_ADDRESS_UPPER, addr >> 32);
 }

src/nouveau/vulkan/nvk_graphics_pipeline.c

@@ -325,7 +325,7 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
       if (stage != MESA_SHADER_FRAGMENT)
          last_geom = shader;
 
-      uint64_t addr = nvk_shader_address(shader);
+      uint64_t addr = shader->hdr_addr;
       if (dev->pdev->info.cls_eng3d >= VOLTA_A) {
          P_MTHD(p, NVC397, SET_PIPELINE_PROGRAM_ADDRESS_A(idx));
          P_NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A(p, idx, addr >> 32);

src/nouveau/vulkan/nvk_heap.c

@@ -166,12 +166,7 @@ nvk_heap_alloc_locked(struct nvk_device *dev, struct nvk_heap *heap,
          assert(heap->bos[bo_idx].bo != NULL);
          assert(bo_offset + size <= heap->bos[bo_idx].bo->size);
 
-         if (heap->base_addr != 0) {
-            assert(bo_idx == 0);
-            *addr_out = bo_offset;
-         } else {
-            *addr_out = heap->bos[bo_idx].addr + bo_offset;
-         }
+         *addr_out = heap->bos[bo_idx].addr + bo_offset;
          if (map_out != NULL) {
             assert(heap->bos[bo_idx].map != NULL);
             *map_out = (char *)heap->bos[bo_idx].map + bo_offset;

src/nouveau/vulkan/nvk_shader.c

@@ -574,11 +574,19 @@ nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader)
 #endif
 
    VkResult result = nvk_heap_upload(dev, &dev->shader_heap, data,
-                                     total_size, alignment, &shader->upload_addr);
+                                     total_size, alignment,
+                                     &shader->upload_addr);
    if (result == VK_SUCCESS) {
       shader->upload_size = total_size;
-      shader->hdr_offset = hdr_offset;
-      shader->data_offset = data_offset;
+
+      shader->hdr_addr = shader->upload_addr + hdr_offset;
+      if (dev->pdev->info.cls_eng3d < VOLTA_A) {
+         const uint64_t heap_base_addr =
+            nvk_heap_contiguous_base_address(&dev->shader_heap);
+         assert(shader->upload_addr - heap_base_addr < UINT32_MAX);
+         shader->hdr_addr -= heap_base_addr;
+      }
+      shader->data_addr = shader->upload_addr + data_offset;
    }
    free(data);
 

src/nouveau/vulkan/nvk_shader.h

@@ -70,22 +70,19 @@ struct nvk_shader {
 
    uint32_t upload_size;
    uint64_t upload_addr;
-   uint32_t hdr_offset;
-   uint32_t data_offset;
+
+   /* Address of the shader header (or start of the shader code) for compute
+    * shaders.
+    *
+    * Prior to Volta, this is relative to the start of the shader heap. On
+    * Volta and later, it's an absolute address.
+    */
+   uint64_t hdr_addr;
+
+   /* Address of the start of the shader data section */
+   uint64_t data_addr;
 };
 
-static inline uint64_t
-nvk_shader_address(const struct nvk_shader *shader)
-{
-   return shader->upload_addr + shader->hdr_offset;
-}
-
-static inline uint64_t
-nvk_shader_data_address(const struct nvk_shader *shader)
-{
-   return shader->upload_addr + shader->data_offset;
-}
-
 static inline bool
 nvk_shader_is_enabled(const struct nvk_shader *shader)
 {