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r600: don't reschedule INTERP_LOAD_P0

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With the NIR code, we have instructions groups that use
INTERP_LOAD_P0 that don't fill all slots. Just make sure
the backend scheduler doesn't fill in INTERP_LOAD_P0
instructions with a different LDS location.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15714>
This commit is contained in:
Gert Wollny
2022-02-10 18:44:13 +01:00
committed by Marge Bot
parent 3c4644afb0
commit 04fd9a6488
1 changed files with 4 additions and 0 deletions
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src/gallium/drivers/r600/r600_asm.c
+4
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@@ -817,6 +817,8 @@ static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu
if (is_alu_once_inst(prev[i]))
return 0;
if (prev[i]->op == ALU_OP1_INTERP_LOAD_P0)
interp_xz |= 3;
if (prev[i]->op == ALU_OP2_INTERP_X)
interp_xz |= 1;
if (prev[i]->op == ALU_OP2_INTERP_Z)
@@ -827,6 +829,8 @@ static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu
return 0;
if (is_alu_once_inst(slots[i]))
return 0;
if (slots[i]->op == ALU_OP1_INTERP_LOAD_P0)
interp_xz |= 3;
if (slots[i]->op == ALU_OP2_INTERP_X)
interp_xz |= 1;
if (slots[i]->op == ALU_OP2_INTERP_Z)