From 04fd9a64881c50ad6c12f8bfb93f1a6c2c8e8e8d Mon Sep 17 00:00:00 2001 From: Gert Wollny Date: Thu, 10 Feb 2022 18:44:13 +0100 Subject: [PATCH] r600: don't reschedule INTERP_LOAD_P0 With the NIR code, we have instructions groups that use INTERP_LOAD_P0 that don't fill all slots. Just make sure the backend scheduler doesn't fill in INTERP_LOAD_P0 instructions with a different LDS location. Signed-off-by: Gert Wollny Acked-by: Emma Anholt Part-of: --- src/gallium/drivers/r600/r600_asm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index bce21abf178..565c657e7bc 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -817,6 +817,8 @@ static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu if (is_alu_once_inst(prev[i])) return 0; + if (prev[i]->op == ALU_OP1_INTERP_LOAD_P0) + interp_xz |= 3; if (prev[i]->op == ALU_OP2_INTERP_X) interp_xz |= 1; if (prev[i]->op == ALU_OP2_INTERP_Z) @@ -827,6 +829,8 @@ static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu return 0; if (is_alu_once_inst(slots[i])) return 0; + if (slots[i]->op == ALU_OP1_INTERP_LOAD_P0) + interp_xz |= 3; if (slots[i]->op == ALU_OP2_INTERP_X) interp_xz |= 1; if (slots[i]->op == ALU_OP2_INTERP_Z)