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aco: remove dead code in nir_intrinsic_xfb_counter_{add,sub}_amd

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This code path is only used by GFX11 now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25903>
This commit is contained in:
Samuel Pitoiset
2023-10-26 12:32:50 +02:00
committed by Marge Bot
parent d390cd7c5d
commit 0477346c0b
1 changed files with 4 additions and 23 deletions
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src/amd/compiler/aco_instruction_selection.cpp
+4 -23
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@@ -9027,21 +9027,12 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
aco_opcode::p_create_vector, Format::PSEUDO, instr->num_components, 1)};
unsigned write_mask = nir_intrinsic_write_mask(instr);
const bool use_gds_registers = ctx->options->gfx_level >= GFX11;
for (unsigned i = 0; i < instr->num_components; i++) {
if (write_mask & (1 << i)) {
Temp chan_counter = emit_extract_vector(ctx, counter, i, v1);
if (use_gds_registers) {
ds_instr = bld.ds(aco_opcode::ds_add_gs_reg_rtn, bld.def(v1), Operand(),
chan_counter, i * 4, 0u, true);
} else {
m = bld.m0((Temp)bld.copy(bld.def(s1, m0), Operand::c32(0x100u)));
ds_instr = bld.ds(aco_opcode::ds_add_rtn_u32, bld.def(v1), gds_base, chan_counter, m,
i * 4, 0u, true);
}
ds_instr = bld.ds(aco_opcode::ds_add_gs_reg_rtn, bld.def(v1), Operand(), chan_counter,
i * 4, 0u, true);
ds_instr->ds().sync = memory_sync_info(storage_gds, semantic_atomicrmw);
vec->operands[i] = Operand(ds_instr->definitions[0].getTemp());
@@ -9064,25 +9055,15 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
break;
}
case nir_intrinsic_xfb_counter_sub_amd: {
const bool use_gds_registers = ctx->options->gfx_level >= GFX11;
unsigned write_mask = nir_intrinsic_write_mask(instr);
Temp counter = get_ssa_temp(ctx, instr->src[0].ssa);
Temp gds_base = bld.copy(bld.def(v1), Operand::c32(0u));
u_foreach_bit (i, write_mask) {
Temp chan_counter = emit_extract_vector(ctx, counter, i, v1);
Instruction* ds_instr;
if (use_gds_registers) {
ds_instr = bld.ds(aco_opcode::ds_sub_gs_reg_rtn, bld.def(v1), Operand(), chan_counter,
i * 4, 0u, true);
} else {
Operand m = bld.m0((Temp)bld.copy(bld.def(s1, m0), Operand::c32(0x100u)));
ds_instr = bld.ds(aco_opcode::ds_sub_rtn_u32, bld.def(v1), gds_base, chan_counter, m,
i * 4, 0u, true);
}
ds_instr = bld.ds(aco_opcode::ds_sub_gs_reg_rtn, bld.def(v1), Operand(), chan_counter,
i * 4, 0u, true);
ds_instr->ds().sync = memory_sync_info(storage_gds, semantic_atomicrmw);
}
break;