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ac/nir: remove dead code in nir_intrinsic_xfb_counter_{add,sub}_amd

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This code path is only used by GFX11 now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25903>
This commit is contained in:
Samuel Pitoiset
2023-10-26 12:31:43 +02:00
committed by Marge Bot
parent 5176f75e0d
commit d390cd7c5d
1 changed files with 9 additions and 29 deletions
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src/amd/llvm/ac_nir_to_llvm.c
+9 -29
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@@ -3654,9 +3654,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
}
case nir_intrinsic_ordered_xfb_counter_add_amd: {
/* must be called in a single lane of a workgroup. */
const bool use_gds_registers = ctx->ac.gfx_level >= GFX11;
LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
LLVMValueRef gdsbase = LLVMBuildIntToPtr(ctx->ac.builder, ctx->ac.i32_0, gdsptr, "");
/* Gfx11 GDS instructions only operate on the first active lane. All other lanes are
* ignored. So are their EXEC bits. This uses the mutex feature of ds_ordered_count
@@ -3705,19 +3703,11 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
LLVMBuildExtractElement(ctx->ac.builder, count_vec,
LLVMConstInt(ctx->ac.i32, i, false), "");
if (write_mask & (1 << i)) {
if (use_gds_registers) {
/* The offset is a relative offset from GDS_STRMOUT_DWORDS_WRITTEN_0. */
global_count[i] =
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.add.gs.reg.rtn.i32", ctx->ac.i32,
(LLVMValueRef[]){value, LLVMConstInt(ctx->ac.i32, i * 4, 0)},
2, 0);
} else {
LLVMValueRef gds_ptr =
ac_build_gep_ptr(&ctx->ac, ctx->ac.i32, gdsbase, LLVMConstInt(ctx->ac.i32, i, 0));
global_count[i] =
LLVMBuildAtomicRMW(ctx->ac.builder, LLVMAtomicRMWBinOpAdd, gds_ptr, value,
LLVMAtomicOrderingMonotonic, false);
}
/* The offset is a relative offset from GDS_STRMOUT_DWORDS_WRITTEN_0. */
global_count[i] =
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.add.gs.reg.rtn.i32", ctx->ac.i32,
(LLVMValueRef[]){value, LLVMConstInt(ctx->ac.i32, i * 4, 0)},
2, 0);
} else {
global_count[i] = LLVMGetUndef(ctx->ac.i32);
}
@@ -3734,9 +3724,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
}
case nir_intrinsic_xfb_counter_sub_amd: {
/* must be called in a single lane of a workgroup. */
const bool use_gds_registers = ctx->ac.gfx_level >= GFX11;
LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
LLVMValueRef gdsbase = LLVMBuildIntToPtr(ctx->ac.builder, ctx->ac.i32_0, gdsptr, "");
LLVMValueRef sub_vec = get_src(ctx, instr->src[0]);
unsigned write_mask = nir_intrinsic_write_mask(instr);
@@ -3745,17 +3732,10 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
LLVMValueRef value =
LLVMBuildExtractElement(ctx->ac.builder, sub_vec,
LLVMConstInt(ctx->ac.i32, i, false), "");
if (use_gds_registers) {
/* The offset is a relative offset from GDS_STRMOUT_DWORDS_WRITTEN_0. */
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.sub.gs.reg.rtn.i32", ctx->ac.i32,
(LLVMValueRef[]){value, LLVMConstInt(ctx->ac.i32, i * 4, 0)},
2, 0);
} else {
LLVMValueRef gds_ptr =
ac_build_gep_ptr(&ctx->ac, ctx->ac.i32, gdsbase, LLVMConstInt(ctx->ac.i32, i, 0));
LLVMBuildAtomicRMW(ctx->ac.builder, LLVMAtomicRMWBinOpSub, gds_ptr, value,
LLVMAtomicOrderingMonotonic, false);
}
/* The offset is a relative offset from GDS_STRMOUT_DWORDS_WRITTEN_0. */
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.sub.gs.reg.rtn.i32", ctx->ac.i32,
(LLVMValueRef[]){value, LLVMConstInt(ctx->ac.i32, i * 4, 0)},
2, 0);
}
}
break;