ac/surface: add radeon_surf::thick_tiling

It's not worth writing a compute shader for copying 3D textures yet.
I have a sophisticated compute shader that will do it properly.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28607>
This commit is contained in:
Marek Olšák
2024-03-17 16:49:53 -04:00
parent abc327a39a
commit 03d241b256
2 changed files with 6 additions and 0 deletions
+4
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@@ -1506,6 +1506,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
surf->is_displayable = surf->is_linear || surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
surf->thick_tiling = AddrSurfInfoOut.blockSlices > 1;
/* The rotated micro tile mode doesn't work if both CMASK and RB+ are
* used at the same time. This case is not currently expected to occur
* because we don't use rotated. Enforce this restriction on all chips
@@ -1852,6 +1854,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
}
}
surf->thick_tiling = out.blockSlices > 1; /* should be 0 for depth and stencil */
if (in->flags.stencil) {
surf->u.gfx9.zs.stencil_swizzle_mode = in->swizzleMode;
surf->u.gfx9.zs.stencil_epitch =
+2
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@@ -314,6 +314,8 @@ struct radeon_surf {
uint8_t has_stencil : 1;
/* This might be true even if micro_tile_mode isn't displayable or rotated. */
uint8_t is_displayable : 1;
/* Thick tiling means 3D tiles. Use 3D compute workgroups for blits. (4x4x4 works well) */
uint8_t thick_tiling : 1;
uint8_t first_mip_tail_level : 4;
/* These are return values. Some of them can be set by the caller, but