diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 6e881cf1669..40d5ba24a01 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1506,6 +1506,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i
    surf->is_displayable = surf->is_linear || surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
                           surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
 
+   surf->thick_tiling = AddrSurfInfoOut.blockSlices > 1;
+
    /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
     * used at the same time. This case is not currently expected to occur
     * because we don't use rotated. Enforce this restriction on all chips
@@ -1852,6 +1854,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
       }
    }
 
+   surf->thick_tiling = out.blockSlices > 1; /* should be 0 for depth and stencil */
+
    if (in->flags.stencil) {
       surf->u.gfx9.zs.stencil_swizzle_mode = in->swizzleMode;
       surf->u.gfx9.zs.stencil_epitch =
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 83338f34134..58229ef6f96 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -314,6 +314,8 @@ struct radeon_surf {
    uint8_t has_stencil : 1;
    /* This might be true even if micro_tile_mode isn't displayable or rotated. */
    uint8_t is_displayable : 1;
+   /* Thick tiling means 3D tiles. Use 3D compute workgroups for blits. (4x4x4 works well) */
+   uint8_t thick_tiling : 1;
    uint8_t first_mip_tail_level : 4;
 
    /* These are return values. Some of them can be set by the caller, but