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nir, anv, hasvk, radv: pull uses_wide_subgroup_intrinsics into shader_info

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
This commit is contained in:
Marcin Ślusarz
2022-09-19 12:55:19 +02:00
committed by Marge Bot
parent de5b137a2d
commit 037404b441
5 changed files with 11 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_shader_info.c
+1 -1
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@@ -627,7 +627,7 @@ gather_shader_info_cs(struct radv_device *device, const nir_shader *nir,
/* Games don't always request full subgroups when they should, which can cause bugs if cswave32
* is enabled.
*/
if (device->physical_device->cs_wave_size == 32 && nir->info.cs.uses_wide_subgroup_intrinsics &&
if (device->physical_device->cs_wave_size == 32 && nir->info.uses_wide_subgroup_intrinsics &&
!req_subgroup_size && local_size % RADV_SUBGROUP_SIZE == 0)
require_full_subgroups = true;
src/compiler/nir/nir_gather_info.c
+3 -4
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@@ -833,10 +833,9 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
case nir_intrinsic_write_invocation_amd:
if (shader->info.stage == MESA_SHADER_FRAGMENT)
shader->info.fs.needs_all_helper_invocations = true;
if (shader->info.stage == MESA_SHADER_COMPUTE)
shader->info.cs.uses_wide_subgroup_intrinsics = true;
if (gl_shader_stage_is_mesh(shader->info.stage))
shader->info.mesh.uses_wide_subgroup_intrinsics = true;
if (shader->info.stage == MESA_SHADER_COMPUTE ||
gl_shader_stage_is_mesh(shader->info.stage))
shader->info.uses_wide_subgroup_intrinsics = true;
break;
case nir_intrinsic_end_primitive:
src/compiler/shader_info.h
+5 -7
View File
@@ -243,6 +243,11 @@ typedef struct shader_info {
enum gl_subgroup_size subgroup_size;
/**
* Uses subgroup intrinsics which can communicate across a quad.
*/
bool uses_wide_subgroup_intrinsics;
/* Transform feedback buffer strides in dwords, max. 1K - 4. */
uint8_t xfb_stride[MAX_XFB_BUFFERS];
@@ -500,11 +505,6 @@ typedef struct shader_info {
* AddressingModelPhysical64: 64
*/
unsigned ptr_size;
/**
* Uses subgroup intrinsics which can communicate across a quad.
*/
bool uses_wide_subgroup_intrinsics;
} cs;
/* Applies to both TCS and TES. */
@@ -532,8 +532,6 @@ typedef struct shader_info {
/* Applies to MESH. */
struct {
bool uses_wide_subgroup_intrinsics;
/* Bit mask of MS outputs that are used
* with an index that is NOT the local invocation index.
*/
src/intel/vulkan/anv_pipeline.c
+1 -6
View File
@@ -1644,15 +1644,10 @@ anv_graphics_pipeline_load_nir(struct anv_graphics_pipeline *pipeline,
static void
anv_fixup_subgroup_size(struct anv_device *device, struct shader_info *info)
{
bool uses_wide_subgroup_intrinsics;
switch (info->stage) {
case MESA_SHADER_COMPUTE:
uses_wide_subgroup_intrinsics = info->cs.uses_wide_subgroup_intrinsics;
break;
case MESA_SHADER_TASK:
case MESA_SHADER_MESH:
uses_wide_subgroup_intrinsics = info->mesh.uses_wide_subgroup_intrinsics;
break;
default:
return;
@@ -1667,7 +1662,7 @@ anv_fixup_subgroup_size(struct anv_device *device, struct shader_info *info)
* subgroup than we choose for the execution.
*/
if (device->physical->instance->assume_full_subgroups &&
uses_wide_subgroup_intrinsics &&
info->uses_wide_subgroup_intrinsics &&
info->subgroup_size == SUBGROUP_SIZE_API_CONSTANT &&
local_size &&
local_size % BRW_SUBGROUP_SIZE == 0)
src/intel/vulkan_hasvk/anv_pipeline.c
+1 -1
View File
@@ -1679,7 +1679,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
* subgroup than we choose for the execution.
*/
if (device->physical->instance->assume_full_subgroups &&
stage.nir->info.cs.uses_wide_subgroup_intrinsics &&
stage.nir->info.uses_wide_subgroup_intrinsics &&
stage.nir->info.subgroup_size == SUBGROUP_SIZE_API_CONSTANT &&
local_size &&
local_size % BRW_SUBGROUP_SIZE == 0)