diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 336ca1cbe2b..7844ed2b8ee 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -627,7 +627,7 @@ gather_shader_info_cs(struct radv_device *device, const nir_shader *nir,
    /* Games don't always request full subgroups when they should, which can cause bugs if cswave32
     * is enabled.
     */
-   if (device->physical_device->cs_wave_size == 32 && nir->info.cs.uses_wide_subgroup_intrinsics &&
+   if (device->physical_device->cs_wave_size == 32 && nir->info.uses_wide_subgroup_intrinsics &&
        !req_subgroup_size && local_size % RADV_SUBGROUP_SIZE == 0)
       require_full_subgroups = true;
 
diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c
index 50dd5c2e82b..8b13a699e48 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -833,10 +833,9 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
    case nir_intrinsic_write_invocation_amd:
       if (shader->info.stage == MESA_SHADER_FRAGMENT)
          shader->info.fs.needs_all_helper_invocations = true;
-      if (shader->info.stage == MESA_SHADER_COMPUTE)
-         shader->info.cs.uses_wide_subgroup_intrinsics = true;
-      if (gl_shader_stage_is_mesh(shader->info.stage))
-         shader->info.mesh.uses_wide_subgroup_intrinsics = true;
+      if (shader->info.stage == MESA_SHADER_COMPUTE ||
+          gl_shader_stage_is_mesh(shader->info.stage))
+         shader->info.uses_wide_subgroup_intrinsics = true;
       break;
 
    case nir_intrinsic_end_primitive:
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 0d0c9fa040c..86d197655fa 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -243,6 +243,11 @@ typedef struct shader_info {
 
    enum gl_subgroup_size subgroup_size;
 
+   /**
+    * Uses subgroup intrinsics which can communicate across a quad.
+    */
+   bool uses_wide_subgroup_intrinsics;
+
    /* Transform feedback buffer strides in dwords, max. 1K - 4. */
    uint8_t xfb_stride[MAX_XFB_BUFFERS];
 
@@ -500,11 +505,6 @@ typedef struct shader_info {
           *   AddressingModelPhysical64: 64
           */
          unsigned ptr_size;
-
-         /**
-          * Uses subgroup intrinsics which can communicate across a quad.
-          */
-         bool uses_wide_subgroup_intrinsics;
       } cs;
 
       /* Applies to both TCS and TES. */
@@ -532,8 +532,6 @@ typedef struct shader_info {
 
       /* Applies to MESH. */
       struct {
-         bool uses_wide_subgroup_intrinsics;
-
          /* Bit mask of MS outputs that are used
           * with an index that is NOT the local invocation index.
           */
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 303c777e31c..f7a2e77696e 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1644,15 +1644,10 @@ anv_graphics_pipeline_load_nir(struct anv_graphics_pipeline *pipeline,
 static void
 anv_fixup_subgroup_size(struct anv_device *device, struct shader_info *info)
 {
-   bool uses_wide_subgroup_intrinsics;
-
    switch (info->stage) {
    case MESA_SHADER_COMPUTE:
-      uses_wide_subgroup_intrinsics = info->cs.uses_wide_subgroup_intrinsics;
-      break;
    case MESA_SHADER_TASK:
    case MESA_SHADER_MESH:
-      uses_wide_subgroup_intrinsics = info->mesh.uses_wide_subgroup_intrinsics;
       break;
    default:
       return;
@@ -1667,7 +1662,7 @@ anv_fixup_subgroup_size(struct anv_device *device, struct shader_info *info)
     * subgroup than we choose for the execution.
     */
    if (device->physical->instance->assume_full_subgroups &&
-       uses_wide_subgroup_intrinsics &&
+       info->uses_wide_subgroup_intrinsics &&
        info->subgroup_size == SUBGROUP_SIZE_API_CONSTANT &&
        local_size &&
        local_size % BRW_SUBGROUP_SIZE == 0)
diff --git a/src/intel/vulkan_hasvk/anv_pipeline.c b/src/intel/vulkan_hasvk/anv_pipeline.c
index f8de43afe04..548c00bd9e6 100644
--- a/src/intel/vulkan_hasvk/anv_pipeline.c
+++ b/src/intel/vulkan_hasvk/anv_pipeline.c
@@ -1679,7 +1679,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
        * subgroup than we choose for the execution.
        */
       if (device->physical->instance->assume_full_subgroups &&
-          stage.nir->info.cs.uses_wide_subgroup_intrinsics &&
+          stage.nir->info.uses_wide_subgroup_intrinsics &&
           stage.nir->info.subgroup_size == SUBGROUP_SIZE_API_CONSTANT &&
           local_size &&
           local_size % BRW_SUBGROUP_SIZE == 0)