Kenneth Graunke
f1ab64ad74
We add several new intrinsics for accessing URB handles: - load_urb_output_handle_intel - load_urb_input_handle_intel - load_urb_input_handle_intel_indexed The latter is used by stages like TCS and GS where each input control point has a unique handle. The index is which ICP to read from. The others are for most stages, where all inputs or outputs are accessed via a single handle. Then we have URB load and store operations, split for Xe2+ (URB via LSC) and earlier (HDC OWord messages): - load_urb_vec4_intel - load_urb_lsc_intel - store_urb_vec4_intel - store_urb_lsc_intel The legacy vec4 variants take a handle and a 128-bit OWord offset as sources. Additionally, stores take a set of channel enables to mask off and avoid writing vec4 components. We don't use the WRITE_MASK const-index as our channel enables are not required to be constant. The Xe2+ LSC variants are simpler. Handles are byte offsets into the URB memory region, and offsets are expressed in bytes. So we simply add them into a single "address" source. We don't support writemasks here, as they aren't really necessary with the better addressability. (Plus, the store_cmask operations work significantly differently than the previous HDC OWord messages). We will lower disjoint writemasks to multiple stores. Based on earlier code by Lionel Landwerlin. Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38482>
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