Jason Ekstrand e8c9e65185 intel/fs: Use a pure vertical stride for large register strides ...

Register strides higher than 4 are uncommon but they can happen.  For
instance, if you have a 64-bit extract_u8 operation, we turn that into
UB -> UQ MOV with a source stride of 8.  Our previous calculation would
try to generate a stride of <32;8,8>:ub which is invalid because the
maximum horizontal stride is 4.  To solve this problem, we instead use a
stride of <8;1,0>.  As noted in the comment, this does not work as a
destination but that's ok as very few things actually generate that
stride.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: mesa-stable@lists.freedesktop.org

2017-11-07 10:37:52 -08:00

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.gitignore

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brw_cfg.cpp

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brw_cfg.h

intel/compiler: consistently use ifndef guards over pragma once

2017-03-22 16:55:22 +00:00

brw_clip_line.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_point.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_tri.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_unfilled.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_util.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip.h

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_compile_clip.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_compile_sf.c

i965: Move SF compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_compiler.c

intel/compiler: Add functions to get prog_data and prog_key sizes for a stage

2017-10-31 23:36:54 -07:00

brw_compiler.h

intel/compiler: Add functions to get prog_data and prog_key sizes for a stage

2017-10-31 23:36:54 -07:00

brw_dead_control_flow.cpp

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brw_dead_control_flow.h

intel/compiler: consistently use ifndef guards over pragma once

2017-03-22 16:55:22 +00:00

brw_disasm.c

i965: Add align1 ternary instruction disassembler support

2017-10-20 15:00:17 -07:00

brw_eu_compact.c

i965: Rename brw_inst 3src functions in preparation for align1

2017-10-20 15:00:16 -07:00

brw_eu_defines.h

i965: Add align1 ternary instruction disassembler support

2017-10-20 15:00:17 -07:00

brw_eu_emit.c

intel/eu: Use EXECUTE_1 for JMPI

2017-10-25 16:14:09 -07:00

brw_eu_util.c

intel/compiler: whitespace cleanups

2017-03-13 11:16:35 +00:00

brw_eu_validate.c

intel/compiler: brw_validate_instructions to take const void* instead of void*

2017-10-26 10:43:48 -07:00

brw_eu.c

i965: Move brw_reg_type_letters() as well

2017-08-21 14:05:23 -07:00

brw_eu.h

intel/compiler: brw_validate_instructions to take const void* instead of void*

2017-10-26 10:43:48 -07:00

brw_fs_builder.h

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brw_fs_cmod_propagation.cpp

intel/compiler: Don't propagate cmod into integer multiplies

2017-10-05 11:54:49 -07:00

brw_fs_combine_constants.cpp

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brw_fs_copy_propagation.cpp

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brw_fs_cse.cpp

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brw_fs_dead_code_eliminate.cpp

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brw_fs_generator.cpp

intel/fs: Use a pure vertical stride for large register strides

2017-11-07 10:37:52 -08:00

brw_fs_live_variables.cpp

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brw_fs_live_variables.h

intel/compiler: consistently use ifndef guards over pragma once

2017-03-22 16:55:22 +00:00

brw_fs_lower_conversions.cpp

i965/fs: rename lower_d2x to lower_conversions

2017-04-14 14:56:07 -07:00

brw_fs_lower_pack.cpp

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brw_fs_nir.cpp

i965/fs: Add brw_reg_type_from_bit_size utility method

2017-10-25 16:14:09 -07:00

brw_fs_reg_allocate.cpp

intel/fs: Take into account amount of data read in spilling cost heuristic.

2017-04-24 11:01:40 -07:00

brw_fs_register_coalesce.cpp

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brw_fs_saturate_propagation.cpp

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brw_fs_sel_peephole.cpp

i965/fs: Do not move MOVs writing the flag outside of control flow

2017-07-20 16:56:49 -07:00

brw_fs_surface_builder.cpp

i965: Mark functions static

2017-08-21 14:45:44 -07:00

brw_fs_surface_builder.h

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brw_fs_validate.cpp

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brw_fs_visitor.cpp

intel/vs: Grow the param array for clip planes

2017-10-12 22:39:30 -07:00

brw_fs.cpp

intel/fs: Don't allocate a param array for zero push constants

2017-11-02 09:55:21 -07:00

brw_fs.h

intel: Rewrite the world of push/pull params

2017-10-12 22:39:29 -07:00

brw_inst.h

i965: Add align1 ternary instruction-word support

2017-10-20 15:00:17 -07:00

brw_interpolation_map.c

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brw_ir_allocator.h

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brw_ir_fs.h

i965: Move fs_inst::has_side_effects()'s eot check to the parent class.

2017-10-19 10:19:20 -07:00

brw_ir_vec4.h

i965/vec4: don't do horizontal stride on some register file types

2017-04-14 14:56:09 -07:00

brw_nir_analyze_boolean_resolves.c

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brw_nir_analyze_ubo_ranges.c

nir: Get rid of nir_shader::stage

2017-10-20 12:49:17 -07:00

brw_nir_attribute_workarounds.c

nir: Rework conversion opcodes

2017-03-14 07:36:40 -07:00

brw_nir_lower_cs_intrinsics.c

intel/nir: Zero local index const struct for valgrind & nir_serialize

2017-10-25 12:36:21 -07:00

brw_nir_opt_peephole_ffma.c

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brw_nir_tcs_workarounds.c

nir: Get rid of nir_shader::stage

2017-10-20 12:49:17 -07:00

brw_nir_trig_workarounds.py

intel: use a flag instead of setting PYTHONPATH

2017-09-27 09:07:28 -07:00

brw_nir.c

intel/compiler: Call nir_lower_system_values in brw_preprocess_nir

2017-10-25 16:14:09 -07:00

brw_nir.h

intel: Allocate prog_data::[pull_]param deeper inside the compiler

2017-10-12 22:39:31 -07:00

brw_packed_float.c

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brw_predicated_break.cpp

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brw_reg_type.c

i965: Add align1 ternary instruction support to conversion functions

2017-10-20 15:00:17 -07:00

brw_reg_type.h

i965: Add align1 ternary instruction support to conversion functions

2017-10-20 15:00:17 -07:00

brw_reg.h

i965: Move brw_reg_type_is_floating_point to brw_reg_type.h

2017-10-20 15:00:16 -07:00

brw_schedule_instructions.cpp

i965: Use is_scheduling_barrier instead of schedule_node::is_barrier.

2017-10-19 10:19:20 -07:00

brw_shader.cpp

intel/compiler: Remove final_program_size from brw_compile_*

2017-10-31 23:36:54 -07:00

brw_shader.h

i965: Move fs_inst::has_side_effects()'s eot check to the parent class.

2017-10-19 10:19:20 -07:00

brw_vec4_builder.h

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brw_vec4_cmod_propagation.cpp

intel/compiler: Don't propagate cmod into integer multiplies

2017-10-05 11:54:49 -07:00

brw_vec4_copy_propagation.cpp

i965: Support copy propagating of untyped atomic surface indexes.

2017-09-26 15:35:14 -07:00

brw_vec4_cse.cpp

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brw_vec4_dead_code_eliminate.cpp

i965/vec4/dce: improve track of partial flag register writes

2017-04-14 14:56:09 -07:00

brw_vec4_generator.cpp

nir: Get rid of nir_shader::stage

2017-10-20 12:49:17 -07:00

brw_vec4_gs_nir.cpp

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_gs_visitor.cpp

intel/compiler: Remove final_program_size from brw_compile_*

2017-10-31 23:36:54 -07:00

brw_vec4_gs_visitor.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_live_variables.cpp

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brw_vec4_live_variables.h

i965/vec4: consider subregister offset in live variables

2017-04-14 14:56:08 -07:00

brw_vec4_nir.cpp

i965/vec4: remove setting default LOD in the backend

2017-10-20 08:29:53 +02:00

brw_vec4_reg_allocate.cpp

i965/vec4: Return float from spill_cost_for_type()

2017-08-21 14:45:44 -07:00

brw_vec4_surface_builder.cpp

i965/vec4: Fix swizzles on atomic sources.

2017-09-26 15:35:11 -07:00

brw_vec4_surface_builder.h

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brw_vec4_tcs.cpp

intel/compiler: Remove final_program_size from brw_compile_*

2017-10-31 23:36:54 -07:00

brw_vec4_tcs.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_tes.cpp

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_tes.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_visitor.cpp

i965/vec4: remove setting default LOD in the backend

2017-10-20 08:29:53 +02:00

brw_vec4_vs_visitor.cpp

intel/vs: Grow the param array for clip planes

2017-10-12 22:39:30 -07:00

brw_vec4_vs.h

intel: Rewrite the world of push/pull params

2017-10-12 22:39:29 -07:00

brw_vec4.cpp

intel/compiler: Remove final_program_size from brw_compile_*

2017-10-31 23:36:54 -07:00

brw_vec4.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vue_map.c

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brw_wm_iz.cpp

nir: Embed the shader_info in the nir_shader again

2017-05-09 15:07:47 -07:00

gen6_gs_visitor.cpp

i965: Move SOL PSIZ hacks from draw time to link time.

2017-06-01 00:08:29 -07:00

gen6_gs_visitor.h

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intel_asm_annotation.c

i965: Add a weak no-op nir_print_instr() symbol

2017-05-15 11:43:01 -07:00

intel_asm_annotation.h

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meson.build

meson: extract out variable for nir_algebraic.py

2017-10-24 15:33:40 -04:00

test_eu_compact.cpp

i965: Remove CONT/BREAK from instruction compaction test

2017-08-21 14:05:23 -07:00

test_eu_validate.cpp

i965: Validate "Special Requirements for Handling Double Precision Data Types"

2017-10-04 14:08:54 -07:00

test_fs_cmod_propagation.cpp

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test_fs_copy_propagation.cpp

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test_fs_saturate_propagation.cpp

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test_vec4_cmod_propagation.cpp

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test_vec4_copy_propagation.cpp

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test_vec4_register_coalesce.cpp

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test_vf_float_conversions.cpp

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