Files
mesa/src
Rafael Antognolli e20830db96 i965/gen10: Change the order of PIPE_CONTROL and load register.
I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
come right after the 3DSTATE_SAMPLE_PATTERN.

This fixes GPU hangs in the i965 initial state batchbuffer when running
some Piglit tests with always_flush_batch=true.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-12-01 11:27:27 -08:00
..
2016-08-31 17:06:54 -07:00
2017-10-09 13:42:44 -07:00
2017-11-28 14:06:33 -08:00