Jesse Natalie cd0cff951a nir_lower_mem_access_bit_sizes: Fix write-mask-constrained 3-byte stores as atomics
The code here handled stores of actual 3-byte values (8-bit, 3-component), but didn't
correctly handle stores of larger 8-bit vectors that were constrained by write mask to
just 3 bytes. In that case, the pad-to-vec4 step was unnecessary and problematic.

Seen in CL CTS test_basic vector_swizzle test group for char3 with CLOn12.

Fixes: c70d94a8 ("nir_lower_mem_access_bit_sizes: Support unaligned stores via a pair of atomics")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26034>
2023-11-14 21:10:30 +00:00
2022-11-22 19:04:13 +00:00
2023-11-07 06:37:00 +00:00
2023-11-02 11:37:46 +00:00
2022-11-21 23:09:30 +00:00
2023-11-14 00:48:15 +00:00
2023-10-25 19:56:42 +00:00

`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
======================================================


Source
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