Pavel Ondračka
cc7ce6c01f
This is safe to do in all circumstances due to the age of the hardware. (we don't have UBOs, just constant registers with automatic OOB checks) R500 hardware doesn't have standard adress register in fragment shaders and while we have the loop register which we in theory can use for indirect access, this is currently not possible to wire through NIR. So anytime there is an indirect uniform array access in a loop, we end with a if ladder with size depending on the size of the uniform array. The two worst behaving apps here are glamor and some GTK shaders, both of which are sometimes ending over the 512 instructions limit. Flattening the if ladders helps a LOT, so we can get into the instruction limit in most cases (all glamor shaders are OK now). So just enable the flattening by setting all load_ubo_vec4 with ACCESS_CAN_SPECULATE. Shader-db RV530: total instructions in shared programs: 128762 -> 128440 (-0.25%) instructions in affected programs: 540 -> 218 (-59.63%) helped: 3 HURT: 0 total temps in shared programs: 17543 -> 17550 (0.04%) temps in affected programs: 11 -> 18 (63.64%) helped: 0 HURT: 3 total cycles in shared programs: 196984 -> 196657 (-0.17%) cycles in affected programs: 592 -> 265 (-55.24%) helped: 3 HURT: 0 LOST: 0 GAINED: 7 No changes for R300/R400 because there we don't have control flow anyway. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6366 Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26877>
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