Ian Romanick bac10ef4aa intel/fs: Add DP4A to get_lowered_simd_width
While working on cooperative matrix support, I noticed some invalid
DP4A instructions being generated.

    dp4a(32)    g33<1>UD    g21<8,8,1>UD    g1.0<0,1,0>UD   g9<1,1,1>UD

This violates the constraint that the destination or a source can only
access two consecutive GRFs.

I'm a little surprised that validation didn't catch this. Perhaps
because it's a 3 source instruction? Either way, it seems like a bigger
project to fix that.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 0f809dbf40 ("intel/compiler: Basic support for DP4A instruction")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25554>
2023-10-07 02:27:53 +00:00
2022-11-22 19:04:13 +00:00
2023-10-04 20:50:34 +00:00
2022-01-19 15:17:17 +00:00
2022-11-21 23:09:30 +00:00
2023-09-26 05:05:26 +00:00
2023-07-12 11:13:17 -07:00

`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
======================================================


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