Kenneth Graunke 788c49ecc6 brw: Extend load_urb/store_urb to handle 32-bit non-vec4-aligned access
(Based on the original implementation by Lionel Landwerlin, but adapted
to my respun URB lowering framework.)

The mesh shader URB payload requires reading and writing fields at
arbitrary DWord offsets.  For example, the Primitive Indices array
starts at DWord 1, and it can be a vec1[], vec2[], or vec3[] array,
leading to very unaligned and sometimes double-parked elements.

Still, most fields are still conveniently vec4-aligned.

To handle this, we add a new cb_data::vec4_access flag.  If set, access
remains in vec4 units, with vec4 alignment.  We use this for non-mesh
stages.  When unset, offset is in 32-bit units, allowing unaligned
DWord access.

This is trivial to support on Xe2, where the LSC URB messages support
arbitrary byte-aligned addressing.  On older platforms, we have to
convert this to vec4 aligned offsets plus a component offset (either
returning a subset of the channels loaded, or using component masking
to store a subset of a vec4/vec8).

Thankfully, since the OWord URB messages support accessing a vec8 at
a time, this means we can do any vec4 access in one message, even if
it's double-parked.  We use mod-analysis to see if we can statically
determine the sub-vec4 component offset required (we often can).  If
not, we use the ability to have dynamic writemasks to sort it out.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38918>
2025-12-16 00:58:38 +00:00
2025-02-23 00:31:59 +01:00
2025-12-12 20:35:35 +00:00
2025-01-08 20:37:51 +00:00
2025-11-14 19:31:17 +00:00
2025-11-03 22:08:48 +00:00
2025-10-21 02:28:09 +00:00
2024-11-18 22:29:14 +00:00
2025-10-16 03:31:58 +00:00

`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
======================================================


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