Iago Toral Quiroga 6c418dfa42 intel/compiler: fix node interference of simd16 instructions
SIMD16 instructions need to have additional interferences to prevent
source / destination hazards when the source and destination registers
are off by one register.

While we already have code to handle this, it was only running for SIMD16
dispatches, however, we can have SIDM16 instructions in a SIMD8 dispatch.
An example of this are pull constant loads since commit b56fa830c6,
but there are more cases.

This fixes a number of CTS test failures found in work-in-progress
tests that were hitting this situation for 16-wide pull constants
in a SIMD8 program.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-11-09 08:22:08 +01:00
2018-10-31 19:15:50 +00:00
2016-08-30 16:44:00 -04:00
2017-09-06 17:48:50 +01:00
2018-11-01 00:05:43 +00:00
2018-08-16 13:52:56 -07:00
2018-11-01 18:54:02 +00:00

`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
======================================================


Source
------

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Other repositories are likely forks, and code found there is not supported.


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Build & install
---------------

You can find more information in our documentation (`docs/install.html
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Meson (`docs/meson.html <https://mesa3d.org/meson.html>`_):

.. code-block:: sh

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  $ cd build
  $ meson ..
  $ sudo ninja install


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Bug reports
-----------

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Contributing
------------

Contributions are welcome, and step-by-step instructions can be found in our
documentation (`docs/submittingpatches.html
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