Ian Romanick 66dc6e07f5 intel/brw: Fix handling of accumulator register numbers
Folks, there's more than one accumulator. In general, when the
register file is ARF, the upper 4 bits of the register number specify
which ARF, and the lower 4 bits specify which one of that ARF. This
can be further partitioned by the subregister number.

This is already mostly handled correctly for flags register, but lots
of places wanted to check the register number for equality with
BRW_ARF_ACCUMULATOR. If acc1 is ever specified, that won't work.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28281>
2024-03-21 15:12:54 -07:00
2022-11-22 19:04:13 +00:00
2024-03-21 13:26:20 +00:00
2024-03-13 15:21:07 +00:00
2024-03-21 20:11:49 +00:00
2024-01-24 10:02:10 +00:00
2023-11-02 11:37:46 +00:00
2024-01-24 10:53:14 +00:00
2024-01-11 11:05:47 +00:00

`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
======================================================


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