65acc81e9d
Indirect pipeline binds force indirect descriptor sets and this needs
to be in the shader stage key, otherwise two shaders might result in
the same pipeline cache key.
Fixes: b1ba02e707 ("radv: force using indirect descriptor sets for indirect compute pipelines")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30209>
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