Samuel Pitoiset 5f3d3be24a radv: fix indirect dispatches on the compute queue on GFX10.3+ ...

For weird reasons, the COPY_DATA packet doesn't seem to copy anything
while on the compute queue. Instead, use PKT3_LOAD_SH_REG_INDEX which
seems to work as expected.

Note that LOAD_SH_REG_INDEX on the compute queue is only supported by
the CP on GFX10.3, so we need to implement a different solution (load
from the indirect BO in the shader) for older generations.

This should fix the Control RT GPU hang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15053>

2022-03-14 08:54:23 +00:00

..

addrlib

amd: update addrlib

2022-03-01 17:03:00 +00:00

ci

radv/ci: remove unused files

2022-03-08 08:25:34 +01:00

common

amd: add PKT3_LOAD_SH_REG_INDEX

2022-03-14 08:54:23 +00:00

compiler

aco/ra: refactor collect_vars() to return a sorted vector

2022-03-14 08:32:10 +00:00

drm-shim

r300/r600: Add drm-shim support.

2022-02-02 00:59:08 +00:00

llvm

ac/nir: implement nir_op_pack_{uint,sint}_2x16

2022-03-04 08:06:56 +00:00

registers

amd: remove the _UMD suffix from register definitions

2022-02-22 11:41:04 +00:00

vulkan

radv: fix indirect dispatches on the compute queue on GFX10.3+

2022-03-14 08:54:23 +00:00

.clang-format

radv, aco: Add u_foreach_bit to .clang-format.

2022-02-22 14:57:29 +00:00

meson.build

r300/r600: Add drm-shim support.

2022-02-02 00:59:08 +00:00