Paulo Zanoni 5ca224aa0c anv/trtt: make all contexts have the same TR-TT programming
On Gen12 (the oldest we support on Mesa right now for TR-TT) we
started having per-engine TR-TT registers and we are supposed to make
all contexts share the same TR-TT programming.

On LNL+, this is documented in the BSpec page for the TRTT_CNTRL
register (68417), with more details in HSDs 14020454786 and
16022013154.

On Gen12 platforms this information is a little harder to find and
there's a whole trail of HSDs leading up to 1209977595, which links to
the documents that describe the programming. BSpec for TR-TT on Gen12
is very confusing as it still contains registers and other information
from Gen11 that were not removed.

Regarding the additional BLT and COMP registers, please notice that on
the BSpec pages for the TR-TT registers, the "Register Instance"
section only lists the GFX registers as non-privileged. However, the
"User Mode Privileged Commands" lists the other instances of the TR-TT
Regsiters as non-privileged, which matches what we see: there's no
need to put these addresses in the FORCE_TO_NONPRIV registers.

Notice that for now, when TR-TT is being used we only expose a single
queue, so this change effectively does nothing until we start exposing
extra queues. I left that part for later to help bisectability.

v2:
 - s/trtt_init_context_state/trtt_init_queues_state/ (José)
 - pass device as the argument to init_queues_state (José)
v3:
 - use async_submit_end (José)

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30252>
2024-07-22 10:04:34 -07:00
2022-11-22 19:04:13 +00:00
2024-07-20 14:40:23 -05:00
2024-03-13 15:21:07 +00:00
2024-01-24 10:02:10 +00:00
2023-11-02 11:37:46 +00:00
2024-05-13 14:32:12 +00:00
2024-07-19 16:37:23 +00:00

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