Samuel Pitoiset 3c81961c2e radv: enable DCC fast clears for 8bpp/16bpp on GFX11 ...

This was disabled during GFX11 bringup few years ago to follow RadeonSI,
but this is working just fine and RadeonSI also enabled it recently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33756>

2025-02-28 08:33:39 +00:00

..

addrlib

amd: update addrlib

2024-12-26 21:02:21 +00:00

ci

ci/angle: remove USE_ANGLE variable

2025-02-28 01:33:34 +00:00

common

treewide: Switch to nir_progress

2025-02-26 15:19:53 +00:00

compiler

aco/tests: add more tests for chained branches

2025-02-27 10:40:01 +00:00

drm-shim

amd/drm-shim: add GFX1150 support

2024-08-13 13:17:17 +00:00

gmlib

amd/gmlib: add gmlib for radeonsi

2025-02-27 03:15:16 +00:00

llvm

ac: Don't include full nir.h anymore.

2025-02-12 22:33:07 +01:00

registers

amd: Rename GFX1103_R1/R2 to PHOENIX/2

2024-11-20 02:14:40 +00:00

vpelib

amd/vpelib: Shaper Refactor

2024-12-26 01:23:59 +00:00

vulkan

radv: enable DCC fast clears for 8bpp/16bpp on GFX11

2025-02-28 08:33:39 +00:00

meson.build

amd/gmlib: add gmlib for radeonsi

2025-02-27 03:15:16 +00:00