Kenneth Graunke 26bb81f3f6 intel/compiler: Fix uncompaction of signed word immediates on Tigerlake
This expression accidentally performs a 32-bit sign-extension when
processing the second half of the expression (the low 16 bits).

Consider -7W, which is represented as 0xfff9fff9 in our encoding (the
16-bit word is replicated to both halves of the 32-bit dword).

Tigerlake's compaction stores the low 11-bits of an immediate as-is,
and replicates the 12th bit.  So here, compacted_imm will be 0xff9.

   (  (int)(0xff9 << 20) >> 4) |
   ((short)(0xff9 <<  4) >> 4))

   0xfff90000 | (0xff90 >> 4)
   0xfff90000 | 0xfffffff9 ...oops...
   0xfffffff9

By casting the second line of the expression to unsigned short, we
prevent the sign-extension when it combines both parts, so we get:

   0xfff90000 | 0x0000fff9
   0xfff9fff9

Fixes: 12d3b11908 ("intel/compiler: Add instruction compaction support on Gen12")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16833>
2022-06-02 13:59:38 -07:00
2022-06-02 13:09:16 +00:00
2022-06-01 09:08:13 +00:00
2022-01-19 15:17:17 +00:00
2022-05-31 18:32:59 +00:00
2022-04-12 10:42:31 +00:00

`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
======================================================


Source
------

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---------------

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