Ian Romanick 23bd356b42 brw/nir: nir_intrinsic_load_reloc_const_intel may not be scalar [v3]
If the (NIR) destination is a register (i.e., not an SSA value), the
destination of the BRW instruction will not be is_scalar. This occurs in
some shaders in Final Fantasy XVI (and
finalfantasytype0_1.rdc.2826e29da3722a83.1.foz).

If the destination is not is_scalar, revert most of this code to the
state previous to f3593df877. This means

- Allocate a SIMD1 register and UNDEF it.
- Emit a SIMD1 MOV_RELOC_IMM to that register.
- Emit an additional MOV to expand the SIMD1 result.

Closes: #12520
Fixes: f3593df877 ("brw/nir: Treat load_reloc_const_intel as convergent")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37384>
2025-09-29 16:48:07 +00:00
2025-09-26 14:02:52 +00:00
2025-09-16 19:45:15 +00:00
2025-08-31 15:38:27 +00:00
2025-09-26 19:40:45 +00:00
2025-07-16 13:50:24 +00:00

`Mesa <https://mesa3d.org>`_ - The 3D Graphics Library
======================================================


Source
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Other repositories are likely forks, and code found there is not supported.


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.. code-block:: sh

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