Samuel Pitoiset 0ae1cf46a6 radv: fix enabling TC-compat HTILE in GENERAL for writes on GFX10+ ...

It wasn't expected to also enable inside render loops.

Fixes: 4bb92d9145 ("radv: enable TC-compat HTILE in GENERAL on GFX10+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8351>

2021-01-08 09:22:32 +00:00

..

addrlib

amd/addrlib: use cpp.has_argument() to filter compiler arguments

2021-01-05 11:29:11 +00:00

common

ac/sqtt: move radv_get_expected_buffer_size to ac

2021-01-07 10:10:16 +01:00

compiler

radv/llvm,aco: always split typed vertex buffer loads on GFX6 and GFX10+

2021-01-07 17:28:00 +00:00

llvm

ac/nir: use llvm.readcyclecounter for LLVM9+

2021-01-05 10:27:00 +00:00

registers

amd/registers: add missing VRS registers

2020-12-14 16:22:38 +00:00

vulkan

radv: fix enabling TC-compat HTILE in GENERAL for writes on GFX10+

2021-01-08 09:22:32 +00:00

Android.addrlib.mk

android: amd/addrlib: add gfx10 support

2019-07-10 09:03:55 +02:00

Android.common.mk

android: amd/registers: switch to new generated register definitions

2020-09-06 20:20:34 +02:00

Android.compiler.mk

android: aco/isel: Move context initialization code to a dedicated file

2020-09-14 21:26:53 +02:00

Android.mk

android: aco: add support for libmesa_aco

2019-09-28 15:56:34 +02:00

Makefile.sources

ac/radv: move radv_rgp.c to ac

2021-01-07 10:09:49 +01:00

meson.build

aco: add framework for unit testing

2020-07-30 16:13:08 +00:00